mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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371 lines
12 KiB
C
371 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/* SPWTDP - SpaceWire Time Distribution Protocol. The driver provides
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* device discovery and interrupt management.
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*
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* COPYRIGHT (c) 2017.
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* Cobham Gaisler AB
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __SPWTDP_H__
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#define __SPWTDP_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPWTDP_ERR_OK 0
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#define SPWTDP_ERR_EINVAL -1
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#define SPWTDP_ERR_ERROR -2
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#define SPWTDP_ERR_NOINIT -3
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/* Maximum number of SPWTDP devices supported by driver */
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#define SPWTDP_MAX 2
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/* SPWTDP Register layout */
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struct spwtdp_regs {
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volatile uint32_t conf[ 4 ]; /* 0x000-0x00C */
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volatile uint32_t stat[ 4 ]; /* 0x010-0x01C */
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volatile uint32_t cmd_ctrl; /* 0x020 */
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volatile uint32_t cmd_et[ 5 ]; /* 0x024-0x034 */
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volatile uint32_t resv1[ 2 ]; /* 0x038-0x03C */
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volatile uint32_t dat_ctrl; /* 0x040 */
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volatile uint32_t dat_et[ 5 ]; /* 0x044-0x054 */
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volatile uint32_t resv2[ 2 ]; /* 0x058-0x05C */
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volatile uint32_t ts_rx_ctrl; /* 0x060 */
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volatile uint32_t ts_rx_et[ 5 ]; /* 0x064-0x074 */
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volatile uint32_t resv3[ 2 ]; /* 0x078-0x07C */
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volatile uint32_t ts_tx_ctrl; /* 0x080 */
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volatile uint32_t ts_tx_et[ 5 ]; /* 0x084-0x094 */
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volatile uint32_t resv4[ 2 ]; /* 0x098 */
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volatile uint32_t lat_ctrl; /* 0x0A0 */
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volatile uint32_t lat_et[ 5 ]; /* 0x0A4-0x0B4 */
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volatile uint32_t resv5[ 2 ]; /* 0x0B8-0x0BC */
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volatile uint32_t ien; /* 0x0C0 */
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volatile uint32_t ists; /* 0x0C4 */
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volatile uint32_t dlycnt; /* 0x0C8 */
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volatile uint32_t dissync; /* 0x0CC */
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volatile uint32_t resv6[ 12 ]; /* 0x0D0-0x0FC */
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volatile uint32_t edmask[ 4 ]; /* 0x100-0x10C */
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struct {
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volatile uint32_t ctrl; /* 0x110, 0x130, 0x150, 0x170 */
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volatile uint32_t
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et[ 5 ]; /* 0x114-0x124, 0x134-0x144, 0x154-0x164, 0x174-0x184, */
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volatile uint32_t
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resv0[ 2 ]; /* 0x128-0x12C, 0x148-0x14C, 0x168-0x16C, 0x188-0x18C, */
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} edat[ 4 ]; /* 0x110-0x18C */
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volatile uint32_t resv7[ 4 ]; /* 0x190-0x19C */
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volatile uint32_t pulse[ 8 ]; /* 0x1A0-0x1BC */
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volatile uint32_t resv8[ 16 ]; /* 0x1C0-0x1FC */
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};
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/*
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* Configuration register definitions
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*/
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#define CONF0_JE ( 0x1 << CONF0_JE_BIT )
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#define CONF0_ST ( 0x1 << CONF0_ST_BIT )
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#define CONF0_EP ( 0x1 << CONF0_EP_BIT )
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#define CONF0_ET ( 0x1 << CONF0_ET_BIT )
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#define CONF0_SP ( 0x1 << CONF0_SP_BIT )
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#define CONF0_SE ( 0x1 << CONF0_SE_BIT )
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#define CONF0_LE ( 0x1 << CONF0_LE_BIT )
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#define CONF0_AE ( 0x1 << CONF0_AE_BIT )
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#define CONF0_MAP ( 0x1f << CONF0_MAP_BIT )
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#define CONF0_TD ( 0x1 << CONF0_TD_BIT )
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#define CONF0_MU ( 0x1 << CONF0_MU_BIT )
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#define CONF0_SEL ( 0x3 << CONF0_SEL_BIT )
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#define CONF0_ME ( 0x1 << CONF0_ME_BIT )
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#define CONF0_RE ( 0x1 << CONF0_RE_BIT )
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#define CONF0_TE ( 0x1 << CONF0_TE_BIT )
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#define CONF0_RS ( 0x1 << CONF0_RS_BIT )
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#define CONF0_JE_BIT 24
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#define CONF0_ST_BIT 21
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#define CONF0_EP_BIT 20
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#define CONF0_ET_BIT 19
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#define CONF0_SP_BIT 18
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#define CONF0_SE_BIT 17
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#define CONF0_LE_BIT 16
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#define CONF0_AE_BIT 15
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#define CONF0_MAP_BIT 8
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#define CONF0_TD_BIT 7
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#define CONF0_MU_BIT 6
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#define CONF0_SEL_BIT 4
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#define CONF0_ME_BIT 3
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#define CONF0_RE_BIT 2
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#define CONF0_TE_BIT 1
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#define CONF0_RS_BIT 0
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#define CONF1_FSINC ( 0x3fffffff << CONF1_FSINC_BIT )
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#define CONF1_FSINC_BIT 0
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#define CONF2_CV ( 0xffffff << CONF2_CV_BIT )
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#define CONF2_ETINC ( 0xff << CONF2_ETINC_BIT )
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#define CONF2_CV_BIT 8
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#define CONF2_ETINC_BIT 0
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#define CONF3_OUTPORT ( 0xf << CONF3_OUTPORT_BIT )
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#define CONF3_INPORT ( 0xf << CONF3_INPORT_BIT )
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#define CONF3_STM ( 0x3f << CONF3_STM_BIT )
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#define CONF3_DI64R ( 0x1 << CONF3_DI64R_BIT )
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#define CONF3_DI64T ( 0x1 << CONF3_DI64T_BIT )
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#define CONF3_DI64 ( 0x1 << CONF3_DI64_BIT )
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#define CONF3_DI ( 0x1 << CONF3_DI_BIT )
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#define CONF3_INRX ( 0x1f << CONF3_INRX_BIT )
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#define CONF3_INTX ( 0x1f << CONF3_INTX_BIT )
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#define CONF3_OUTPORT_BIT 28
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#define CONF3_INPORT_BIT 24
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#define CONF3_STM_BIT 16
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#define CONF3_DI64R_BIT 13
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#define CONF3_DI64T_BIT 12
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#define CONF3_DI64_BIT 11
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#define CONF3_DI_BIT 10
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#define CONF3_INRX_BIT 5
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#define CONF3_INTX_BIT 0
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/*
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* Control register definitions
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*/
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#define CTRL_NC ( 0x1 << CTRL_NC_BIT )
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#define CTRL_IS ( 0x1 << CTRL_IS_BIT )
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#define CTRL_SPWTC ( 0xff << CTRL_SPWTC_BIT )
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#define CTRL_CPF ( 0xffff << CTRL_CPF_BIT )
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#define CTRL_NC_BIT 31
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#define CTRL_IS_BIT 30
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#define CTRL_SPWTC_BIT 16
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#define CTRL_CPF_BIT 0
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/*
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* Interrupt register definition
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*/
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#define SPWTDP_IRQ_S ( 0x1 << SPWTDP_IRQ_S_BIT )
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#define SPWTDP_IRQ_TR ( 0x1 << SPWTDP_IRQ_TR_BIT )
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#define SPWTDP_IRQ_TM ( 0x1 << SPWTDP_IRQ_TM_BIT )
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#define SPWTDP_IRQ_TT ( 0x1 << SPWTDP_IRQ_TT_BIT )
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#define SPWTDP_IRQ_DIR ( 0x1 << SPWTDP_IRQ_DIR_BIT )
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#define SPWTDP_IRQ_DIT ( 0x1 << SPWTDP_IRQ_DIT_BIT )
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#define SPWTDP_IRQ_EDI0 ( 0x1 << SPWTDP_IRQ_EDI0_BIT )
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#define SPWTDP_IRQ_EDI1 ( 0x1 << SPWTDP_IRQ_EDI1_BIT )
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#define SPWTDP_IRQ_EDI2 ( 0x1 << SPWTDP_IRQ_EDI2_BIT )
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#define SPWTDP_IRQ_EDI3 ( 0x1 << SPWTDP_IRQ_EDI3_BIT )
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#define SPWTDP_IRQ_SET ( 0x1 << SPWTDP_IRQ_SET_BIT )
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#define SPWTDP_IRQ_P0 ( 0x1 << SPWTDP_IRQ_P0_BIT )
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#define SPWTDP_IRQ_P1 ( 0x1 << SPWTDP_IRQ_P1_BIT )
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#define SPWTDP_IRQ_P2 ( 0x1 << SPWTDP_IRQ_P2_BIT )
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#define SPWTDP_IRQ_P3 ( 0x1 << SPWTDP_IRQ_P3_BIT )
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#define SPWTDP_IRQ_P4 ( 0x1 << SPWTDP_IRQ_P4_BIT )
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#define SPWTDP_IRQ_P5 ( 0x1 << SPWTDP_IRQ_P5_BIT )
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#define SPWTDP_IRQ_P6 ( 0x1 << SPWTDP_IRQ_P6_BIT )
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#define SPWTDP_IRQ_P7 ( 0x1 << SPWTDP_IRQ_P7_BIT )
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#define SPWTDP_IRQ_NCTC ( 0x1 << SPWTDP_IRQ_NCTC_BIT )
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#define SPWTDP_IRQ_WCLEAR \
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( SPWTDP_IRQ_S | SPWTDP_IRQ_TR | SPWTDP_IRQ_TM | SPWTDP_IRQ_TT | \
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SPWTDP_IRQ_DIR | SPWTDP_IRQ_DIT | SPWTDP_IRQ_EDI0 | SPWTDP_IRQ_EDI1 | \
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SPWTDP_IRQ_EDI2 | SPWTDP_IRQ_EDI3 | SPWTDP_IRQ_SET | SPWTDP_IRQ_P0 | \
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SPWTDP_IRQ_P1 | SPWTDP_IRQ_P2 | SPWTDP_IRQ_P3 | SPWTDP_IRQ_P4 | \
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SPWTDP_IRQ_P5 | SPWTDP_IRQ_P6 | SPWTDP_IRQ_P7 | SPWTDP_IRQ_NCTC )
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#define SPWTDP_IRQ_ALL ( SPWTDP_IRQ_WCLEAR )
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#define SPWTDP_IRQ_S_BIT 0
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#define SPWTDP_IRQ_TR_BIT 1
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#define SPWTDP_IRQ_TM_BIT 2
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#define SPWTDP_IRQ_TT_BIT 3
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#define SPWTDP_IRQ_DIR_BIT 4
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#define SPWTDP_IRQ_DIT_BIT 5
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#define SPWTDP_IRQ_EDI0_BIT 6
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#define SPWTDP_IRQ_EDI1_BIT 7
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#define SPWTDP_IRQ_EDI2_BIT 8
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#define SPWTDP_IRQ_EDI3_BIT 9
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#define SPWTDP_IRQ_SET_BIT 10
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#define SPWTDP_IRQ_P0_BIT 11
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#define SPWTDP_IRQ_P1_BIT 12
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#define SPWTDP_IRQ_P2_BIT 13
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#define SPWTDP_IRQ_P3_BIT 14
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#define SPWTDP_IRQ_P4_BIT 15
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#define SPWTDP_IRQ_P5_BIT 16
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#define SPWTDP_IRQ_P6_BIT 17
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#define SPWTDP_IRQ_P7_BIT 18
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#define SPWTDP_IRQ_NCTC_BIT 19
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/* Register the SPWTDP Driver to the Driver Manager */
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void spwtdp_register_drv( void );
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/* Open a SPWTDP device by registration order index. A SPWTDP device can only by
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* opened once. The handle returned must be used as the input parameter 'spwtdp'
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* in the rest of the calls in the function interface.
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*/
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extern void *spwtdp_open( int dev_no );
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/* Close a previously opened SPWTDP device */
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extern int spwtdp_close( void *spwtdp );
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/* Reset SPWTDP Core */
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extern int spwtdp_reset( void *spwtdp );
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/* Setup the frequency configuration registers */
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extern int spwtdp_freq_setup(
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void *spwtdp,
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uint32_t fsinc,
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uint32_t cv,
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uint8_t etinc
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);
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/* Unmask Interrupts at Interrupt controller */
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extern int spwtdp_interrupt_unmask( void *spwtdp, uint32_t irqmask );
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/* Mask Interrupts at Interrupt controller */
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extern int spwtdp_interrupt_mask( void *spwtdp, uint32_t irqmask );
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/* Function ISR callback prototype
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*
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* ists - Interrupt STatus register of the SPWTDP core read by ISR
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* data - Custom data provided by user
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*/
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typedef void ( *spwtdp_isr_t )( unsigned int ists, void *data );
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/* Register an Interrupt handler and custom data, the function call is
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* removed by calling unregister function.
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*/
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extern int spwtdp_isr_register( void *spwtdp, spwtdp_isr_t isr, void *data );
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/* Unregister an Interrupt handler */
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extern int spwtdp_isr_unregister( void *spwtdp );
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/* Get and clear interrupt status */
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extern int spwtdp_interrupt_status(
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void *spwtdp,
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uint32_t *sts,
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uint32_t clrmask
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);
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/* Setup Initiator and target */
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#define SPWTDP_TDP_ENABLE CONF0_TD
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#define SPWTDP_TDP_DISABLE 0
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#define SPWTDP_LATENCY_ENABLE CONF0_LE
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#define SPWTDP_LATENCY_DISABLE 0
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#define SPWTDP_EXTET_INC_POLARITY_RISING CONF0_EP
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#define SPWTDP_EXTET_INC_POLARITY_FALLING 0
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#define SPWTDP_EXTET_INC_ENABLE CONF0_ET
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#define SPWTDP_EXTET_INC_DISABLE 0
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#define SPWTDP_EXTET_POLARITY_RISING CONF0_SP
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#define SPWTDP_EXTET_POLARITY_FALLING 0
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#define SPWTDP_EXTET_ENABLE CONF0_SE
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#define SPWTDP_EXTET_DISABLE 0
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#define SPWTDP_TARGET_SPWSYNC_ENABLE CONF0_ST
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#define SPWTDP_TARGET_SPWSYNC_DISABLE 0
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#define SPWTDP_TARGET_JITTERC_ENABLE CONF0_JE
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#define SPWTDP_TARGET_JITTERC_DISABLE 0
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#define SPWTDP_TARGET_MITIGATION_ENABLE CONF0_ME
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#define SPWTDP_TARGET_MITIGATION_DISABLE 0
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extern int spwtdp_initiator_conf(
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void *spwtdp,
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uint8_t mapping,
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uint32_t options
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);
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extern int spwtdp_target_conf(
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void *spwtdp,
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uint8_t mapping,
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uint32_t options
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);
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/* Setup Initiator and target dist interrupts */
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extern int spwtdp_initiator_int_conf(
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void *spwtdp,
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uint8_t stm,
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uint8_t inrx,
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uint8_t intx
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);
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#define SPWTDP_TARGET_DISTINT_INTACK CONF3_DI
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#define SPWTDP_TARGET_DISTINT_INT 0
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extern int spwtdp_target_int_conf(
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void *spwtdp,
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uint8_t inrx,
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uint8_t intx,
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uint32_t options
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);
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/* Enable Initiator and target */
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extern int spwtdp_initiator_enable( void *spwtdp );
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extern int spwtdp_target_enable( void *spwtdp );
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/* Disable Initiator and target */
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extern int spwtdp_initiator_disable( void *spwtdp );
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extern int spwtdp_target_disable( void *spwtdp );
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/* Get and clear status */
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extern int spwtdp_status( void *spwtdp, uint32_t *sts, uint32_t clrmask );
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/* Define time struct */
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/* Length of the max data sample (136 bits), aligned to the next 32-bit word
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* (160 bits=20 byte=5 words)
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*/
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#define SPWTDP_TIME_DATA_LENGTH 20
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struct spwtdp_time_t {
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uint8_t data[ SPWTDP_TIME_DATA_LENGTH ];
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uint32_t preamble;
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};
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typedef struct spwtdp_time_t spwtdp_time_t;
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/* Get datation elapsed time */
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extern int spwtdp_dat_et_get( void *spwtdp, spwtdp_time_t *val );
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extern int spwtdp_tsrx_et_get( void *spwtdp, spwtdp_time_t *val );
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extern int spwtdp_tstx_et_get( void *spwtdp, spwtdp_time_t *val );
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extern int spwtdp_lat_et_get( void *spwtdp, spwtdp_time_t *val );
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extern int spwtdp_cmd_et_get( void *spwtdp, spwtdp_time_t *val );
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/* Configure TSTX */
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extern int spwtdp_initiator_tstx_conf( void *spwtdp, uint8_t tstc );
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/* Manage control register */
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extern int spwtdp_initiator_cmd_et_set( void *spwtdp, spwtdp_time_t val );
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extern int spwtdp_initiator_cmd_spwtc_set( void *spwtdp, uint8_t spwtc );
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#define SPWTDP_TARGET_CTRL_NEWCOMMAND_ENABLE CTRL_NC
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#define SPWTDP_TARGET_CTRL_NEWCOMMAND_DISABLE 0
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#define SPWTDP_TARGET_CTRL_INIT CTRL_IS
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#define SPWTDP_TARGET_CTRL_SYNC 0
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extern int spwtdp_target_cmd_conf(
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void *spwtdp,
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uint8_t spwtc,
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uint16_t cpf,
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uint32_t options
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);
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/* Get precision */
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extern int spwtdp_precision_get(
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void *spwtdp,
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uint8_t *fine,
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uint8_t *coarse
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);
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#ifdef __cplusplus
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}
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#endif
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#endif
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