Sebastian Huber 9fbe0c70e8 bsps/mips: Add the Malta interrupt controller
The BSP linked the stubs of bsps/mips/shared/irq/irqstubs.c, so
rtems_interrupt_raise(), rtems_interrupt_clear(),
rtems_interrupt_is_pending() and rtems_interrupt_vector_enable()
returned RTEMS_UNSATISFIED or did nothing for every vector.
RtemsIntrReqEntryInstall scanned for a vector which it can raise,
found none and used the vector count as a vector.  Every directive
then returned RTEMS_INVALID_ID.  ts-validation-intr reported 638
failed steps from this alone.

The dispatcher of the BSP printed a line for six of the eight sources
of the processor.  It did not pass them to the interrupt manager, so a
handler of them was never called.

Give the BSP its own implementation.  The two software interrupts of
the processor carry raise and clear through the cause register.  The
mask of the status register carries enable and disable of the sources
of the processor.  The cascade of the south bridge carries them for
its own lines.  The dispatcher passes every source of the processor to
the interrupt manager and keeps the decode of the south bridge.

The base of that implementation needs three repairs.  Each vector
number expands to a sum with no brackets around it.  A subtraction of
one therefore adds the terms of the sum.
BSP_irq_enabled_at_i8259s() returns a bitwise complement which is
never zero.  Eight vectors name address and data lines of the PCI
bus.  Such a line reaches the processor through the south bridge.

Bracket every vector number.  Return whether the cache bit is clear.
Remove the eight vectors of the PCI bus and the four aliases which
name them.  Replace the note which describes the interrupt controller
of another board with the order of the vectors.

Update #5742.

Assisted-by: Claude:claude-opus-5 claude-code
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2026-09-21 20:02:55 -05:00
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Real-Time Executive for Multiprocessing Systems

RTEMS is a real-time executive (kernel) which provides a high performance environment for embedded applications with the following features:

  • Standards based user interfaces.
  • Multitasking capabilities.
  • Homogeneous and heterogeneous multiprocessor systems.
  • Symmetric Multiprocessing (SMP):
    • Cluster scheduling: Job-level fixed prority scheduler (EDF) with support for one-to-one and one-to-all thread to processor affinities.
    • Locking protocols with transitive priority inheritance, priority ceiling, MRsP and OMIP.
  • Event-driven, priority-based, preemptive scheduling.
  • Scalable timer and timeout support.
  • Optional rate monotonic scheduling.
  • Intertask communication and synchronisation.
  • Priority inheritance.
  • Responsive interrupt management.
  • Dynamic memory allocation.
  • Dynamic code loading using run-time link editing.
  • File systems, IMFS, FAT, RFS, JFFS, NSFv4 (with LibBSD)
  • High level of user configurability.
  • Link-time configurable schedulers.
  • Linker-set based initialization (similar to global C++ constructors).
  • Drivers for I2C, SPI and LibBSD has NIC, USB, SD/MMC and Framebuffer.
  • Open source with a friendly user license.

RTEMS Project:

Project git repositories are located at:

Online documentation is available at:

RTEMS Doxygen for CPUKit:

RTEMS POSIX 1003.1 Compliance Guide:

RTEMS Discourse User forum for questions, answers and examples:

RTEMS Discord for support:

RTEMS Mailing Lists for general purpose use the users list and for developers use the devel list.

The version number for this software in releases is located in the VERSION file if present.

S
Description
RTEMS is a ​real-time executive in use by embedded systems applications around the world and beyond
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