mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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388 lines
15 KiB
C
388 lines
15 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/* GR1553B driver, used by BC, RT and/or BM driver
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*
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* COPYRIGHT (c) 2010.
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* Cobham Gaisler AB.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* OVERVIEW
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* ========
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* This driver controls the GR1553B device regardless of interfaces supported
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* (BC, RT and/or BM). The device can be located at an on-chip AMBA or an
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* AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM
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* drivers to use. Since the different interfaces are accessed over the same
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* register interface on the same core, the other drivers must share a GR1553B
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* device. Any combination of interface functionality is supported, but the RT
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* and BC functionality can nnot be used simultaneously due to hardware
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* limitation.
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*
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*/
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#ifndef __GR1553B_H__
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#define __GR1553B_H__
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The GR1553B registers */
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struct gr1553b_regs {
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/* Common Registers */
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volatile uint32_t irq; /* 0x00 IRQ register */
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volatile uint32_t imask; /* 0x04 IRQ enable mask */
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int unused0[ ( 0x10 - 0x08 ) / 4 ];
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volatile uint32_t hwcfg; /* 0x10 HW config register */
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int unused1[ ( 0x40 - 0x14 ) / 4 ]; /* Padding */
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/* BC Registers */
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volatile uint32_t bc_stat; /* 0x40 BC status */
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volatile uint32_t bc_ctrl; /* 0x44 BC Action register */
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volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */
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volatile uint32_t bc_abd; /* 0x4c BC async list pointer */
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volatile uint32_t bc_timer; /* 0x50 BC timer register */
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volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */
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volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */
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volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */
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int unused2[ ( 0x68 - 0x60 ) / 4 ]; /* Padding */
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volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */
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volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */
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int unused3[ ( 0x80 - 0x70 ) / 4 ]; /* Padding */
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/* RT Registers */
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volatile uint32_t rt_stat; /* 0x80 RT status */
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volatile uint32_t rt_cfg; /* 0x84 RT config register */
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volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */
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volatile uint32_t rt_statw; /* 0x8c RT status words */
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volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */
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volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */
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volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */
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int unused4[ ( 0xa4 - 0x9c ) / 4 ];
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volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */
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int unused5; /* 0xa8 RESERVED */
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volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */
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volatile uint32_t rt_evlog; /* 0xb0 RT event log position */
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volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */
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int unused6[ ( 0xc0 - 0xb8 ) / 4 ]; /* Padding */
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/* BM Registers */
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volatile uint32_t bm_stat; /* 0xc0 BM status */
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volatile uint32_t bm_ctrl; /* 0xc4 BM control register */
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volatile uint32_t bm_adr; /* 0xc8 BM address filter */
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volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */
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volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */
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volatile uint32_t bm_start; /* 0xd4 BM log start address */
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volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */
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volatile uint32_t bm_pos; /* 0xdc BM log position */
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volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */
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};
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#define GR1553BC_KEY 0x15520000
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#define GR1553RT_KEY 0x15530000
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/* IRQ Definitions */
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#define GR1553BC_IRQLOG_SIZE 64
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#define GR1553BC_IRQLOG_CNT ( GR1553BC_IRQLOG_SIZE / sizeof( uint32_t ) )
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/*** IRQ Flag Register ***/
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#define GR1553B_IRQ_BCEV_BIT 0
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#define GR1553B_IRQ_BCD_BIT 1
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#define GR1553B_IRQ_BCWK_BIT 2
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#define GR1553B_IRQ_RTEV_BIT 8
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#define GR1553B_IRQ_RTD_BIT 9
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#define GR1553B_IRQ_RTTE_BIT 10
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#define GR1553B_IRQ_BMD_BIT 16
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#define GR1553B_IRQ_BMTOF_BIT 17
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#define GR1553B_IRQ_BCEV ( 1 << GR1553B_IRQ_BCEV_BIT )
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#define GR1553B_IRQ_BCD ( 1 << GR1553B_IRQ_BCD_BIT )
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#define GR1553B_IRQ_BCWK ( 1 << GR1553B_IRQ_BCWK_BIT )
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#define GR1553B_IRQ_RTEV ( 1 << GR1553B_IRQ_RTEV_BIT )
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#define GR1553B_IRQ_RTD ( 1 << GR1553B_IRQ_RTD_BIT )
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#define GR1553B_IRQ_RTTE ( 1 << GR1553B_IRQ_RTTE_BIT )
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#define GR1553B_IRQ_BMD ( 1 << GR1553B_IRQ_BMD_BIT )
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#define GR1553B_IRQ_BMTOF ( 1 << GR1553B_IRQ_BMTOF_BIT )
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/*** IRQ Enable Register ***/
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#define GR1553B_IRQEN_BCEVE_BIT 0
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#define GR1553B_IRQEN_BCDE_BIT 1
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#define GR1553B_IRQEN_BCWKE_BIT 2
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#define GR1553B_IRQEN_RTEVE_BIT 8
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#define GR1553B_IRQEN_RTDE_BIT 9
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#define GR1553B_IRQEN_RTTEE_BIT 10
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#define GR1553B_IRQEN_BMDE_BIT 16
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#define GR1553B_IRQEN_BMTOE_BIT 17
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#define GR1553B_IRQEN_BCEVE ( 1 << GR1553B_IRQEN_BCEVE_BIT )
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#define GR1553B_IRQEN_BCDE ( 1 << GR1553B_IRQEN_BCDE_BIT )
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#define GR1553B_IRQEN_BCWKE ( 1 << GR1553B_IRQEN_BCWKE_BIT )
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#define GR1553B_IRQEN_RTEVE ( 1 << GR1553B_IRQEN_RTEVE_BIT )
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#define GR1553B_IRQEN_RTDE ( 1 << GR1553B_IRQEN_RTDE_BIT )
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#define GR1553B_IRQEN_RTTEE ( 1 << GR1553B_IRQEN_RTTEE_BIT )
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#define GR1553B_IRQEN_BMDE ( 1 << GR1553B_IRQEN_BMDE_BIT )
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#define GR1553B_IRQEN_BMTOE ( 1 << GR1553B_IRQEN_BMTOE_BIT )
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/*** BC Status Register ***/
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#define GR1553B_BC_STAT_SCST_BIT 0
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#define GR1553B_BC_STAT_SCADL_BIT 3
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#define GR1553B_BC_STAT_ASST_BIT 8
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#define GR1553B_BC_STAT_ASADL_BIT 11
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#define GR1553B_BC_STAT_BCSUP_BIT 31
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#define GR1553B_BC_STAT_SCST ( 0x3 << GR1553B_BC_STAT_SCST_BIT )
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#define GR1553B_BC_STAT_SCADL ( 0x1f << GR1553B_BC_STAT_SCADL_BIT )
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#define GR1553B_BC_STAT_ASST ( 0x3 << GR1553B_BC_STAT_ASST_BIT )
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#define GR1553B_BC_STAT_ASADL ( 0x1f << GR1553B_BC_STAT_ASADL_BIT )
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#define GR1553B_BC_STAT_BCSUP ( 1 << GR1553B_BC_STAT_BCSUP_BIT )
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/*** BC Action Register ***/
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#define GR1553B_BC_ACT_SCSRT_BIT 0
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#define GR1553B_BC_ACT_SCSUS_BIT 1
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#define GR1553B_BC_ACT_SCSTP_BIT 2
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#define GR1553B_BC_ACT_SETT_BIT 3
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#define GR1553B_BC_ACT_CLRT_BIT 4
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#define GR1553B_BC_ACT_ASSRT_BIT 8
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#define GR1553B_BC_ACT_ASSTP_BIT 9
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#define GR1553B_BC_ACT_BCKEY_BIT 16
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#define GR1553B_BC_ACT_SCSRT ( 1 << GR1553B_BC_ACT_SCSRT_BIT )
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#define GR1553B_BC_ACT_SCSUS ( 1 << GR1553B_BC_ACT_SCSUS_BIT )
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#define GR1553B_BC_ACT_SCSTP ( 1 << GR1553B_BC_ACT_SCSTP_BIT )
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#define GR1553B_BC_ACT_SETT ( 1 << GR1553B_BC_ACT_SETT_BIT )
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#define GR1553B_BC_ACT_CLRT ( 1 << GR1553B_BC_ACT_CLRT_BIT )
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#define GR1553B_BC_ACT_ASSRT ( 1 << GR1553B_BC_ACT_ASSRT_BIT )
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#define GR1553B_BC_ACT_ASSTP ( 1 << GR1553B_BC_ACT_ASSTP_BIT )
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#define GR1553B_BC_ACT_BCKEY ( 0xffff << GR1553B_BC_ACT_BCKEY_BIT )
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/*** BC Timer Register ***/
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#define GR1553B_BC_TIMER_SCTM_BIT 0
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#define GR1553B_BC_TIMER_SCTM ( 0xffffff << GR1553B_BC_TIMER_SCTM_BIT )
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/*** BC Wake-up control Register ***/
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#define GR1553B_BC_WAKE_TIME_BIT 0
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#define GR1553B_BC_WAKE_WKEN_BIT 31
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#define GR1553B_BC_WAKE_TIME ( 0xffffff << GR1553B_BC_WAKE_TIME_BIT )
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#define GR1553B_BC_WAKE_WKEN ( 1 < GR1553B_BC_WAKE_WKEN_BIT )
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/*** RT status Register ***/
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#define GR1553B_RT_STAT_RUN_BIT 0
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#define GR1553B_RT_STAT_SHDB_BIT 1
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#define GR1553B_RT_STAT_SHDA_BIT 2
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#define GR1553B_RT_STAT_ACT_BIT 3
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#define GR1553B_RT_STAT_RTSUP_BIT 31
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#define GR1553B_RT_STAT_RUN ( 1 << GR1553B_RT_STAT_RUN_BIT )
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#define GR1553B_RT_STAT_SHDB ( 1 << GR1553B_RT_STAT_SHDB_BIT )
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#define GR1553B_RT_STAT_SHDA ( 1 << GR1553B_RT_STAT_SHDA_BIT )
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#define GR1553B_RT_STAT_ACT ( 1 << GR1553B_RT_STAT_ACT_BIT )
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#define GR1553B_RT_STAT_RTSUP ( 1 << GR1553B_RT_STAT_RTSUP_BIT )
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/*** RT Config Register ***/
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#define GR1553B_RT_CFG_RTEN_BIT 0
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#define GR1553B_RT_CFG_RTADDR_BIT 1
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#define GR1553B_RT_CFG_RTKEY_BIT 16
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#define GR1553B_RT_CFG_RTEN ( 1 << GR1553B_RT_CFG_RTEN_BIT )
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#define GR1553B_RT_CFG_RTADDR ( 1 << GR1553B_RT_CFG_RTADDR_BIT )
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#define GR1553B_RT_CFG_RTKEY ( 0xffff << GR1553B_RT_CFG_RTKEY_BIT )
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/*** RT Bus Status Register ***/
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#define GR1553B_RT_STAT2_TFLG_BIT 0
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#define GR1553B_RT_STAT2_DBCA_BIT 1
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#define GR1553B_RT_STAT2_SSF_BIT 2
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#define GR1553B_RT_STAT2_BUSY_BIT 3
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#define GR1553B_RT_STAT2_SREQ_BIT 4
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#define GR1553B_RT_STAT2_TFDE_BIT 8
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#define GR1553B_RT_STAT2_TFLG ( 1 << GR1553B_RT_STAT2_TFLG_BIT )
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#define GR1553B_RT_STAT2_DBCA ( 1 << GR1553B_RT_STAT2_DBCA_BIT )
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#define GR1553B_RT_STAT2_SSF ( 1 << GR1553B_RT_STAT2_SSF_BIT )
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#define GR1553B_RT_STAT2_BUSY ( 1 << GR1553B_RT_STAT2_BUSY_BIT )
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#define GR1553B_RT_STAT2_SREQ ( 1 << GR1553B_RT_STAT2_SREQ_BIT )
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#define GR1553B_RT_STAT2_TFDE ( 1 << GR1553B_RT_STAT2_TFDE_BIT )
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/*** RT Status Words Register ***/
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#define GR1553B_RT_STATW_VECW_BIT 0
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#define GR1553B_RT_STATW_BITW_BIT 16
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#define GR1553B_RT_STATW_VECW ( 0xffff << GR1553B_RT_STATW_VECW_BIT )
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#define GR1553B_RT_STATW_BITW ( 0xffff << GR1553B_RT_STATW_BITW_BIT )
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/*** RT Sync Register ***/
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#define GR1553B_RT_SYNC_SYD_BIT 0
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#define GR1553B_RT_SYNC_SYTM_BIT 16
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#define GR1553B_RT_SYNC_SYD ( 0xffff << GR1553B_RT_SYNC_SYD_BIT )
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#define GR1553B_RT_SYNC_SYTM ( 0xffff << GR1553B_RT_SYNC_SYTM_BIT )
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/*** RT Sub adress table Register ***/
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#define GR1553B_RT_TAB_SATB_BIT 0
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#define GR1553B_RT_TAB_SATB ( 0xffff << GR1553B_RT_TAB_SATB_BIT )
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/*** RT Mode code control Register ***/
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#define GR1553B_RT_MCCTRL_S_BIT 0
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#define GR1553B_RT_MCCTRL_SB_BIT 2
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#define GR1553B_RT_MCCTRL_SD_BIT 4
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#define GR1553B_RT_MCCTRL_SDB_BIT 6
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#define GR1553B_RT_MCCTRL_TS_BIT 8
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#define GR1553B_RT_MCCTRL_TSB_BIT 10
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#define GR1553B_RT_MCCTRL_TVW_BIT 12
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#define GR1553B_RT_MCCTRL_TBW_BIT 14
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#define GR1553B_RT_MCCTRL_DBC_BIT 16
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#define GR1553B_RT_MCCTRL_IST_BIT 18
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#define GR1553B_RT_MCCTRL_ISTB_BIT 20
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#define GR1553B_RT_MCCTRL_ITF_BIT 22
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#define GR1553B_RT_MCCTRL_ITFB_BIT 24
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#define GR1553B_RT_MCCTRL_RRT_BIT 26
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#define GR1553B_RT_MCCTRL_RRTB_BIT 28
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#define GR1553B_RT_MCCTRL_S ( 1 << GR1553B_RT_MCCTRL_S_BIT )
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#define GR1553B_RT_MCCTRL_SB ( 1 << GR1553B_RT_MCCTRL_SB_BIT )
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#define GR1553B_RT_MCCTRL_SD ( 1 << GR1553B_RT_MCCTRL_SD_BIT )
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#define GR1553B_RT_MCCTRL_SDB ( 1 << GR1553B_RT_MCCTRL_SDB_BIT )
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#define GR1553B_RT_MCCTRL_TS ( 1 << GR1553B_RT_MCCTRL_TS_BIT )
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#define GR1553B_RT_MCCTRL_TSB ( 1 << GR1553B_RT_MCCTRL_TSB_BIT )
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#define GR1553B_RT_MCCTRL_TVW ( 1 << GR1553B_RT_MCCTRL_TVW_BIT )
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#define GR1553B_RT_MCCTRL_TBW ( 1 << GR1553B_RT_MCCTRL_TBW_BIT )
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#define GR1553B_RT_MCCTRL_DBC ( 1 << GR1553B_RT_MCCTRL_DBC_BIT )
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#define GR1553B_RT_MCCTRL_IST ( 1 << GR1553B_RT_MCCTRL_IST_BIT )
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#define GR1553B_RT_MCCTRL_ISTB ( 1 << GR1553B_RT_MCCTRL_ISTB_BIT )
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#define GR1553B_RT_MCCTRL_ITF ( 1 << GR1553B_RT_MCCTRL_ITF_BIT )
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#define GR1553B_RT_MCCTRL_ITFB ( 1 << GR1553B_RT_MCCTRL_ITFB_BIT )
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#define GR1553B_RT_MCCTRL_RRT ( 1 << GR1553B_RT_MCCTRL_RRT_BIT )
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#define GR1553B_RT_MCCTRL_RRTB ( 1 << GR1553B_RT_MCCTRL_RRTB_BIT )
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/*** RT Time Tag control Register ***/
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#define GR1553B_RT_TTAG_TVAL_BIT 0
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#define GR1553B_RT_TTAG_TRES_BIT 16
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#define GR1553B_RT_TTAG_TVAL ( 0xffff << GR1553B_RT_TTAG_TVAL_BIT )
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#define GR1553B_RT_TTAG_TRES ( 0xffff << GR1553B_RT_TTAG_TRES_BIT )
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/*** BM Control Register ***/
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#define GR1553B_BM_STAT_BMSUP_BIT 31
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#define GR1553B_BM_STAT_BMSUP ( 1 << GR1553B_BM_STAT_BMSUP_BIT )
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/*** BM Control Register ***/
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#define GR1553B_BM_CTRL_BMEN_BIT 0
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#define GR1553B_BM_CTRL_MANL_BIT 1
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#define GR1553B_BM_CTRL_UDWL_BIT 2
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#define GR1553B_BM_CTRL_IMCL_BIT 3
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#define GR1553B_BM_CTRL_BMEN ( 1 << GR1553B_BM_CTRL_BMEN_BIT )
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#define GR1553B_BM_CTRL_MANL ( 1 << GR1553B_BM_CTRL_MANL_BIT )
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#define GR1553B_BM_CTRL_UDWL ( 1 << GR1553B_BM_CTRL_UDWL_BIT )
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#define GR1553B_BM_CTRL_IMCL ( 1 << GR1553B_BM_CTRL_IMCL_BIT )
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/*** BM RT Mode code filter Register ***/
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#define GR1553B_BM_MC_S_BIT 0
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#define GR1553B_BM_MC_SB_BIT 1
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#define GR1553B_BM_MC_SD_BIT 2
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#define GR1553B_BM_MC_SDB_BIT 3
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#define GR1553B_BM_MC_TS_BIT 4
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#define GR1553B_BM_MC_TSB_BIT 5
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#define GR1553B_BM_MC_TVW_BIT 6
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#define GR1553B_BM_MC_TBW_BIT 7
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#define GR1553B_BM_MC_DBC_BIT 8
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#define GR1553B_BM_MC_IST_BIT 9
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#define GR1553B_BM_MC_ISTB_BIT 10
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#define GR1553B_BM_MC_ITF_BIT 11
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#define GR1553B_BM_MC_ITFB_BIT 12
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#define GR1553B_BM_MC_RRT_BIT 13
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#define GR1553B_BM_MC_RRTB_BIT 14
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#define GR1553B_BM_MC_TSW_BIT 15
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#define GR1553B_BM_MC_TLC_BIT 16
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#define GR1553B_BM_MC_STS_BIT 17
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#define GR1553B_BM_MC_STSB_BIT 18
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#define GR1553B_BM_MC_S ( 1 << GR1553B_BM_MC_S_BIT )
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#define GR1553B_BM_MC_SB ( 1 << GR1553B_BM_MC_SB_BIT )
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#define GR1553B_BM_MC_SD ( 1 << GR1553B_BM_MC_SD_BIT )
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#define GR1553B_BM_MC_SDB ( 1 << GR1553B_BM_MC_SDB_BIT )
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#define GR1553B_BM_MC_TS ( 1 << GR1553B_BM_MC_TS_BIT )
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#define GR1553B_BM_MC_TSB ( 1 << GR1553B_BM_MC_TSB_BIT )
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#define GR1553B_BM_MC_TVW ( 1 << GR1553B_BM_MC_TVW_BIT )
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#define GR1553B_BM_MC_TBW ( 1 << GR1553B_BM_MC_TBW_BIT )
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#define GR1553B_BM_MC_DBC ( 1 << GR1553B_BM_MC_DBC_BIT )
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#define GR1553B_BM_MC_IST ( 1 << GR1553B_BM_MC_IST_BIT )
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#define GR1553B_BM_MC_ISTB ( 1 << GR1553B_BM_MC_ISTB_BIT )
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#define GR1553B_BM_MC_ITF ( 1 << GR1553B_BM_MC_ITF_BIT )
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#define GR1553B_BM_MC_ITFB ( 1 << GR1553B_BM_MC_ITFB_BIT )
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#define GR1553B_BM_MC_RRT ( 1 << GR1553B_BM_MC_RRT_BIT )
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#define GR1553B_BM_MC_RRTB ( 1 << GR1553B_BM_MC_RRTB_BIT )
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#define GR1553B_BM_MC_TSW ( 1 << GR1553B_BM_MC_TSW_BIT )
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#define GR1553B_BM_MC_TLC ( 1 << GR1553B_BM_MC_TLC_BIT )
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#define GR1553B_BM_MC_STS ( 1 << GR1553B_BM_MC_STS_BIT )
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#define GR1553B_BM_MC_STSB ( 1 << GR1553B_BM_MC_STSB_BIT )
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/*** BM RT Mode code filter Register ***/
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#define GR1553B_BM_TTAG_VAL_BIT 0
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#define GR1553B_BM_TTAG_RES_BIT 24
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#define GR1553B_BM_TTAG_VAL ( 0xffffff << GR1553B_BM_TTAG_VAL_BIT )
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#define GR1553B_BM_TTAG_RES ( 0xff << GR1553B_BM_TTAG_RES_BIT )
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/* Register GR1553B driver */
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extern void gr1553_register( void );
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/*** BC Device allocation ***/
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/* Allocate a BC device. Minor is assigned to a device in the order
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* they are registered to the driver.
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*/
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extern struct drvmgr_dev **gr1553_bc_open( int minor );
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/* Free a BC device previously allocated */
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extern void gr1553_bc_close( struct drvmgr_dev **dev );
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/*** RT Device allocation ***/
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/* Allocate a BC device. Minor is assigned to a device in the order
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* they are registered to the driver.
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*/
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extern struct drvmgr_dev **gr1553_rt_open( int minor );
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/* Free a BC device previously allocated */
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extern void gr1553_rt_close( struct drvmgr_dev **dev );
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/*** BM Device allocation ***/
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/* Allocate a BC device. Minor is assigned to a device in the order
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* they are registered to the driver.
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*/
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extern struct drvmgr_dev **gr1553_bm_open( int minor );
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/* Free a BC device previously allocated */
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extern void gr1553_bm_close( struct drvmgr_dev **dev );
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#ifdef __cplusplus
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}
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#endif
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#endif /* __GR1553B_H__ */
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