The genmcf548x partly uses is own implementation of the interrupt
extension API for libbsd support.
This patch is a part of the BSP source reorganization.
Update #3285.
This avoids warnings like this:
warning: ISO C does not allow extra ';' outside of a function [-Wpedantic]
RTEMS_DECLARE_GLOBAL_SYMBOL( abc );
^
Update #3459.
The partition buffer area alignment required by rtems_partition_create()
was too strict since it was checked via _Addresses_Is_aligned() which
uses CPU_ALIGNMENT. The CPU_ALIGNMENT must take long double and vector
data type alignment requirements into account. For the partition
maintenance only pointer alignment is required (Chain_Node, which
consists of two pointers). The user should ensure that its partition
buffer area is suitable for the items it wants to manage. The user
should not be burdened to provide buffers with the maximum architecture
alignment, e.g. why need a 16 byte aligned buffer if you want to manage
items with 4 byte integers only?
Update #3482.
Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.
It seems that previously the condition
CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)
was true on all CPU ports. Now, we need an additional check.
Update #3482.
Set the FIFO control register while DLAB == 1 in the line control
register. At least on the QorIQ T4240 the driver still works with the
re-ordered FIFO control register access.
Using CONFIGURE_MINIMUM_TASK_STACK_SIZE increases also the interrupt
stack size. This is an issue on some BSPs. Use
CONFIGURE_INIT_TASK_TABLE_SIZE instead.
Update #3433.
Introduce a new internal define _CONFIGURE_MAXIMUM_PROCESSORS and ensure
that it is _CONFIGURE_MAXIMUM_PROCESSORS > 1 only in SMP configurations.
This avoids to allocate data structures for non-existing additional
processors in uniprocessor configuration.
Update #3459.
The previous version worked only on a patched Qemu. Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.
Update #3433.
Sebastian Huber