ZYNQ7000: Add support PYNQ, PicoZed, MicroZed, ZYBO and ZYBO Z7

This patch adds basic support for the following boards:

xilinx_zynq_pynq - PYNQ Z1 / Z2
xilinx_zynq_microzed - MicroZed 7010 / 7020
xilinx_zynq_picozed - PicoZed 7010 / 7015 / 7020 / 7030
xilinx_zynq_zybo - ZYBO
xilinx_zynq_zybo_z7 - ZYBO Z7-10 / Z7-20

N.b. Arty Z7-20 is basically a PYNQ Z1 - different board
color and updated Eth PHY.
This commit is contained in:
Bernd Moessner
2023-11-28 12:51:34 -06:00
committed by Joel Sherrill
parent b2dd594422
commit fe35c8d5ee
21 changed files with 171 additions and 2 deletions
@@ -0,0 +1,7 @@
#
# Xilinx Zedboard RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: xilinx_zynq-testsuite.tcfg
+1
View File
@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
@@ -0,0 +1,7 @@
#
# Xilinx Zedboard RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: xilinx_zynq-testsuite.tcfg
+1
View File
@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
@@ -0,0 +1,7 @@
#
# Xilinx Zedboard RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: xilinx_zynq-testsuite.tcfg
+1
View File
@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
@@ -0,0 +1,7 @@
#
# Xilinx Zedboard RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: xilinx_zynq-testsuite.tcfg
+1
View File
@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
@@ -0,0 +1,7 @@
#
# Xilinx Zedboard RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: xilinx_zynq-testsuite.tcfg
+1
View File
@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/xilinx_zynq.inc
@@ -0,0 +1,19 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: arm
bsp: xilinx_zynq_microzed
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2023 B. Moessner
cppflags: []
enabled-by: true
family: xilinx-zynq
includes: []
install: []
links:
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: grp
source: []
type: build
@@ -0,0 +1,19 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: arm
bsp: xilinx_zynq_picozed
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2023 B. Moessner
cppflags: []
enabled-by: true
family: xilinx-zynq
includes: []
install: []
links:
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: grp
source: []
type: build
@@ -0,0 +1,19 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: arm
bsp: xilinx_zynq_pynq
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2023 B. Moessner
cppflags: []
enabled-by: true
family: xilinx-zynq
includes: []
install: []
links:
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: grp
source: []
type: build
@@ -0,0 +1,19 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: arm
bsp: xilinx_zynq_zybo
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2023 B. Moessner
cppflags: []
enabled-by: true
family: xilinx-zynq
includes: []
install: []
links:
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: grp
source: []
type: build
@@ -0,0 +1,19 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: arm
bsp: xilinx_zynq_zybo_z7
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2023 B. Moessner
cppflags: []
enabled-by: true
family: xilinx-zynq
includes: []
install: []
links:
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: grp
source: []
type: build
@@ -4,17 +4,25 @@ actions:
- define: null
build-type: option
copyrights:
- Copyright (C) 2023 B. Moessner
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- arm/xilinx_zynq_zc702
- arm/xilinx_zynq_zc706
- arm/xilinx_zynq_zedboard
- arm/xilinx_zynq_picozed
- arm/xilinx_zynq_zybo_z7
- arm/xilinx_zynq_zybo_microzed
value: 333333333
- enabled-by:
- arm/xilinx_zynq_zybo
- arm/xilinx_zynq_pynq
value: 325000000
- enabled-by: true
value: 100000000
description: |
ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz
ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz. Set this to CPU Clock /2.
enabled-by: true
format: '{}'
links: []
@@ -4,7 +4,12 @@ actions:
- define: null
build-type: option
copyrights:
- Copyright (C) 2023 B. Moessner
- Copyright (C) 2020 embedded brains GmbH & Co. KG
- enabled-by:
- arm/xilinx_zynq_zybo
- arm/xilinx_zynq_pynq
value: 108333336
default:
- enabled-by: true
value: 111111111
@@ -4,8 +4,13 @@ actions:
- define: null
build-type: option
copyrights:
- Copyright (C) 2023 B. Moessner
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- arm/xilinx_zynq_zybo_z7
- arm/xilinx_zynq_pynq
value: 100000000
- enabled-by: true
value: 50000000
description: |
@@ -6,13 +6,20 @@ actions:
- format-and-define: null
build-type: option
copyrights:
- Copyright (C) 2023 B. Moessner
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- arm/xilinx_zynq_zc702
- arm/xilinx_zynq_zc706
- arm/xilinx_zynq_picozed
- arm/xilinx_zynq_zyno_z7
- arm/xilinx_zynq_microzed
value: 0x40000000
- enabled-by: arm/xilinx_zynq_zedboard
- enabled-by:
- arm/xilinx_zynq_zedboard
- arm/xilinx_zynq_zybo
- arm/xilinx_zynq_pynq
value: 0x20000000
- enabled-by: true
value: 0x10000000
+3
View File
@@ -6,6 +6,9 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- arm/xilinx_zynq_microzed
value: 0
- enabled-by: true
value: 1
description: |
+6
View File
@@ -5,6 +5,7 @@ actions:
- define-condition: null
build-type: option
copyrights:
- Copyright (C) 2023 B. Moessner
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: true
@@ -27,6 +28,11 @@ enabled-by:
- arm/xilinx_zynq_zc702
- arm/xilinx_zynq_zc706
- arm/xilinx_zynq_zedboard
- arm/xilinx_zynq_zybo
- arm/xilinx_zynq_zybo_z7
- arm/xilinx_zynq_picozed
- arm/xilinx_zynq_pynq
- arm/xilinx_zynq_microzed
- powerpc/qoriq_e500
- powerpc/qoriq_e6500_32
- powerpc/qoriq_e6500_64