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2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>

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* cpu.c, rtems/score/mips.h:
	Use "__asm__" instead of "asm" for improved c99-compliance.
This commit is contained in:
Ralf Corsepius
2011-02-11 08:54:08 +00:00
parent e4a2a21f8d
commit f8958d9c7d
3 changed files with 22 additions and 17 deletions
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cpukit/score/cpu/mips/ChangeLog
+5
View File
@@ -1,3 +1,8 @@
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* cpu.c, rtems/score/mips.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
2011-01-04 Joel Sherrill <joel.sherrill@oarcorp.com>
* cpu_asm.S: _Thread_Executing was not used.
cpukit/score/cpu/mips/cpu.c
+1 -1
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@@ -315,7 +315,7 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
#if (__mips == 3) || (__mips == 32)
for( ; ; )
asm volatile("wait"); /* use wait to enter low power mode */
__asm__ volatile("wait"); /* use wait to enter low power mode */
#elif __mips == 1
for( ; ; )
;
cpukit/score/cpu/mips/rtems/score/mips.h
+16 -16
View File
@@ -116,13 +116,13 @@ extern "C" {
#define mips_get_sr( _x ) \
do { \
asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \
__asm__ volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \
} while (0)
#define mips_set_sr( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
__asm__ volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
} while (0)
@@ -132,14 +132,14 @@ extern "C" {
#define mips_get_cause( _x ) \
do { \
asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
__asm__ volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
} while (0)
#define mips_set_cause( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
__asm__ volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
} while (0)
@@ -151,14 +151,14 @@ extern "C" {
#define mips_get_dcic( _x ) \
do { \
asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \
__asm__ volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \
} while (0)
#define mips_set_dcic( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \
__asm__ volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \
} while (0)
@@ -171,8 +171,8 @@ extern "C" {
#define mips_get_bpcrm( _x, _y ) \
do { \
asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \
asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \
__asm__ volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \
__asm__ volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \
} while (0)
@@ -180,8 +180,8 @@ extern "C" {
do { \
register unsigned int __x = (_x); \
register unsigned int __y = (_y); \
asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \
asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \
__asm__ volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \
__asm__ volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \
} while (0)
@@ -196,8 +196,8 @@ extern "C" {
#define mips_get_bdarm( _x, _y ) \
do { \
asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \
asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \
__asm__ volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \
__asm__ volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \
} while (0)
@@ -205,8 +205,8 @@ extern "C" {
do { \
register unsigned int __x = (_x); \
register unsigned int __y = (_y); \
asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \
asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \
__asm__ volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \
__asm__ volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \
} while (0)
@@ -223,14 +223,14 @@ extern "C" {
#define mips_get_fcr31( _x ) \
do { \
asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
__asm__ volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
} while(0)
#define mips_set_fcr31( _x ) \
do { \
register unsigned int __x = (_x); \
asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
__asm__ volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
} while(0)
#else