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2000-08-28 Joel Sherrill <joel.sherrill@OARcorp.com>

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* cpu.c: Spacing issues.
	* rtems/score/cpu.h: Removed warning by setting _level.
This commit is contained in:
Joel Sherrill
2000-08-29 14:47:09 +00:00
parent ce6411d66f
commit eeec72f883
4 changed files with 12 additions and 8 deletions
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c/src/exec/score/cpu/arm/cpu.c
+5 -4
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@@ -13,7 +13,7 @@
#include <rtems/system.h>
#include <rtems.h>
#include <bspio.h>
#include <bspIo.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <rtems/score/thread.h>
@@ -155,11 +155,12 @@ extern void _Exception_Handler_Abort();
void rtems_exception_init_mngt()
{
ISR_Level level;
_CPU_ISR_Disable(level);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _Exception_Handler_Abort , NULL);
c/src/exec/score/cpu/arm/rtems/score/cpu.h
+1
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@@ -525,6 +525,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
*/
#define _CPU_ISR_Disable( _level ) \
{ \
(_level) = 0; \
asm volatile ("MRS r0, cpsr \n" ); \
asm volatile ("ORR r0, r0, #0xc0 \n" ); \
asm volatile ("MSR cpsr, r0 \n" ); \
cpukit/score/cpu/arm/cpu.c
+5 -4
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@@ -13,7 +13,7 @@
#include <rtems/system.h>
#include <rtems.h>
#include <bspio.h>
#include <bspIo.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <rtems/score/thread.h>
@@ -155,11 +155,12 @@ extern void _Exception_Handler_Abort();
void rtems_exception_init_mngt()
{
ISR_Level level;
_CPU_ISR_Disable(level);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI, _Exception_Handler_Undef_Swi, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, _Exception_Handler_Abort , NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _Exception_Handler_Abort , NULL);
cpukit/score/cpu/arm/rtems/score/cpu.h
+1
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@@ -525,6 +525,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
*/
#define _CPU_ISR_Disable( _level ) \
{ \
(_level) = 0; \
asm volatile ("MRS r0, cpsr \n" ); \
asm volatile ("ORR r0, r0, #0xc0 \n" ); \
asm volatile ("MSR cpsr, r0 \n" ); \