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2009-09-14 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* cpu_supplement/arm.t: Update.
	* cpu_supplement/preface.texi: Typo.
	* cpu_supplement/general.t: Expanded abbreviation.
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Joel Sherrill committed 2009-09-14 14:50:39 +00:00
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doc/ChangeLog
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@@ -1,3 +1,15 @@
2009-09-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
* cpu_supplement/arm.t: Update.
* cpu_supplement/preface.texi: Typo.
* cpu_supplement/general.t: Expanded abbreviation.
2009-09-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
* cpu_supplement/arm.t: Update.
* cpu_supplement/preface.texi: Typo.
* cpu_supplement/general.t: Expanded abbreviation.
2009-08-26 Sebastian Huber <sebastian.huber@embedded-brains.de>
* user/conf.t: Change stack allocator signature.
doc/cpu_supplement/arm.t
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doc/cpu_supplement/general.t
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@@ -38,9 +38,9 @@ may be based on either an architectural specification or on maintaining
compatibility with a popular processor. Recent microprocessor families
such as the SPARC or PowerPC are based on an architectural specification
which is independent or any particular CPU model or implementation.
Older families such as the M68xxx and the iX86 evolved as the manufacturer
strived to produce higher performance processor models which maintained
binary compatibility with older models.
Older families such as the Motorola 68000 and the Intel x86 evolved as the
manufacturer strived to produce higher performance processor models which
maintained binary compatibility with older models.
RTEMS takes advantage of the similarity of the various models within a
CPU family. Although the models do vary in significant ways, the high
doc/cpu_supplement/preface.texi
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@@ -33,7 +33,7 @@ which occur when a CPU core implementation is combined with
a set of peripherals to form a system on chip. For example,
there are many ARM CPU models from numerous semiconductor
vendors and a wide variety of peripherals. But at the
ISA level, they share a common compaability.
ISA level, they share a common compatibility.
RTEMS depends upon this core similarity across the CPU models
and leverages that to minimize the source code that is specific