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cpukit/score/cpu/mips: Save fcr31 through cfc1

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The exception path of _ISR_Handler() read the control and status
register of coprocessor 1 with mfc1 and wrote it back with mtc1.
Those instructions address a floating point data register.  cfc1 and
ctc1 address a control register.

So the save put the bits of $f31 into the frame at R_FCSR, over the
value which the prologue stored there.  The restore put the slot into
$f31 and destroyed that register.  The same pair used C1_REVISION,
which is $f0 and which holds the identity of the unit rather than
state of a context.

Drop both accesses.  The prologue stores the register through the
two-read idiom of the port and the exit restores it with ctc1, so the
exception path needs neither.  Nothing fills R_FEIR, because no MIPS32
processor carries that register.

Update #5769.

Assisted-by: Claude:claude-opus-5 claude-code
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
This commit is contained in:
Sebastian Huber
2026-09-21 20:02:55 -05:00
committed by Kinsey Moore
parent a29441c5f6
commit ea80e1d7ba
2 changed files with 11 additions and 12 deletions
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cpukit/score/cpu/mips/cpu_asm.S
+8 -8
View File
@@ -762,13 +762,13 @@ _ISR_Handler_Exception:
STREG t1,R_BADVADDR*R_SZ(sp)
#if ( MIPS_HAS_FPU == 1 )
/*
* The prologue above stores the control and status register of
* coprocessor 1, so the frame carries it already.
*/
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_save_fp_from_exception
NOP
mfc1 t0,C1_REVISION
mfc1 t1,C1_STATUS
STREG t0,R_FEIR*R_SZ(sp)
STREG t1,R_FCSR*R_SZ(sp)
#endif
move a0,sp
@@ -786,13 +786,13 @@ _ISR_Handler_Exception:
#if ( MIPS_HAS_FPU == 1 )
/*
* The exit below restores the control and status register of
* coprocessor 1 from the frame.
*/
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_restore_fp_from_exception
NOP
LDREG t0,R_FEIR*R_SZ(sp)
LDREG t1,R_FCSR*R_SZ(sp)
mtc1 t0,C1_REVISION
mtc1 t1,C1_STATUS
#endif
LDREG s0,R_S0*R_SZ(sp) /* restore s0 - s7 */
LDREG s1,R_S1*R_SZ(sp)
cpukit/score/cpu/mips/include/rtems/score/cpu.h
+3 -4
View File
@@ -425,10 +425,9 @@ typedef struct
__MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */
__MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */
/* (oddly not documented on MGV) */
__MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */
/* (oddly not documented on MGV) */
__MIPS_REGISTER_TYPE fcsr; /* 70 -- saved if FP enabled */
__MIPS_REGISTER_TYPE feir; /* 71 -- NOT FILLED IN, the register */
/* exists on no MIPS32 CPU */
/* GDB does not seem to care about anything past this point */