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added BSP hsc_cm01

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Thomas Doerfler committed 2007-08-10 08:15:58 +00:00
1 parent 38630e9849
commit e35c6965bf
14 files changed
+641 -39
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README.configure
+3 -1
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@@ -202,8 +202,10 @@ mips : csb350 genmongoosev hurricane jmr3904 rbtx4925 rbtx4938
powerpc : psim score603e mcp750 mvme2100 mvme2307 mpc8260ads ss555
mvme5500 ep1a pm520_cr825 pm520_ze30 gen405 helas403
mbx821_001 mbx821_002 mbx821_002b mbx860_001b
mbx860_002 mbx860_005b mtx603e brs5l gen5200 ep5200
virtex gen83xx mpc8349eamds
mbx860_002 mbx860_005b mtx603e brs5l gen5200 icecube
virtex gen83xx mpc8349eamds
virtex gen83xx mpc8349eamds hsc_cm01
NOTE: The "motorola_powerpc" BSP is a single BSP which
can be conditionally compiled to support most Motorola
aclocal/bsp-alias.m4
+1
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@@ -27,6 +27,7 @@ AC_DEFUN([_RTEMS_BSP_ALIAS],
pm520*) $2=gen5200 ;; # MPC5200 based board
icecube) $2=gen5200 ;; # MPC5200 based board - LITE5200B
mpc8349eamds) $2=gen83xx ;; # MPC8349 based board
hsc_cm01) $2=gen83xx ;; # MPC8349 based board
simcpu32) $2=sim68000 ;; # BSVC CPU32 variant
simsh7032) $2=shsim ;; # SH7032 simulator
simsh7045) $2=shsim ;; # SH7045 simulator
aclocal/check-bsps.m4
+1 -1
View File
@@ -26,7 +26,7 @@ AC_MSG_CHECKING([for available BSPs])
bsps="$bsps mbx860_005b"
;;
gen5200) bsps="pm520_cr825 pm520_ze30 brs5l";;
gen83xx) bsps="mpc8349eamds";;
gen83xx) bsps="mpc8349eamds hsc_cm01";;
motorola_powerpc) bsps="mvme2307 mcp750 mtx603e mvme2100";;
pc386) bsps="pc386 pc386dx pc486 pc586 pc686 pck6";;
erc32) bsps="erc32 sis";;
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
+4
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@@ -1,3 +1,7 @@
2007-08-08 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* Makefile.am, i2c/i2c_init.c: add i2c initialization
2007-07-13 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am, preinstall.am: Install a linkcmds all the time.
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
+11 -3
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@@ -33,7 +33,9 @@ rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds startup/linkcmds.mpc8349eamds
dist_project_lib_DATA += startup/linkcmds \
startup/linkcmds.mpc8349eamds \
startup/linkcmds.hsc_cm01
noinst_PROGRAMS += mpc83xx_regs.rel
mpc83xx_regs_rel_SOURCES = startup/mpc83xx_regs.c
@@ -85,11 +87,16 @@ network_rel_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += bsp_i2c.rel
bsp_i2c_rel_SOURCES = i2c/i2c_init.c
bsp_i2c_rel_CPPFLAGS = $(AM_CPPFLAGS)
bsp_i2c_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_LIBADD = startup.rel pclock.rel console.rel \
vectors.rel irq.rel mpc83xx_regs.rel
libbsp_a_LIBADD += network.rel
libbsp_a_LIBADD += network.rel bsp_i2c.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
@@ -99,7 +106,8 @@ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel \
../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel \
../../../libcpu/@RTEMS_CPU@/mpc83xx/i2c.rel
EXTRA_DIST += README.mpc8349eamds
EXTRA_DIST += times.mpc8349eamds
c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c
+111
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@@ -0,0 +1,111 @@
/*===============================================================*\
| Project: RTEMS support for MPC83xx |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| this file contains the low level MPC83xx I2C driver parameters |
\*===============================================================*/
#include <mpc83xx/mpc83xx_i2cdrv.h>
#include <libchip/i2c-2b-eeprom.h>
#include <bsp/irq.h>
#include <bsp.h>
static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
/* first channel */
{
{/* public fields */
ops: &mpc83xx_i2c_ops,
size: sizeof(mpc83xx_i2c_bus_tbl[0]),
},
{ /* our private fields */
reg_ptr: &mpc83xx.i2c[0],
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_I2C1
}
},
/* second channel */
{
{ /* public fields */
ops: &mpc83xx_i2c_ops,
size: sizeof(mpc83xx_i2c_bus_tbl[1]),
},
{ /* our private fields */
reg_ptr: &mpc83xx.i2c[1],
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_I2C2
}
}
};
rtems_libi2c_bus_t *mpc83xx_i2c_bus_descriptor[2] = {
&mpc83xx_i2c_bus_tbl[0].bus_desc,
&mpc83xx_i2c_bus_tbl[1].bus_desc
};
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
rtems_status_code bsp_register_i2c
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| register I2C busses and devices |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
void /* <none> */
)
/*-------------------------------------------------------------------------*\
| Return Value: |
| 0 or error code |
\*=========================================================================*/
{
int ret_code;
/*
* init I2C library
*/
rtems_libi2c_initialize ();
/*
* register first I2C bus
*/
ret_code = rtems_libi2c_register_bus("/dev/i2c1",
mpc83xx_i2c_bus_descriptor[0]);
if (ret_code < 0) {
return -ret_code;
}
/*
* register second I2C bus
*/
ret_code = rtems_libi2c_register_bus("/dev/i2c2",
mpc83xx_i2c_bus_descriptor[1]);
if (ret_code < 0) {
return -ret_code;
}
/*
* register EEPROM to bus 1, Address 0x50
*/
ret_code = rtems_libi2c_register_drv(RTEMS_BSP_I2C_EEPROM_DEVICE_NAME,
i2c_2b_eeprom_driver_descriptor,
0,0x50);
if (ret_code < 0) {
return -ret_code;
}
/*
* FIXME: register RTC driver, when available
*/
return 0;
}
c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
+80 -11
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@@ -40,12 +40,81 @@
#define BSP_CLKIN_FRQ 66000000L
#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(4) | \
RCWLR_COREPLL(4))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_GMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
/*
* for JPK HSC_CM01
*/
#elsif defined(HSC_CM01)
/*
* one DUART channel (UART1) supported
*/
#define GEN83xx_DUART_AVAIL_MASK 0x01
/* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT
/*
* clocking infos
*/
#define BSP_CLKIN_FRQ 66000000L
#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(4) | \
RCWLR_COREPLL(4))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_RGMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
#else
#error "board type not defined"
#endif
/*
* for JPK HSC_CM01 and freescale MPC8349EAMDS
*/
#if defined(MPC8349EAMDS) || defined(HSC_CM01)
/*
* address range definitions
*/
/* ROM definitions (2 MB) */
#define ROM_START 0xFFE00000
#define ROM_SIZE 0x00200000
/* ROM definitions (8 MB, mirrored multiple times) */
#define ROM_START 0xFE000000
#define ROM_SIZE 0x02000000
#define ROM_END (ROM_START+ROM_SIZE-1)
#define BOOT_START ROM_START
#define BOOT_END ROM_END
@@ -55,6 +124,7 @@
#define RAM_SIZE 0x10000000
#define RAM_END (RAM_START+RAM_SIZE-1)
/* working internal memory map base address */
#define IMMRBAR 0xE0000000
@@ -125,14 +195,6 @@ extern "C" {
#include <bsp/irq.h>
#include <bsp/vectors.h>
/*
* Network driver configuration
*/
struct rtems_bsdnet_ifconfig;
extern int rtems_mpc83xx_tsec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc83xx_tsec_driver_attach_detach
/* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration;
@@ -176,6 +238,7 @@ extern rtems_configuration_table BSP_Configuration;
/* functions */
void bsp_cleanup(void);
rtems_status_code bsp_register_i2c(void);
/* console modes (only termios) */
#ifdef PRINTK_MINOR
@@ -211,6 +274,12 @@ extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2"
/*
* i2c EEPROM device name
*/
#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
#ifdef __cplusplus
}
#endif
c/src/lib/libbsp/powerpc/gen83xx/preinstall.am
+4
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@@ -73,6 +73,10 @@ $(PROJECT_LIB)/linkcmds.mpc8349eamds: startup/linkcmds.mpc8349eamds $(PROJECT_LI
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8349eamds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8349eamds
$(PROJECT_LIB)/linkcmds.hsc_cm01: startup/linkcmds.hsc_cm01 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.hsc_cm01
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.hsc_cm01
$(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
+70 -22
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@@ -73,6 +73,8 @@
sync
.endm
#define REP8(l) l ; l; l; l; l; l; l; l;
.extern _bss_start
.extern _bss_size
.extern _data_start
@@ -83,31 +85,48 @@
.extern boot_card
.extern MBAR
.section ".vectors"
.section ".resconf","ax"
PUBLIC_VAR (reset_conf_words)
reset_conf_words:
REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff))
.section ".vectors","ax"
PUBLIC_VAR (reset_vec)
reset_vec:
bl start
bl rom_entry
.section ".entry"
PUBLIC_VAR (start)
start:
/*
* FIXME: basic CPU setup:
* init MSR
* basic CPU setup:
* init MSR
*/
mfmsr r30
SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_IP|MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
b start_rom_skip
PUBLIC_VAR (rom_entry)
rom_entry:
/*
* check, wether we are starting from ROM
* detect this using the absolute code address:
* when the upper 4 bits are 0xF, then we are in ROM
* basic CPU setup:
* init MSR
*/
bl 1f
1: mflr r28
LWI r29,0xF0000000
TSTBITS r28,r29,r30,0xF0000000
bne start_rom_skip
mfmsr r30
SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_IP|MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
/*
* ROM startup: remap IMMR to 0xE0000000
* use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR"
@@ -116,22 +135,49 @@ start:
LWI r31,IMMRBAR
lwz r29,0(r30)
stw r31,0(r30)
#if 0
lwz r29,0(r28) /* read from ROM... */
#endif
isync
lwz r29,0(r31) /* read from IMMRBAR... */
isync
/*
* NOTE: now r31 points to onchip registers
*/
/*
* ROM startup: init local access windows
* FIXME:
* we start from 0x100, so ROM is currently mapped to
* 0x00000000..
* in the next step, ROM will be remapped to its final location
* at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value)
* and we jump to that location.
* then we remove the ROM mapping to zero
*/
#ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL
#endif
#ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL
#endif
/*
* ROM startup: jump to code final ROM location
*/
LA r20, ROM_START /* ROM-RAM reloc in r20 */
LA r29, start_code_in_rom /* get compile time addr of label */
add r29,r20,r29 /* compute exec address */
mtlr r29
blr /* now further execution in upper ROM */
start_code_in_rom:
#ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL
#endif
#ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL
#endif
#endif
#ifdef LBLAWBAR1_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL
#endif
@@ -275,20 +321,22 @@ start:
LA r29, _data_start /* get start address of data section in RAM */
LA r28, _data_size /* get size of RAM image */
bl copy_image /* copy initialized data section from ROM to RAM location */
start_rom_skip:
/*
* ROM startup: clear bss in SDRAM
*/
LWI r30, _bss_start /* get start address of bss section */
LWI r29, _bss_size /* get size of bss section */
bl clr_mem /* Clear the bss section */
/*
* ROM startup: jump to code copy in SDRAM
*/
LA r29, start_code_in_ram /* get compile time address of label */
mtlr r29
blr /* now further execution RAM */
start_code_in_ram:
start_rom_skip:
/*
* ROM/RAM startup: clear bss in SDRAM
*/
LWI r30, _bss_start /* get start address of bss section */
LWI r29, _bss_size /* get size of bss section */
bl clr_mem /* Clear the bss section */
/*
* call boot_card
*/
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds
+5
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@@ -46,6 +46,11 @@ SECTIONS
*mpc83xx_regs*(*)
} > mpc83xx_regs
.resconf 0x000 :
{
*(.resconf)
} > ram
.vectors 0x100 :
{
*(.vectors)
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
+329
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File diff suppressed because it is too large. Load diff
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds
+5
View File
@@ -43,6 +43,11 @@ SECTIONS
*mpc83xx_regs*(*)
} > mpc83xx_regs
.resconf 0x000 :
{
*(.resconf)
} > ram
.vectors 0x100 :
{
*(.vectors)
make/custom/hsc_cm01.cfg
+16
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@@ -0,0 +1,16 @@
#
# Config file for customer specific MPC8349 board
#
# $Id$
#
#
# All GEN83xx configurations share the same base file, only a few
# parameters differ.
#
RTEMS_BOARD_MODEL=HSC-CM01
RTEMS_83XX_DERIVATE=MPC8349
RTEMS_LINKCMDS=linkcmds.hsc_cm01
include $(RTEMS_ROOT)/make/custom/gen83xx.cfg
make/custom/mpc8349eamds.cfg
+1 -1
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@@ -1,5 +1,5 @@
#
# Config file for customer specific MPC5200 board
# Config file for freescale's MPC8349EAMDS evaluation board
#
# $Id$
#