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can: add support for SJA1000 CAN controller
This commit adds support for a stand alone SJA1000 CAN controller. This is classical CAN only capable controller, so no FD support here. The driver's implementation is similar to CTU CAN FD, thus interrupt handler triggers a semaphore in main worker thread that takes care of handling interrupts and receiving and sending messages. The controller utilizes its one TX buffer for sending messages with abort function available if higher priority message is present in the software queue. Signed-off-by: Michal Lenc <michallenc@seznam.cz> Co-authored-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
This commit is contained in:
Michal Lenc
committed by
Kinsey Moore
Kinsey Moore
co-authored by
Pavel Pisa
Pavel Pisa
parent
1f92e9f89f
commit
df346b439b
File diff suppressed because it is too large
Load Diff
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/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
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/**
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* @file
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*
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* @ingroup SJA1000
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*
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* @brief This source file contains the register's definition of SJA1000
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* controller.
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*/
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/*
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* Copyright (C) 2025-2026 Michal Lenc <michallenc@seznam.cz> self-funded
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* Copyright (C) 2025-2026 Pavel Pisa <pisa@cmp.felk.cvut.cz> self-funded
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* Implementation is based on original LinCAN SJA1000 driver
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* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz>
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* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Copyright (C) 2004-2005 Tomasz Motylewski (BFAD GmbH)
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* Funded by OCERA and FRESCOR IST projects
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* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_CAN_SJA1000_SJA1000_REGS_H
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#define _DEV_CAN_SJA1000_SJA1000_REGS_H
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#include <dev/can/can-helpers.h>
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/* PeliCAN mode */
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enum sja1000_regs {
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SJA1000_MODE = 0x00,
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SJA1000_CMR = 0x01,
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SJA1000_SR = 0x02,
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SJA1000_IR = 0x03,
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SJA1000_IER = 0x04,
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SJA1000_BTR0 = 0x06,
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SJA1000_BTR1 = 0x07,
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SJA1000_OCR = 0x08,
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SJA1000_ALC = 0x0b,
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SJA1000_ECC = 0x0c,
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SJA1000_EWLR = 0x0d,
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SJA1000_RXERR = 0x0e,
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SJA1000_TXERR0 = 0x0e,
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SJA1000_TXERR1 = 0x0f,
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SJA1000_RMC = 0x1d,
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SJA1000_RBSA = 0x1e,
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SJA1000_FRM = 0x10,
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SJA1000_ID0 = 0x11,
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SJA1000_ID1 = 0x12,
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SJA1000_ID2 = 0x13,
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SJA1000_ID3 = 0x14,
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SJA1000_DATS = 0x13,
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SJA1000_DATE = 0x15,
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SJA1000_ACR0 = 0x10,
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SJA1000_ACR1 = 0x11,
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SJA1000_ACR2 = 0x12,
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SJA1000_ACR3 = 0x13,
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SJA1000_AMR0 = 0x14,
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SJA1000_AMR1 = 0x15,
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SJA1000_AMR2 = 0x16,
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SJA1000_AMR3 = 0x17,
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SJA1000_CDR = 0x1f
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};
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/* Mode registers */
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#define REG_MODE_RM BIT(0)
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#define REG_MODE_LOM BIT(1)
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#define REG_MODE_STM BIT(2)
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#define REG_MODE_AFM BIT(3)
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#define REG_MODE_SM BIT(4)
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/* Command registers */
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#define REG_CMR_TR BIT(0)
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#define REG_CMR_AT BIT(1)
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#define REG_CMR_RRB BIT(2)
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#define REG_CMR_CDO BIT(3)
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#define REG_CMR_SRR BIT(4)
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/* Status registers */
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#define REG_SR_RBS BIT(0)
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#define REG_SR_DOS BIT(1)
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#define REG_SR_TBS BIT(2)
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#define REG_SR_TCS BIT(3)
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#define REG_SR_RS BIT(4)
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#define REG_SR_TS BIT(5)
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#define REG_SR_ES BIT(6)
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#define REG_SR_BS BIT(7)
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#define REG_SR_WORKER_MASK (0x5)
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/* Interrupt registers */
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#define REG_INT_RI BIT(0)
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#define REG_INT_TI BIT(1)
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#define REG_INT_EI BIT(2)
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#define REG_INT_DOI BIT(3)
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#define REG_INT_WUI BIT(4)
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#define REG_INT_EPI BIT(5)
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#define REG_INT_ALI BIT(6)
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#define REG_INT_BEI BIT(7)
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#define REG_INT_MASK (0xff)
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#define REG_INT_WORKER_MASK (0xfc)
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/* Arbitration lost capture register */
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#define REG_ALC_RTR (0x1f)
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#define REG_ALC_IDE (0x1c)
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#define REG_ALC_SRTR (0x0b)
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/* Error Code Capture Register */
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#define REG_ECC_DIR BIT(5)
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#define REG_ECC_ERCC GENMASK(7, 6)
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#define REG_ECC_FUNC GENMASK(4, 0)
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#define REG_ECC_ERCC_BIT (0)
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#define REG_ECC_ERCC_FORM (1)
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#define REG_ECC_ERCC_STUFF (2)
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#define REG_ECC_ERCC_OTHER (3)
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#define REG_ECC_ERROR_ACTIVE (0x11)
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#define REG_ECC_ERROR_PASSIVE (0x16)
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/* Frame format information */
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#define REG_FRM_DLC GENMASK(3, 0)
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#define REG_FRM_RTR BIT(6)
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#define REG_FRM_FF BIT(7)
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#define REG_FRM_DLC_MASK (BIT(4) - 1)
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/* Bus Timing 1 Register */
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#define REG_BTR1_TSEG1_MAX (15)
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#define REG_BTR1_TSEG2_MAX (7)
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/* Output Control Register */
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#define REG_OCR_MODE_BIPHASE (0)
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#define REG_OCR_MODE_TEST (1)
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#define REG_OCR_MODE_NORMAL (2)
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#define REG_OCR_MODE_CLOCK (3)
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#define REG_OCR_TX0_LH (0x18)
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#define REG_OCR_TX1_ZZ (0)
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/* Clock Divider register */
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#define REG_CDR_OFF BIT(3)
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#define REG_CDR_RXINPEN BIT(5)
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#define REG_CDR_CBP BIT(6)
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#define REG_CDR_PELICAN BIT(7)
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#define REG_CDR_CLKOUT_DIV1 (7)
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#define REG_CDR_CLKOUT_DIV2 (0)
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#define REG_CDR_CLKOUT_DIV4 (1)
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#define REG_CDR_CLKOUT_DIV6 (2)
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#define REG_CDR_CLKOUT_DIV8 (3)
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#define REG_CDR_CLKOUT_DIV10 (4)
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#define REG_CDR_CLKOUT_DIV12 (5)
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#define REG_CDR_CLKOUT_DIV14 (6)
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#define REG_CDR_CLKOUT_MASK (7)
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#endif /* _DEV_CAN_SJA1000_SJA1000_REGS_H */
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@@ -0,0 +1,96 @@
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/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
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/**
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* @file
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*
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* @ingroup SJA1000
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*
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* @brief This header file contains the implementation of SJA1000 controller.
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*/
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/*
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* Copyright (C) 2025-2026 Michal Lenc <michallenc@seznam.cz> self-funded
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* Copyright (C) 2025-2026 Pavel Pisa <pisa@cmp.felk.cvut.cz> self-funded
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* Implementation is based on Linux CTU CAN FD driver
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_CAN_SJA1000_H
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#define _DEV_CAN_SJA1000_H
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struct rtems_can_chip;
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/**
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* @brief SJA1000 chip register mapping specification
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*/
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#define RTEMS_SJA1000_HW_REG_SPAN_MASK ( 3 )
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/**
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* @brief SJA1000 chip register mapping one byte each
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*/
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#define RTEMS_SJA1000_HW_REG_SPAN_1 ( 0 )
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/**
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* @brief SJA1000 chip register mapping with span 2 bytes
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*/
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#define RTEMS_SJA1000_HW_REG_SPAN_2 ( 1 )
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/**
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* @brief SJA1000 chip register mapping with span 4 bytes
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*/
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#define RTEMS_SJA1000_HW_REG_SPAN_4 ( 2 )
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/**
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* @brief SJA1000 chip register mapping into CPU I/O space
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*/
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#define RTEMS_SJA1000_HW_REG_IO_PORT ( 0x100 )
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/**
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* @brief This function initializes the SJA1000 controller.
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*
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* This is an entry point for SJA1000 controller initialization. This
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* function allocates generic CAN and SJA1000 related structures, sets
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* default values and initializes the resources (interrupt handler, semaphore.
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* worker thread).
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*
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* @param addr SJA1000 controller base address.
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* @param hw_options SJA1000 controller hardware options for register
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* mapping.
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* @param irq Interrupt number.
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* @param worker_priotiry The priority of TX/RX worker thread.
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* @param irq_option RTEMS_INTERRUPT_SHARED or RTEMS_INTERRUPT_UNIQUE.
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* @param can_clk_rate CAN clock rate.
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*
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* @return Pointer to CAN chip structure on success, NULL otherwise.
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*/
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struct rtems_can_chip *rtems_can_sja1000_initialize(
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uintptr_t addr,
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unsigned int hw_options,
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rtems_vector_number irq,
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rtems_task_priority worker_priority,
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rtems_option irq_option,
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unsigned long can_clk_rate
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);
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#endif /* _DEV_CAN_SJA1000_H */
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@@ -49,6 +49,7 @@ install:
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- cpukit/include/dev/can/can-virtual.h
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- cpukit/include/dev/can/can.h
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- cpukit/include/dev/can/ctucanfd.h
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- cpukit/include/dev/can/sja1000.h
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- destination: ${BSP_INCLUDEDIR}/dev/i2c
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source:
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- cpukit/include/dev/i2c/eeprom.h
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@@ -553,6 +554,7 @@ source:
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- cpukit/dev/can/can-queue.c
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- cpukit/dev/can/can-virtual.c
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- cpukit/dev/can/ctucanfd/ctucanfd.c
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- cpukit/dev/can/sja1000/sja1000.c
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- cpukit/dev/contrib/iovprintf.c
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- cpukit/dev/flash/flashdev.c
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- cpukit/dev/i2c/eeprom.c
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