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Merge branch 'master' of ssh://git.rtems.org/data/git/rtems

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This commit is contained in:
Joel Sherrill
2013-02-02 15:19:01 -06:00
parent 956722f4b4 80e37434ac
commit dd7b83550d
935 changed files with 24558 additions and 17944 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libbsp/arm/edb7312/irq/irq.c
+3 -1
View File
@@ -12,6 +12,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -170,7 +172,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
}
int_stat = *EP7312_INTSR3;
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libbsp/arm/gba/start/start.S
+1 -1
View File
@@ -162,7 +162,7 @@
.align
PUBLIC_ARM_FUNCTION(_gba_ISR_handler)
ldmfd r13!,{r0-r3,r12,r14}
b arm_exc_interrupt
b _ARMV4_Exception_interrupt
LABEL_END(_gba_ISR_handler)
c/src/lib/libbsp/arm/gp32/Makefile.am
+1 -1
View File
@@ -30,7 +30,7 @@ libbsp_a_SOURCES =
# startup
libbsp_a_SOURCES += ../../shared/bsplibc.c ../../shared/bsppost.c \
../../shared/bsppredriverhook.c ../../shared/bspgetworkarea.c \
../../shared/bsppretaskinghook.c startup/bspstart.c \
../../shared/bsppretaskinghook.c startup/bspstart.c startup/bspidle.c \
../../shared/bspclean.c startup/bspreset.c \
startup/memmap.c ../../shared/bootcard.c ../../shared/sbrk.c \
../../shared/gnatinstallhandler.c
c/src/lib/libbsp/arm/gp32/include/bsp.h
+6 -6
View File
@@ -1,12 +1,12 @@
/**
* @file
*
* This include file contains definitions related to the GP32 BSP.
* This include file contains definitions related to the GP32 BSP.
*/
/*
* Copyright (c) Canon Research France SA.]
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
* Copyright (c) Canon Research France SA.]
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -59,13 +59,13 @@ void gp32_setPalette( unsigned char pos, uint16_t color);
/*
* This BSP provides its own IDLE task to override the RTEMS one.
* This BSP provides its own IDLE thread to override the RTEMS one.
* So we prototype it and define the constant confdefs.h expects
* to configure a BSP specific one.
*/
Thread bsp_idle_task(uint32_t);
void *bsp_idle_thread(uintptr_t ignored);
#define BSP_IDLE_TASK_BODY bsp_idle_task
#define BSP_IDLE_TASK_BODY bsp_idle_thread
#ifdef __cplusplus
}
c/src/lib/libbsp/arm/gp32/startup/bspidle.c
+23
View File
@@ -0,0 +1,23 @@
/*
* BSP specific Idle thread
*/
/*
* Copyright (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp.h>
void *bsp_idle_thread(uintptr_t ignored)
{
while(1) {
__asm__ volatile ("MCR p15,0,r0,c7,c0,4 \n");
}
return NULL;
}
c/src/lib/libbsp/arm/gp32/startup/bspstart.c
+8 -17
View File
@@ -2,14 +2,15 @@
* This file contains the ARM BSP startup package. It includes application,
* board, and monitor specific initialization and configuration. The generic CPU
* dependent initialization has been performed before this routine is invoked.
*/
/*
* Copyright (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
*
* Copyright (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp.h>
@@ -22,16 +23,6 @@
*/
extern void rtems_exception_init_mngt(void);
/*
* BSP specific Idle task
*/
Thread bsp_idle_task(uint32_t ignored)
{
while(1) {
__asm__ volatile ("MCR p15,0,r0,c7,c0,4 \n");
}
}
/*
* BSP Specific Initialization in C
*/
c/src/lib/libbsp/arm/lpc24xx/configure.ac
+1 -1
View File
@@ -123,7 +123,7 @@ RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]
RTEMS_BSPOPTS_SET([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[lpc17xx_ea*],[(0x2f << 1)])
RTEMS_BSPOPTS_HELP([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[USB OTG transceiver I2C address used by USB stack])
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
RTEMS_BSP_LINKCMDS
AC_CONFIG_FILES([Makefile])
c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h
+21 -1
View File
@@ -27,6 +27,24 @@
#define LPC17XX_BASE 0x00
typedef struct {
#define LPC17XX_WWDT_MOD_WDEN BSP_BIT32(0)
#define LPC17XX_WWDT_MOD_WDRESET BSP_BIT32(1)
#define LPC17XX_WWDT_MOD_WDTOF BSP_BIT32(2)
#define LPC17XX_WWDT_MOD_WDINT BSP_BIT32(3)
#define LPC17XX_WWDT_MOD_WDPROTECT BSP_BIT32(4)
uint32_t mod;
uint32_t tc;
uint32_t feed;
uint32_t tv;
uint32_t reserved_10;
uint32_t warnint;
uint32_t window;
uint32_t reserved_1c;
} lpc17xx_wwdt;
#define LPC17XX_WWDT (*(volatile lpc17xx_wwdt *) (LPC17XX_BASE + 0x40000000))
typedef struct {
#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0)
#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4)
@@ -176,7 +194,9 @@ typedef struct {
#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000))
typedef struct {
uint32_t reserved_00 [268693504];
uint32_t reserved_00 [268435456];
lpc17xx_wwdt wwdt;
uint32_t reserved_40000020 [258040];
lpc17xx_scb scb;
} lpc17xx;
c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
+4
View File
@@ -104,12 +104,16 @@ extern BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
extern BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_static_chip_count;
#ifdef ARM_MULTILIB_ARCH_V7M
extern BSP_START_DATA_SECTION const ARMV7M_MPU_Region
lpc24xx_start_config_mpu_region [];
extern BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_mpu_region_count;
#endif /* ARM_MULTILIB_ARCH_V7M */
#ifdef __cplusplus
}
#endif /* __cplusplus */
c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c
+4 -2
View File
@@ -20,6 +20,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -33,13 +35,13 @@ void bsp_interrupt_dispatch(void)
rtems_vector_number vector = VICVectAddr;
/* Enable interrupts in program status register */
uint32_t psr = arm_status_irq_enable();
uint32_t psr = _ARMV4_Status_irq_enable();
/* Dispatch interrupt handlers */
bsp_interrupt_handler_dispatch(vector);
/* Restore program status register */
arm_status_restore(psr);
_ARMV4_Status_restore(psr);
/* Acknowledge interrupt */
VICVectAddr = 0;
c/src/lib/libbsp/arm/lpc24xx/irq/irq.c
+2 -1
View File
@@ -20,6 +20,7 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <rtems/score/armv7m.h>
#include <bsp.h>
@@ -113,7 +114,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
}
/* Install the IRQ exception handler */
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c
+6 -4
View File
@@ -7,7 +7,7 @@
*/
/*
* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
* Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
@@ -21,6 +21,7 @@
*/
#include <rtems.h>
#include <rtems/score/armv7m.h>
#include <bsp/bootcard.h>
#include <bsp/lpc24xx.h>
@@ -32,15 +33,16 @@ BSP_START_TEXT_SECTION __attribute__((flatten)) void bsp_reset(void)
rtems_interrupt_disable(level);
#ifdef ARM_MULTILIB_ARCH_V4
#if defined(ARM_MULTILIB_ARCH_V4)
/* Trigger watchdog reset */
WDCLKSEL = 0;
WDTC = 0xff;
WDMOD = 0x3;
WDFEED = 0xaa;
WDFEED = 0x55;
#else
printk("reset\n");
#elif defined(ARM_MULTILIB_ARCH_V7M)
_ARMV7M_SCB->aircr = ARMV7M_SCB_AIRCR_VECTKEY
| ARMV7M_SCB_AIRCR_SYSRESETREQ;
#endif
while (true) {
c/src/lib/libbsp/arm/lpc32xx/configure.ac
+1 -1
View File
@@ -106,7 +106,7 @@ RTEMS_BSPOPTS_HELP([BSP_USB_OTG_TRANSCEIVER_I2C_ADDR],[USB OTG transceiver I2C a
RTEMS_BSPOPTS_SET([TESTS_USE_PRINTK],[*],[1])
RTEMS_BSPOPTS_HELP([TESTS_USE_PRINTK],[tests use printk() for output])
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
RTEMS_BSP_LINKCMDS
AC_CONFIG_FILES([Makefile])
c/src/lib/libbsp/arm/lpc32xx/console/console-config.c
+6 -3
View File
@@ -45,7 +45,7 @@ static void lpc32xx_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
#ifdef LPC32XX_UART_3_BAUD
static bool lpc32xx_uart_probe_3(int minor)
{
LPC32XX_UARTCLK_CTRL |= 1U << 0;
LPC32XX_UARTCLK_CTRL |= BSP_BIT32(0);
LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK;
LPC32XX_UART_CLKMODE = BSP_FLD32SET(LPC32XX_UART_CLKMODE, 0x2, 4, 5);
@@ -64,7 +64,7 @@ static void lpc32xx_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
*/
gpio->p2_mux_set = BSP_BIT32(2);
LPC32XX_UARTCLK_CTRL |= 1U << 1;
LPC32XX_UARTCLK_CTRL |= BSP_BIT32(1);
LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK;
LPC32XX_UART_CLKMODE = BSP_FLD32SET(LPC32XX_UART_CLKMODE, 0x2, 6, 7);
@@ -75,7 +75,10 @@ static void lpc32xx_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
#ifdef LPC32XX_UART_6_BAUD
static bool lpc32xx_uart_probe_6(int minor)
{
LPC32XX_UARTCLK_CTRL |= 1U << 3;
/* Bypass the IrDA modulator/demodulator */
LPC32XX_UART_CTRL |= BSP_BIT32(5);
LPC32XX_UARTCLK_CTRL |= BSP_BIT32(3);
LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK;
LPC32XX_UART_CLKMODE = BSP_FLD32SET(LPC32XX_UART_CLKMODE, 0x2, 10, 11);
c/src/lib/libbsp/arm/lpc32xx/irq/irq.c
+5 -3
View File
@@ -19,6 +19,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -252,11 +254,11 @@ void bsp_interrupt_dispatch(void)
lpc32xx.sic_1.er = er_sic_1 & masks->field.sic_1;
lpc32xx.sic_2.er = er_sic_2 & masks->field.sic_2;
psr = arm_status_irq_enable();
psr = _ARMV4_Status_irq_enable();
bsp_interrupt_handler_dispatch(vector);
arm_status_restore(psr);
_ARMV4_Status_restore(psr);
lpc32xx.mic.er = er_mic & lpc32xx_irq_enable.field.mic;
lpc32xx.sic_1.er = er_sic_1 & lpc32xx_irq_enable.field.sic_1;
@@ -341,7 +343,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
lpc32xx.sic_1.atr = 0x26000;
lpc32xx.sic_2.atr = 0x0;
lpc32xx_set_exception_handler(ARM_EXCEPTION_IRQ, arm_exc_interrupt);
lpc32xx_set_exception_handler(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c
+3
View File
@@ -1323,6 +1323,9 @@ static int lpc_eth_up_or_down(lpc_eth_driver_entry *e, bool up)
lpc_eth_config_module_enable();
/* Enable RX/TX reset and disable soft reset */
lpc_eth->mac1 = 0xf00;
/* Initialize PHY */
lpc_eth->mcfg = ETH_MCFG_CLOCK_SELECT(0x7);
eno = lpc_eth_phy_up(e);
c/src/lib/libbsp/arm/shared/start/start.S
+31 -30
View File
@@ -5,7 +5,7 @@
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
* Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
@@ -31,6 +31,14 @@
.extern boot_card
.extern bsp_start_hook_0
.extern bsp_start_hook_1
.extern _ARMV4_Exception_undef_default
.extern _ARMV4_Exception_swi_default
.extern _ARMV4_Exception_data_abort_default
.extern _ARMV4_Exception_pref_abort_default
.extern _ARMV4_Exception_reserved_default
.extern _ARMV4_Exception_irq_default
.extern _ARMV4_Exception_fiq_default
.extern _ARMV7M_Exception_default
/* Global symbols */
.globl _start
@@ -74,31 +82,31 @@ handler_addr_reset:
handler_addr_undef:
.word reset
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word reset
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word reset
.word _ARMV4_Exception_data_abort_default
handler_addr_abort:
.word reset
.word _ARMV4_Exception_pref_abort_default
handler_addr_reserved:
.word reset
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word reset
.word _ARMV4_Exception_irq_default
handler_addr_fiq:
.word reset
.word _ARMV4_Exception_fiq_default
bsp_start_vector_table_end:
@@ -199,13 +207,6 @@ twiddle:
b twiddle
.arm
reset:
SWITCH_FROM_ARM_TO_THUMB r0
b twiddle
#elif defined(ARM_MULTILIB_ARCH_V7M)
.syntax unified
@@ -218,22 +219,22 @@ bsp_start_vector_table_begin:
.word bsp_stack_main_end
.word _start /* Reset */
.word bsp_reset /* NMI */
.word bsp_reset /* Hard Fault */
.word bsp_reset /* MPU Fault */
.word bsp_reset /* Bus Fault */
.word bsp_reset /* Usage Fault */
.word bsp_reset /* Reserved */
.word bsp_reset /* Reserved */
.word bsp_reset /* Reserved */
.word bsp_reset /* Reserved */
.word bsp_reset /* SVC */
.word bsp_reset /* Debug Monitor */
.word bsp_reset /* Reserved */
.word bsp_reset /* PendSV */
.word bsp_reset /* SysTick */
.word _ARMV7M_Exception_default /* NMI */
.word _ARMV7M_Exception_default /* Hard Fault */
.word _ARMV7M_Exception_default /* MPU Fault */
.word _ARMV7M_Exception_default /* Bus Fault */
.word _ARMV7M_Exception_default /* Usage Fault */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* SVC */
.word _ARMV7M_Exception_default /* Debug Monitor */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* PendSV */
.word _ARMV7M_Exception_default /* SysTick */
.rept BSP_INTERRUPT_VECTOR_MAX + 1
.word bsp_reset /* IRQ */
.word _ARMV7M_Exception_default /* IRQ */
.endr
bsp_start_vector_table_end:
c/src/lib/libbsp/arm/smdk2410/Makefile.am
+1 -1
View File
@@ -28,7 +28,7 @@ libbsp_a_SOURCES =
# startup
libbsp_a_SOURCES += ../../shared/bsplibc.c ../../shared/bsppost.c \
../gp32/startup/bspstart.c ../../shared/bspclean.c \
../gp32/startup/bspstart.c ../gp32/startup/bspidle.c ../../shared/bspclean.c \
startup/bspreset.c startup/memmap.c \
../../shared/bootcard.c ../../shared/sbrk.c \
../../shared/bsppretaskinghook.c \
c/src/lib/libbsp/m68k/mvme167/include/bsp.h
+7 -4
View File
@@ -1,11 +1,14 @@
/* bsp.h
/**
* @file
*
* Following defines must reflect the setup of the particular MVME167.
* All page references are to the MVME166/MVME167/MVME187 Single Board
* Computer Programmer's Reference Guide (MVME187PG/D2) with the April
* 1993 supplements/addenda (MVME187PG/D2A1).
*
* COPYRIGHT (c) 1989-2009.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -309,7 +312,7 @@ rtems_isr_entry set_vector(
#define EXTERN extern
#endif
extern rtems_isr_entry M68Kvec[]; /* vector table address */
extern void *M68Kvec[]; /* vector table address */
#ifdef __cplusplus
}
c/src/lib/libbsp/m68k/mvme167/startup/bspclean.c
+8 -11
View File
@@ -1,9 +1,12 @@
/* bspclean.c
/**
* @file
*
* These routines return control to 167Bug after a normal exit from the
* application.
*
* COPYRIGHT (c) 1989-2010.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -21,17 +24,11 @@
extern void start( void );
extern void page_table_teardown( void );
/*
* bsp_return_to_monitor_trap
/**
* @brief bsp_return_to_monitor_trap
*
* Switch the VBR back to ROM and make a .RETURN syscall to return control to
* 167 Bug. If 167Bug ever returns, restart the application.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
static void bsp_return_to_monitor_trap( void )
{
c/src/lib/libbsp/m68k/mvme167/startup/bspstart.c
+23 -35
View File
@@ -1,30 +1,5 @@
/* bspstart.c
*
* This set of routines starts the application. It includes application,
* board, and monitor specific initialization and configuration. The generic
* CPU dependent initialization has been performed before any of these are
* invoked.
*
* COPYRIGHT (c) 1989-2010.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* Modifications of respective RTEMS files:
* Copyright (c) 1998, National Research Council of Canada
*/
#include <bsp.h>
#include <page_table.h>
#include <fatal.h>
void M68KFPSPInstallExceptionHandlers (void);
extern rtems_isr_entry M68Kvec[];
/*
* bsp_start()
/**
* @file
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
@@ -43,22 +18,35 @@ extern rtems_isr_entry M68Kvec[];
*
* ASSUMES THAT 167BUG IS PRESENT TO CATCH ANY EXCEPTIONS DURING
* INITIALIZATION.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* Modifications of respective RTEMS files:
* Copyright (c) 1998, National Research Council of Canada
*/
#include <bsp.h>
#include <bsp/bootcard.h>
#include <page_table.h>
void M68KFPSPInstallExceptionHandlers (void);
void bsp_start( void )
{
rtems_isr_entry *rom_monitor_vector_table;
void **rom_monitor_vector_table;
int index;
/*
* 167Bug Vectors are at 0xFFE00000
*/
rom_monitor_vector_table = (rtems_isr_entry *)0xFFE00000;
rom_monitor_vector_table = (void **)0xFFE00000;
m68k_set_vbr( rom_monitor_vector_table );
/*
c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/mpisr.c
+10 -10
View File
@@ -1,6 +1,11 @@
/* Shm_isr_nobsp()
/**
* @file
*
* COPYRIGHT (c) 1989-1999.
* Template for Shared Memory Driver Interrupt Support
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -12,7 +17,7 @@
#include <bsp.h>
#include <shm_driver.h>
rtems_isr Shm_isr_nobsp( void )
rtems_isr Shm_isr_nobsp(rtems_vector_number ignored)
{
/*
* If this routine has to do anything other than the mpisr.c
@@ -22,20 +27,15 @@ rtems_isr Shm_isr_nobsp( void )
* must be cleared.
*
* If the generic mpisr.c satisifies your requirements, then
* remove this routine from your target's shmsupp/mpisb.c file.
* remove this routine from your target's shmsupp/mpisr.c file.
* Then simply install the generic Shm_isr in the Shm_setvec
* routine below.
*/
}
/* Shm_setvec
*
/*
* This driver routine sets the SHM interrupt vector to point to the
* driver's SHM interrupt service routine.
*
* Input parameters: NONE
*
* Output parameters: NONE
*/
void Shm_setvec( void )
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
+1
View File
@@ -66,6 +66,7 @@ libbsp_a_SOURCES += ../../shared/bsplibc.c \
startup/bspstart.c \
../../shared/bspclean.c \
startup/bspreset.c \
startup/bsprestart.c \
../../shared/bspgetworkarea.c \
../../shared/src/bsp-uboot-board-info.c \
../shared/uboot_getenv.c
c/src/lib/libbsp/powerpc/gen83xx/configure.ac
+1 -1
View File
@@ -76,7 +76,7 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
AC_CONFIG_FILES([Makefile])
RTEMS_BSP_BOOTCARD_OPTIONS
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
RTEMS_BSP_LINKCMDS
RTEMS_PPC_EXCEPTIONS
c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c
+61 -52
View File
@@ -20,10 +20,31 @@
#include <mpc83xx/mpc83xx_i2cdrv.h>
#include <libchip/i2c-2b-eeprom.h>
#include <libchip/i2c-sc620.h>
#include <bsp/irq.h>
#include <bsp.h>
static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
static void i2c1_probe(mpc83xx_i2c_softc_t *self)
{
#if MPC83XX_CHIP_TYPE != 8309
if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) {
self->base_frq =
(BSP_bus_frequency
/((mpc83xx.clk.sccr >> (31-1)) & 0x03));
}
#else /* MPC83XX_CHIP_TYPE != 8309 */
self->base_frq = BSP_bus_frequency;
#endif /* MPC83XX_CHIP_TYPE != 8309 */
}
#ifndef MPC83XX_BOARD_BR_UID
static void i2c2_probe(mpc83xx_i2c_softc_t *self)
{
self->base_frq = BSP_bus_frequency;
}
#endif /* MPC83XX_BOARD_BR_UID */
static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[] = {
/* first channel */
{
{/* public fields */
@@ -34,27 +55,26 @@ static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
.reg_ptr = &mpc83xx.i2c[0],
.initialized = FALSE,
.irq_number = BSP_IPIC_IRQ_I2C1,
.base_frq = 0 /* will be set during initiailization */
.base_frq = 0, /* will be set during probe */
.probe = i2c1_probe
}
},
}
#ifndef MPC83XX_BOARD_BR_UID
/* second channel */
{
, {
{ /* public fields */
.ops = &mpc83xx_i2c_ops,
.size = sizeof(mpc83xx_i2c_bus_tbl[1]),
.size = sizeof(mpc83xx_i2c_bus_tbl[0]),
},
{ /* our private fields */
.reg_ptr = &mpc83xx.i2c[1],
.initialized = FALSE,
.irq_number = BSP_IPIC_IRQ_I2C2,
.base_frq = 0 /* will be set during initiailization */
.base_frq = 0, /* will be set during probe */
.probe = i2c2_probe
}
}
};
rtems_libi2c_bus_t *mpc83xx_i2c_bus_descriptor[2] = {
&mpc83xx_i2c_bus_tbl[0].bus_desc,
&mpc83xx_i2c_bus_tbl[1].bus_desc
#endif /* MPC83XX_BOARD_BR_UID */
};
/*=========================================================================*\
@@ -76,8 +96,10 @@ rtems_status_code bsp_register_i2c
\*=========================================================================*/
{
int ret_code;
int i2c1_busno,i2c2_busno;
char device_path[] = "/dev/i2c?";
size_t n = RTEMS_ARRAY_SIZE(mpc83xx_i2c_bus_tbl);
size_t i;
int i2c_busno[n];
/*
* init I2C library (if not already done)
@@ -85,54 +107,41 @@ rtems_status_code bsp_register_i2c
rtems_libi2c_initialize ();
/*
* update input frequency of I2c modules into descriptor
* init I2C buses
*/
/*
* I2C1 is clocked with TSEC 1
*/
if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) {
mpc83xx_i2c_bus_tbl[0].softc.base_frq =
(BSP_bus_frequency
/((mpc83xx.clk.sccr >> (31-1)) & 0x03));
}
for (i = 0; i < n; ++i) {
mpc83xx_i2c_desc_t *desc = &mpc83xx_i2c_bus_tbl[i];
mpc83xx_i2c_bus_tbl[1].softc.base_frq = BSP_bus_frequency;
/*
* register first I2C bus
*/
ret_code = rtems_libi2c_register_bus("/dev/i2c1",
mpc83xx_i2c_bus_descriptor[0]);
if (ret_code < 0) {
return -ret_code;
(*desc->softc.probe)(&desc->softc);
device_path[sizeof(device_path) - 2] = (char) ('1' + i);
i2c_busno[i] = rtems_libi2c_register_bus(device_path, &desc->bus_desc);
}
i2c1_busno = ret_code;
/*
* register second I2C bus
*/
ret_code = rtems_libi2c_register_bus("/dev/i2c2",
mpc83xx_i2c_bus_descriptor[1]);
if (ret_code < 0) {
return -ret_code;
}
i2c2_busno = ret_code;
#ifdef RTEMS_BSP_I2C_EEPROM_DEVICE_NAME
/*
* register EEPROM to bus 1, Address 0x50
*/
ret_code = rtems_libi2c_register_drv(RTEMS_BSP_I2C_EEPROM_DEVICE_NAME,
i2c_2b_eeprom_driver_descriptor,
i2c1_busno,0x50);
if (ret_code < 0) {
return -ret_code;
if (n > 0) {
/*
* register EEPROM to bus 1, Address 0x50
*/
rtems_libi2c_register_drv(RTEMS_BSP_I2C_EEPROM_DEVICE_NAME,
i2c_2b_eeprom_driver_descriptor,
i2c_busno[0],0x50);
}
#endif /* RTEMS_BSP_I2C_EEPROM_DEVICE_NAME */
#ifdef MPC83XX_BOARD_BR_UID
if (n > 0) {
rtems_libi2c_register_drv(
"sc620",
&i2c_sc620_driver,
i2c_busno[0],
0x70
);
}
#endif /* MPC83XX_BOARD_BR_UID */
/*
* FIXME: register RTC driver, when available
*/
return 0;
return RTEMS_SUCCESSFUL;
}
c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
+2
View File
@@ -145,6 +145,8 @@ void mpc83xx_zero_4( void *dest, size_t n);
void cpu_init( void);
void bsp_restart(void *addr);
#ifdef __cplusplus
}
#endif
c/src/lib/libbsp/powerpc/gen83xx/startup/bsprestart.c
+46
View File
@@ -0,0 +1,46 @@
/*
* Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#include <bsp.h>
#include <bsp/u-boot.h>
#include <libcpu/powerpc-utility.h>
void bsp_restart(void *addr)
{
rtems_interrupt_level level;
void (*start)(void) = addr;
#ifdef HAS_UBOOT
const void *mem_begin = (const void *) bsp_uboot_board_info.bi_memstart;
size_t mem_size = bsp_uboot_board_info.bi_memsize;
#else /* HAS_UBOOT */
const void *mem_begin = bsp_ram_start;
size_t mem_size = (size_t) bsp_ram_size;
#endif /* HAS_UBOOT */
uint32_t hid0;
rtems_interrupt_disable(level);
hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0);
if ((hid0 & HID0_DCE) != 0) {
rtems_cache_flush_multiple_data_lines(mem_begin, mem_size);
}
hid0 &= ~(HID0_DCE | HID0_ICE);
PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
(*start)();
}
c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
+10 -3
View File
@@ -141,14 +141,21 @@ void cpu_init( void)
{
BAT dbat, ibat;
uint32_t msr;
uint32_t hid0;
/* Clear MMU and segment registers */
clear_mmu_regs();
/* Clear caches */
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK | HID0_ICE | HID0_DCE);
PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0);
if ((hid0 & (HID0_ICE | HID0_DCE)) == 0) {
hid0 &= ~(HID0_ILOCK | HID0_DLOCK | HID0_ICE | HID0_DCE);
PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
hid0 |= HID0_ICFI | HID0_DCI;
PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
hid0 &= ~(HID0_ICFI | HID0_DCI);
PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
}
/*
* Set up IBAT registers in MMU
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.br_uid
-1
View File
@@ -8,7 +8,6 @@ MEMORY {
RAM : ORIGIN = 0x0, LENGTH = 256M
ROM : ORIGIN = 0xfe000000, LENGTH = 2M
MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
NIRVANA : ORIGIN = 0x0, LENGTH = 0
}
INCLUDE linkcmds.base
c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
+5
View File
@@ -32,6 +32,11 @@ RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([gwlcfm],[])
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_USE_WRITE_THROUGH],[mpc5674f_ecu508*],[1])
RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_USE_WRITE_THROUGH],[*],[])
RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_USE_WRITE_THROUGH],
[use write-through for data cache])
RTEMS_BSPOPTS_SET([PPC_EXC_CONFIG_USE_FIXED_HANDLER],[*],[1])
RTEMS_BSPOPTS_HELP([PPC_EXC_CONFIG_USE_FIXED_HANDLER],
[use fixed high-level exception handler])
c/src/lib/libbsp/powerpc/mpc55xxevb/i2c/i2c_init.c
+7 -2
View File
@@ -24,6 +24,11 @@
#include <bsp/mpc83xx_i2cdrv.h>
#if MPC55XX_CHIP_FAMILY == 551
static void i2c_probe(mpc83xx_i2c_softc_t *self)
{
self->base_frq = bsp_clock_speed;
}
static mpc83xx_i2c_desc_t mpc55xx_i2c_bus = {
.bus_desc = {
.ops = &mpc83xx_i2c_ops,
@@ -33,7 +38,8 @@
.reg_ptr = (m83xxI2CRegisters_t *) 0xfff88000,
.initialized = FALSE,
.irq_number = MPC55XX_IRQ_I2C(0),
.base_frq = 0
.base_frq = 0,
.probe = i2c_probe
}
};
@@ -44,7 +50,6 @@
rtems_libi2c_initialize ();
mpc55xx_i2c_bus.softc.base_frq = bsp_clock_speed;
busno = rtems_libi2c_register_bus(
"/dev/i2c1",
&mpc55xx_i2c_bus.bus_desc
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c
+9 -5
View File
@@ -85,7 +85,11 @@ const struct MMU_tag mpc55xx_start_config_mmu [] = {
MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
/* External SRAM 2M */
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M, 0, 1, 1, 0),
#ifndef BSP_DATA_CACHE_USE_WRITE_THROUGH
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M, 0, 1, 1, 0),
#else
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M, 0, 1, 1, 2),
#endif
/* Internal SRAM 256k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0),
@@ -118,6 +122,8 @@ const struct MMU_tag mpc55xx_start_config_mmu [] = {
MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
/* External MRAM 4M */
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_4M, 0, 1, 1, 0),
/* Internal SRAM 256k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0),
@@ -125,13 +131,11 @@ const struct MMU_tag mpc55xx_start_config_mmu [] = {
MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0),
/* Used as cache-inhibited area (ADC, DSPI queues) */
MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1),
/* External MRAM 4M */
MPC55XX_MMU_TAG_INITIALIZER(15, 0x20000000, MPC55XX_MMU_4M, 0, 1, 1, 0),
/* External FPGA */
MPC55XX_MMU_TAG_INITIALIZER(16, 0x21000000, MPC55XX_MMU_8M, 0, 1, 1, 1),
MPC55XX_MMU_TAG_INITIALIZER(15, 0x21000000, MPC55XX_MMU_8M, 0, 1, 1, 1),
#if defined(MPC55XX_BOARD_MPC5674F_RSM6_KOMA)
/* External Ethernet controller */
MPC55XX_MMU_TAG_INITIALIZER(18, 0x23000000, MPC55XX_MMU_1K, 0, 1, 1, 1),
MPC55XX_MMU_TAG_INITIALIZER(17, 0x23000000, MPC55XX_MMU_1K, 0, 1, 1, 1),
#endif
#else
/* Used as cache-inhibited area (ADC, DSPI queues) */
c/src/lib/libbsp/powerpc/shared/src/memcpy.c
+3 -1
View File
@@ -15,7 +15,9 @@
#include <bspopts.h>
#include <rtems/powerpc/powerpc.h>
#if BSP_DATA_CACHE_ENABLED && PPC_CACHE_ALIGNMENT == 32
#if BSP_DATA_CACHE_ENABLED \
&& PPC_CACHE_ALIGNMENT == 32 \
&& !defined(BSP_DATA_CACHE_USE_WRITE_THROUGH)
#include <string.h>
#include <stdint.h>
c/src/lib/libbsp/powerpc/virtex4/include/irq.h
+2
View File
@@ -67,6 +67,8 @@ extern "C" {
} rtems_irq_symbolic_name;
extern rtems_irq_connect_data *BSP_rtems_irq_tbl;
void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data);
void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused);
void BSP_rtems_irq_mngt_init(unsigned cpuId);
#ifdef __cplusplus
c/src/lib/libbsp/powerpc/virtex4/irq/irq_init.c
+1 -1
View File
@@ -91,7 +91,7 @@ void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused)
/***********************************************************
* High level IRQ handler called from shared_raw_irq_code_entry
*/
int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
static int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
{
/*
* Handle interrupt
c/src/lib/libbsp/powerpc/virtex4/startup/bspstart.c
+2 -2
View File
@@ -139,7 +139,7 @@ void BSP_ask_for_reset(void)
void BSP_panic(char *s)
{
rtems_interrupt_level level;
__attribute__((unused)) rtems_interrupt_level level;
rtems_interrupt_disable(level);
@@ -151,7 +151,7 @@ void BSP_panic(char *s)
void _BSP_Fatal_error(unsigned int v)
{
rtems_interrupt_level level;
__attribute__((unused)) rtems_interrupt_level level;
rtems_interrupt_disable(level);
c/src/lib/libbsp/powerpc/virtex5/include/irq.h
+4 -3
View File
@@ -67,14 +67,15 @@ extern "C" {
} rtems_irq_symbolic_name;
extern rtems_irq_connect_data *BSP_rtems_irq_tbl;
void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data);
void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused);
void BSP_rtems_irq_mngt_init(unsigned cpuId);
#ifdef __cplusplus
}
#define BSP_DEC BSP_PIT
#define BSP_DECREMENTER BSP_PIT
#ifdef __cplusplus
}
#endif
#endif /* ASM */
c/src/lib/libbsp/powerpc/virtex5/irq/irq_init.c
+2 -2
View File
@@ -90,7 +90,7 @@ void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused)
SPR_RW(BOOKE_TSR)
int C_dispatch_dec_handler (BSP_Exception_frame *frame, unsigned int excNum)
static int C_dispatch_dec_handler (BSP_Exception_frame *frame, unsigned int excNum)
{
/* Acknowledge the interrupt */
_write_BOOKE_TSR( BOOKE_TSR_DIS );
@@ -105,7 +105,7 @@ int C_dispatch_dec_handler (BSP_Exception_frame *frame, unsigned int excNum)
/***********************************************************
* High level IRQ handler called from shared_raw_irq_code_entry
*/
int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
static int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
{
/*
* Handle interrupt
c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
+2 -2
View File
@@ -152,7 +152,7 @@ void BSP_ask_for_reset(void)
void BSP_panic(char *s)
{
rtems_interrupt_level level;
__attribute__((unused)) rtems_interrupt_level level;
rtems_interrupt_disable(level);
@@ -164,7 +164,7 @@ void BSP_panic(char *s)
void _BSP_Fatal_error(unsigned int v)
{
rtems_interrupt_level level;
__attribute__((unused)) rtems_interrupt_level level;
rtems_interrupt_disable(level);
c/src/lib/libbsp/shared/src/irq-server.c
+2 -2
View File
@@ -220,8 +220,8 @@ rtems_status_code rtems_interrupt_server_handler_remove(
sc = rtems_interrupt_handler_remove(
vector,
ie.entry->handler,
ie.entry->arg
bsp_interrupt_server_trigger,
ie.entry
);
if (sc != RTEMS_SUCCESSFUL) {
return sc;
c/src/lib/libbsp/sparc/leon3/leon_open_eth/leon_open_eth.c
+1 -1
View File
@@ -54,7 +54,7 @@ int rtems_leon_open_eth_driver_attach(
*(volatile int *) base_addr = 0;
*(volatile int *) base_addr = 0x800;
*(volatile int *) base_addr = 0;
leon_open_eth_configuration.base_address = base_addr;
leon_open_eth_configuration.base_address = (void *) base_addr;
leon_open_eth_configuration.vector = eth_irq + 0x10;
leon_open_eth_configuration.txd_count = TDA_COUNT;
leon_open_eth_configuration.rxd_count = RDA_COUNT;
c/src/lib/libbsp/sparc/leon3/shmsupp/getcfg.c
+11 -37
View File
@@ -1,27 +1,11 @@
/* void Shm_Get_configuration( localnode, &shmcfg )
/**
* @file
*
* This routine initializes, if necessary, and returns a pointer
* to the Shared Memory Configuration Table for the XXX target.
*
* INPUT PARAMETERS:
* localnode - local node number
* shmcfg - address of pointer to SHM Config Table
*
* OUTPUT PARAMETERS:
* *shmcfg - pointer to SHM Config Table
*
XXX: FIX THE COMMENTS BELOW WHEN THE CPU IS KNOWN
* NOTES: The XYZ does not have an interprocessor interrupt.
*
* The following table illustrates the configuration limitations:
*
* BUS MAX
* MODE ENDIAN NODES
* ========= ====== =======
* POLLED BIG 2+
* INTERRUPT **** NOT SUPPORTED ****
*
* COPYRIGHT (c) 1989-1999.
* LEON3 Shared Memory Driver Support - Configuration
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -35,7 +19,6 @@ XXX: FIX THE COMMENTS BELOW WHEN THE CPU IS KNOWN
/* multiprocessor communications interface (MPCI) table */
extern rtems_mpci_entry Shm_Get_packet(
rtems_packet_prefix **
);
@@ -56,19 +39,11 @@ extern rtems_mpci_entry Shm_Send_packet(
);
/* rtems_mpci_table MPCI_table = { */
/* 100000, /\* default timeout value in ticks *\/ */
/* MAX_PACKET_SIZE, /\* maximum packet size *\/ */
/* Shm_Initialization, /\* initialization procedure *\/ */
/* Shm_Get_packet, /\* get packet procedure *\/ */
/* Shm_Return_packet, /\* return packet procedure *\/ */
/* Shm_Send_packet, /\* packet send procedure *\/ */
/* Shm_Receive_packet /\* packet receive procedure *\/ */
/* }; */
/*
* configured if currently polling of interrupt driven
* configured if currently polling or interrupt driven
*
* NOTE: Code in mpisr.c is commented out. Fix when interrupt mode
* is added.
*/
#define INTERRUPT 0 /* XXX: */
@@ -95,7 +70,6 @@ void Shm_Get_configuration(
shm_config_table **shmcfg
)
{
extern rtems_configuration_table Configuration;
int i;
unsigned int tmp;
c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c
+10 -15
View File
@@ -1,12 +1,17 @@
/* Shared Memory Lock Routines
/**
* @file
*
* LEON3 Shared Memory Lock Routines
*
* This shared memory locked queue support routine need to be
* able to lock the specified locked queue. Interrupts are
* disabled while the queue is locked to prevent preemption
* and deadlock when two tasks poll for the same lock.
* previous level.
*
* COPYRIGHT (c) 1989-1999.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -20,11 +25,8 @@
/*
* Shm_Initialize_lock
*
* Initialize the lock for the specified locked queue.
*/
void Shm_Initialize_lock(
Shm_Locked_queue_Control *lq_cb
)
@@ -32,12 +34,12 @@ void Shm_Initialize_lock(
lq_cb->lock = LQ_UNLOCKED;
}
/* void _Shm_Lock( &lq_cb )
*
/*
* This shared memory locked queue support routine locks the
* specified locked queue. It disables interrupts to prevent
* a deadlock condition.
*/
extern unsigned int LEON3_Atomic_Swap(uint32_t value, uint32_t *address);
__asm__ (
".text\n"
@@ -63,16 +65,9 @@ void Shm_Lock(
Shm_isrstat = isr_level;
while ( lock_value ) {
lock_value = LEON3_Atomic_Swap(lock_value, lockptr);
/* __asm__ volatile( "" */
/* : "=r" (lockptr), "=r" (lock_value) */
/* : "0" (lockptr), "1" (lock_value) */
/* ); */
/*
* If not available, then may want to delay to reduce load on lock.
*/
/* if ( lock_value ) */
/* rtems_bsp_delay( 10 ); /\* approximately 10 microseconds *\/ */
}
}
c/src/lib/libbsp/sparc/leon3/shmsupp/mpisr.c
+17 -13
View File
@@ -1,6 +1,11 @@
/* Shm_isr_nobsp()
/**
* @file
*
* COPYRIGHT (c) 1989-1999.
* LEON3 Shared Memory Driver Interrupt Support
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -12,7 +17,8 @@
#include <bsp.h>
#include <shm_driver.h>
rtems_isr Shm_isr_nobsp( void )
#if 0
void Shm_isr(void)
{
/*
* If this routine has to do anything other than the mpisr.c
@@ -22,25 +28,23 @@ rtems_isr Shm_isr_nobsp( void )
* must be cleared.
*
* If the generic mpisr.c satisifies your requirements, then
* remove this routine from your target's shmsupp/mpisb.c file.
* remove this routine from your target's shmsupp/mpisr.c file.
* Then simply install the generic Shm_isr in the Shm_setvec
* routine below.
*/
}
#endif
/* Shm_setvec
*
/*
* This driver routine sets the SHM interrupt vector to point to the
* driver's SHM interrupt service routine.
*
* Input parameters: NONE
*
* Output parameters: NONE
*/
void Shm_setvec( void )
{
/*
* Interrupt driven mode is not currently supported.
* This is thought to be the interrupt to use.
*/
LEON_Unmask_interrupt(LEON3_MP_IRQ);
set_vector(Shm_isr, LEON_TRAP_TYPE(LEON3_MP_IRQ), 1);
set_vector((rtems_isr_entry) Shm_isr, LEON_TRAP_TYPE(LEON3_MP_IRQ), 1);
}
c/src/lib/libcpu/arm/at91rm9200/irq/irq.c
+3 -1
View File
@@ -10,6 +10,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -50,7 +52,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
/* disable all interrupts */
AIC_CTL_REG(AIC_IDCR) = 0xffffffff;
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libcpu/arm/lpc22xx/irq/irq.c
+3 -1
View File
@@ -9,6 +9,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -64,7 +66,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
VICVectAddr = 0;
/* Install the IRQ exception handler */
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c
+3 -1
View File
@@ -10,6 +10,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -36,7 +38,7 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
rtems_status_code bsp_interrupt_facility_initialize(void)
{
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libcpu/arm/pxa255/irq/irq.c
+3 -1
View File
@@ -9,6 +9,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -45,7 +47,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
XSCALE_INT_ICLR = 0x0;
/* Install the IRQ exception handler */
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libcpu/arm/s3c24xx/irq/irq.c
+3 -1
View File
@@ -12,6 +12,8 @@
* http://www.rtems.com/license/LICENSE.
*/
#include <rtems/score/armv4.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
@@ -37,7 +39,7 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
rtems_status_code bsp_interrupt_facility_initialize(void)
{
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
return RTEMS_SUCCESSFUL;
}
c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h
+2 -1
View File
@@ -157,7 +157,8 @@ extern "C" {
.VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \
}, \
.MAS2 = { .B = { \
.EPN = (addr) >> 10, .VLE = 0, .W = 0, .I = (io), .M = 0, .G = (io), .E = 0 } \
.EPN = (addr) >> 10, .VLE = 0, \
.W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \
}, \
.MAS3 = { .B = { \
.RPN = (addr) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \

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