mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-08-27 04:50:53 +08:00
Now using libchip instead of local precursor to libchip. Untested.
This commit is contained in:
Joel Sherrill
@@ -16,7 +16,7 @@ VPATH = @srcdir@
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PGM = ${ARCH}/console.rel
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# C source names, if any, go here -- minus the .c
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C_PIECES = console ns16550 z85c30 i8042vga i8042 vga
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C_PIECES = console i8042vga i8042 ns16550cfg z85c30cfg vga
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C_FILES = $(C_PIECES:%=%.c)
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C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
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@@ -17,15 +17,32 @@
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* $Id$
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*/
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#include <libchip/serial.h>
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#include <libchip/mc68681.h>
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#include <libchip/z85c30.h>
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#include "i8042vga.h"
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#include "ns16550.h"
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#include "z85c30.h"
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#include "ns16550cfg.h"
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#include "z85c30cfg.h"
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#include <pci.h>
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#define PMX1553_BUS 2
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#define PMX1553_SLOT 1
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/*
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* Based on BSP configuration information decide whether to do polling IO
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* or interrupt driven IO.
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*/
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#if (CONSOLE_USE_INTERRUPTS)
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#define NS16550_FUNCTIONS &ns16550_fns
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#define Z85C30_FUNCTIONS &z85c30_fns
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#else
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#define NS16550_FUNCTIONS &ns16550_fns_polled
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#define Z85C30_FUNCTIONS &z85c30_fns_polled
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#endif
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/*
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* Configuration specific probe routines
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*/
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@@ -73,6 +90,7 @@ static boolean config_z85c30_probe(int minor);
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console_tbl Console_Port_Tbl[] = {
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{
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"/dev/vga", /* sDeviceName */
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SERIAL_CUSTOM, /* deviceType */
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&i8042vga_fns, /* pDeviceFns */
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NULL, /* deviceProbe */
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NULL, /* pDeviceFlow */
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@@ -82,11 +100,17 @@ console_tbl Console_Port_Tbl[] = {
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I8042_CS, /* ulCtrlPort1 */
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0, /* ulCtrlPort2 */
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I8042_DATA, /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_KBD /* ulIntVector */
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},
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{
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"/dev/com1", /* sDeviceName */
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&ns16550_fns, /* pDeviceFns */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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NULL, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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16, /* ulMargin */
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@@ -95,11 +119,17 @@ console_tbl Console_Port_Tbl[] = {
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NS16550_PORT_A, /* ulCtrlPort1 */
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0, /* ulCtrlPort2 */
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NS16550_PORT_A, /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_COM1 /* ulIntVector */
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},
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{
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"/dev/ser1", /* sDeviceName */
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&ns16550_fns, /* pDeviceFns */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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80, /* ulMargin */
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@@ -108,11 +138,17 @@ console_tbl Console_Port_Tbl[] = {
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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1, /* Channel 1-4 */ /* ulDataPort */
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NULL, /* getRegister */
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NULL, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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0 /* RS232 */ /* ulIntVector */
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},
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{
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"/dev/ser2", /* sDeviceName */
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&ns16550_fns, /* pDeviceFns */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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80, /* ulMargin */
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@@ -121,11 +157,17 @@ console_tbl Console_Port_Tbl[] = {
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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2, /* Channel 1-4 */ /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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0 /* RS232 */ /* ulIntVector */
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},
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{
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"/dev/ser3", /* sDeviceName */
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&ns16550_fns, /* pDeviceFns */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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96, /* ulMargin */
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@@ -134,11 +176,17 @@ console_tbl Console_Port_Tbl[] = {
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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3, /* Channel 1-4 */ /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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0 /* RS232 */ /* ulIntVector */
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},
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{
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"/dev/ser4", /* sDeviceName */
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&ns16550_fns, /* pDeviceFns */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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96, /* ulMargin */
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@@ -147,12 +195,18 @@ console_tbl Console_Port_Tbl[] = {
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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4, /* Channel 1-4 */ /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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0 /* RS232 */ /* ulIntVector */
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},
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#if !PPCN_60X_USE_DINK
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{
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"/dev/com2", /* sDeviceName */
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&ns16550_fns, /* pDeviceFns */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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NULL, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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16, /* ulMargin */
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@@ -161,12 +215,18 @@ console_tbl Console_Port_Tbl[] = {
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NS16550_PORT_B, /* ulCtrlPort1 */
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0, /* ulCtrlPort2 */
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NS16550_PORT_B, /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_COM2 /* ulIntVector */
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},
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#endif
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{
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"/dev/com3", /* sDeviceName */
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&z85c30_fns, /* pDeviceFns */
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SERIAL_Z85C30, /* deviceType */
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Z85C30_FUNCTIONS, /* pDeviceFns */
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config_z85c30_probe, /* deviceProbe */
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&z85c30_flow_RTSCTS, /* pDeviceFlow */
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16, /* ulMargin */
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@@ -175,11 +235,17 @@ console_tbl Console_Port_Tbl[] = {
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Z85C30_CTRL_A, /* ulCtrlPort1 */
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Z85C30_CTRL_A, /* ulCtrlPort2 */
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Z85C30_DATA_A, /* ulDataPort */
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Read_85c30_register, /* getRegister */
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Write_85c30_register, /* setRegister */
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Read_85c30_data, /* getData */
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Write_85c30_data, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_COM3_4 /* ulIntVector */
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},
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{
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"/dev/com4", /* sDeviceName */
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&z85c30_fns, /* pDeviceFns */
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SERIAL_Z85C30, /* deviceType */
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Z85C30_FUNCTIONS, /* pDeviceFns */
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config_z85c30_probe, /* deviceProbe */
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&z85c30_flow_RTSCTS, /* pDeviceFlow */
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16, /* ulMargin */
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@@ -188,6 +254,11 @@ console_tbl Console_Port_Tbl[] = {
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Z85C30_CTRL_B, /* ulCtrlPort1 */
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Z85C30_CTRL_A, /* ulCtrlPort2 */
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Z85C30_DATA_B, /* ulDataPort */
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Read_85c30_register, /* getRegister */
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Write_85c30_register, /* setRegister */
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Read_85c30_data, /* getData */
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Write_85c30_data, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_COM3_4 /* ulIntVector */
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}
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};
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@@ -20,47 +20,9 @@
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*/
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#include <ringbuf.h>
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typedef struct _console_fns {
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boolean (*deviceProbe)(int minor);
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int (*deviceFirstOpen)(int major, int minor, void *arg);
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int (*deviceLastClose)(int major, int minor, void *arg);
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int (*deviceRead)(int minor);
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int (*deviceWrite)(int minor, const char *buf, int len);
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void (*deviceInitialize)(int minor);
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int (*deviceSetAttributes)(int minor, const struct termios *);
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void (*deviceWritePolled)(int minor, char cChar);
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int deviceOutputUsesInterrupts;
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} console_fns;
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typedef struct _console_flow {
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int (*deviceStopRemoteTx)(int minor);
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int (*deviceStartRemoteTx)(int minor);
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} console_flow;
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typedef struct _console_tbl {
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char *sDeviceName;
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console_fns *pDeviceFns;
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boolean (*deviceProbe)(int minor);
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console_flow *pDeviceFlow;
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unsigned32 ulMargin;
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unsigned32 ulHysteresis;
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void *pDeviceParams;
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unsigned32 ulCtrlPort1;
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unsigned32 ulCtrlPort2;
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unsigned32 ulDataPort;
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unsigned int ulIntVector;
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} console_tbl;
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typedef struct _console_data {
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void *termios_data;
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volatile boolean bActive;
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volatile Ring_buffer_t TxBuffer;
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/*
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* This field may be used for any purpose required by the driver
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*/
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void *pDeviceContext;
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} console_data;
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#include <libchip/serial.h>
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#include <libchip/ns16550.h>
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#include <libchip/z85c30.h>
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extern console_tbl Console_Port_Tbl[];
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extern console_data Console_Port_Data[];
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@@ -24,6 +24,7 @@
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#include <rtems.h>
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#include <bsp.h>
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#include <rtems/libio.h>
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#include <libchip/serial.h>
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#include <ringbuf.h>
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#include "console.h"
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File diff suppressed because it is too large
Load Diff
@@ -1,40 +0,0 @@
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/*
|
||||
* COPYRIGHT (c) 1998 by Radstone Technology
|
||||
*
|
||||
*
|
||||
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
|
||||
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
|
||||
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
|
||||
*
|
||||
* You are hereby granted permission to use, copy, modify, and distribute
|
||||
* this file, provided that this notice, plus the above copyright notice
|
||||
* and disclaimer, appears in all copies. Radstone Technology will provide
|
||||
* no support for this code.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _NS16550_H_
|
||||
#define _NS16550_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Driver function table
|
||||
*/
|
||||
extern console_fns ns16550_fns;
|
||||
extern console_fns ns16550_fns_polled;
|
||||
|
||||
/*
|
||||
* Flow control function tables
|
||||
*/
|
||||
extern console_flow ns16550_flow_RTSCTS;
|
||||
extern console_flow ns16550_flow_DTRCTS;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NS16550_H_ */
|
||||
@@ -1,196 +0,0 @@
|
||||
/*
|
||||
* COPYRIGHT (c) 1998 by Radstone Technology
|
||||
*
|
||||
*
|
||||
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
|
||||
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
|
||||
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
|
||||
*
|
||||
* You are hereby granted permission to use, copy, modify, and distribute
|
||||
* this file, provided that this notice, plus the above copyright notice
|
||||
* and disclaimer, appears in all copies. Radstone Technology will provide
|
||||
* no support for this code.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _NS16550_P_H_
|
||||
#define _NS16550_P_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/*
|
||||
* Define serial port read registers structure.
|
||||
*/
|
||||
|
||||
typedef volatile struct _SP_READ_REGISTERS {
|
||||
unsigned char ReceiveBuffer;
|
||||
unsigned char InterruptEnable;
|
||||
unsigned char InterruptId;
|
||||
unsigned char LineControl;
|
||||
unsigned char ModemControl;
|
||||
unsigned char LineStatus;
|
||||
unsigned char ModemStatus;
|
||||
unsigned char ScratchPad;
|
||||
} SP_READ_REGISTERS, *PSP_READ_REGISTERS;
|
||||
|
||||
/*
|
||||
* Define serial port write registers structure.
|
||||
*/
|
||||
|
||||
typedef volatile struct _SP_WRITE_REGISTERS {
|
||||
unsigned char TransmitBuffer;
|
||||
unsigned char InterruptEnable;
|
||||
unsigned char FifoControl;
|
||||
unsigned char LineControl;
|
||||
unsigned char ModemControl;
|
||||
unsigned char Reserved1;
|
||||
unsigned char ModemStatus;
|
||||
unsigned char ScratchPad;
|
||||
} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS;
|
||||
|
||||
/*
|
||||
* Define serial port interrupt enable register structure.
|
||||
*/
|
||||
|
||||
#define SP_INT_RX_ENABLE 0x01
|
||||
#define SP_INT_TX_ENABLE 0x02
|
||||
#define SP_INT_LS_ENABLE 0x04
|
||||
#define SP_INT_MS_ENABLE 0x08
|
||||
|
||||
/*
|
||||
* Define serial port interrupt id register structure.
|
||||
*/
|
||||
|
||||
typedef struct _SP_INTERRUPT_ID {
|
||||
unsigned char InterruptPending : 1;
|
||||
unsigned char Identification : 3;
|
||||
unsigned char Reserved1 : 2;
|
||||
unsigned char FifoEnabled : 2;
|
||||
} SP_INTERRUPT_ID, *PSP_INTERRUPT_ID;
|
||||
|
||||
/*
|
||||
* Define serial port fifo control register structure.
|
||||
*/
|
||||
#define SP_FIFO_ENABLE 0x01
|
||||
#define SP_FIFO_RXRST 0x02
|
||||
#define SP_FIFO_TXRST 0x04
|
||||
#define SP_FIFO_DMA 0x08
|
||||
#define SP_FIFO_RXLEVEL 0xc0
|
||||
|
||||
/*
|
||||
* Define serial port line control register structure.
|
||||
*/
|
||||
#define SP_LINE_SIZE 0x03
|
||||
#define SP_LINE_STOP 0x04
|
||||
#define SP_LINE_PAR 0x08
|
||||
#define SP_LINE_ODD 0x10
|
||||
#define SP_LINE_STICK 0x20
|
||||
#define SP_LINE_BREAK 0x40
|
||||
#define SP_LINE_DLAB 0x80
|
||||
|
||||
/*
|
||||
* Line status register character size definitions.
|
||||
*/
|
||||
#define FIVE_BITS 0x0 /* five bits per character */
|
||||
#define SIX_BITS 0x1 /* six bits per character */
|
||||
#define SEVEN_BITS 0x2 /* seven bits per character */
|
||||
#define EIGHT_BITS 0x3 /* eight bits per character */
|
||||
|
||||
/*
|
||||
* Line speed divisor definition.
|
||||
*/
|
||||
#define NS16550_Baud(baud_rate) (115200/baud_rate)
|
||||
|
||||
/*
|
||||
* Define serial port modem control register structure.
|
||||
*/
|
||||
#define SP_MODEM_DTR 0x01
|
||||
#define SP_MODEM_RTS 0x02
|
||||
#define SP_MODEM_IRQ 0x08
|
||||
#define SP_MODEM_LOOP 0x10
|
||||
#define SP_MODEM_DIV4 0x80
|
||||
|
||||
/*
|
||||
* Define serial port line status register structure.
|
||||
*/
|
||||
#define SP_LSR_RDY 0x01
|
||||
#define SP_LSR_EOVRUN 0x02
|
||||
#define SP_LSR_EPAR 0x04
|
||||
#define SP_LSR_EFRAME 0x08
|
||||
#define SP_LSR_BREAK 0x10
|
||||
#define SP_LSR_THOLD 0x20
|
||||
#define SP_LSR_TX 0x40
|
||||
#define SP_LSR_EFIFO 0x80
|
||||
|
||||
typedef struct _ns16550_context
|
||||
{
|
||||
unsigned8 ucModemCtrl;
|
||||
} ns16550_context;
|
||||
|
||||
/*
|
||||
* Driver functions
|
||||
*/
|
||||
static boolean ns16550_probe(int minor);
|
||||
|
||||
static void ns16550_init(int minor);
|
||||
|
||||
static int ns16550_open(
|
||||
int major,
|
||||
int minor,
|
||||
void * arg
|
||||
);
|
||||
|
||||
static int ns16550_close(
|
||||
int major,
|
||||
int minor,
|
||||
void * arg
|
||||
);
|
||||
|
||||
static void ns16550_write_polled(
|
||||
int minor,
|
||||
char cChar
|
||||
);
|
||||
|
||||
static void ns16550_assert_RTS(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void ns16550_negate_RTS(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void ns16550_assert_DTR(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void ns16550_negate_DTR(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void ns16550_initialize_interrupts(int minor);
|
||||
|
||||
static int ns16550_flush(int major, int minor, void *arg);
|
||||
|
||||
static int ns16550_write_support_int(
|
||||
int minor,
|
||||
const char *buf,
|
||||
int len
|
||||
);
|
||||
|
||||
static int ns16550_write_support_polled(
|
||||
int minor,
|
||||
const char *buf,
|
||||
int len
|
||||
);
|
||||
|
||||
static int ns16550_inbyte_nonblocking_polled(
|
||||
int minor
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NS16550_P_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,52 +0,0 @@
|
||||
/* z85c30.h
|
||||
*
|
||||
* This include file contains all console driver definations for the z85c30
|
||||
*
|
||||
* COPYRIGHT (c) 1998 by Radstone Technology
|
||||
*
|
||||
*
|
||||
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
|
||||
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
|
||||
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
|
||||
*
|
||||
* You are hereby granted permission to use, copy, modify, and distribute
|
||||
* this file, provided that this notice, plus the above copyright notice
|
||||
* and disclaimer, appears in all copies. Radstone Technology will provide
|
||||
* no support for this code.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id:
|
||||
*/
|
||||
|
||||
#ifndef __Z85C30_H
|
||||
#define __Z85C30_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Driver function table
|
||||
*/
|
||||
extern console_fns z85c30_fns;
|
||||
extern console_fns z85c30_fns_polled;
|
||||
|
||||
/*
|
||||
* Flow control function tables
|
||||
*/
|
||||
extern console_flow z85c30_flow_RTSCTS;
|
||||
extern console_flow z85c30_flow_DTRCTS;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,385 +0,0 @@
|
||||
/* z85c30_p.h
|
||||
*
|
||||
* This include file contains all private driver definations for the z85c30
|
||||
*
|
||||
* COPYRIGHT (c) 1998 by Radstone Technology
|
||||
*
|
||||
*
|
||||
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
|
||||
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
|
||||
* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
|
||||
*
|
||||
* You are hereby granted permission to use, copy, modify, and distribute
|
||||
* this file, provided that this notice, plus the above copyright notice
|
||||
* and disclaimer, appears in all copies. Radstone Technology will provide
|
||||
* no support for this code.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id:
|
||||
*/
|
||||
|
||||
#ifndef __Z85C30_P_H
|
||||
#define __Z85C30_P_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* bit values for write register 0 */
|
||||
/* command register */
|
||||
|
||||
#define SCC_WR0_SEL_WR0 0x00
|
||||
#define SCC_WR0_SEL_WR1 0x01
|
||||
#define SCC_WR0_SEL_WR2 0x02
|
||||
#define SCC_WR0_SEL_WR3 0x03
|
||||
#define SCC_WR0_SEL_WR4 0x04
|
||||
#define SCC_WR0_SEL_WR5 0x05
|
||||
#define SCC_WR0_SEL_WR6 0x06
|
||||
#define SCC_WR0_SEL_WR7 0x07
|
||||
#define SCC_WR0_SEL_WR8 0x08
|
||||
#define SCC_WR0_SEL_WR9 0x09
|
||||
#define SCC_WR0_SEL_WR10 0x0a
|
||||
#define SCC_WR0_SEL_WR11 0x0b
|
||||
#define SCC_WR0_SEL_WR12 0x0c
|
||||
#define SCC_WR0_SEL_WR13 0x0d
|
||||
#define SCC_WR0_SEL_WR14 0x0e
|
||||
#define SCC_WR0_SEL_WR15 0x0f
|
||||
#define SCC_WR0_SEL_RD0 0x00
|
||||
#define SCC_WR0_SEL_RD1 0x01
|
||||
#define SCC_WR0_SEL_RD2 0x02
|
||||
#define SCC_WR0_SEL_RD3 0x03
|
||||
#define SCC_WR0_SEL_RD4 0x04
|
||||
#define SCC_WR0_SEL_RD5 0x05
|
||||
#define SCC_WR0_SEL_RD6 0x06
|
||||
#define SCC_WR0_SEL_RD7 0x07
|
||||
#define SCC_WR0_SEL_RD8 0x08
|
||||
#define SCC_WR0_SEL_RD9 0x09
|
||||
#define SCC_WR0_SEL_RD10 0x0a
|
||||
#define SCC_WR0_SEL_RD11 0x0b
|
||||
#define SCC_WR0_SEL_RD12 0x0c
|
||||
#define SCC_WR0_SEL_RD13 0x0d
|
||||
#define SCC_WR0_SEL_RD14 0x0e
|
||||
#define SCC_WR0_SEL_RD15 0x0f
|
||||
#define SCC_WR0_NULL_CODE 0x00
|
||||
#define SCC_WR0_RST_INT 0x10
|
||||
#define SCC_WR0_SEND_ABORT 0x18
|
||||
#define SCC_WR0_EN_INT_RX 0x20
|
||||
#define SCC_WR0_RST_TX_INT 0x28
|
||||
#define SCC_WR0_ERR_RST 0x30
|
||||
#define SCC_WR0_RST_HI_IUS 0x38
|
||||
#define SCC_WR0_RST_RX_CRC 0x40
|
||||
#define SCC_WR0_RST_TX_CRC 0x80
|
||||
#define SCC_WR0_RST_TX_UND 0xc0
|
||||
|
||||
/* write register 2 */
|
||||
/* interrupt vector */
|
||||
|
||||
/* bit values for write register 1 */
|
||||
/* tx/rx interrupt and data transfer mode definition */
|
||||
|
||||
#define SCC_WR1_EXT_INT_EN 0x01
|
||||
#define SCC_WR1_TX_INT_EN 0x02
|
||||
#define SCC_WR1_PARITY 0x04
|
||||
#define SCC_WR1_RX_INT_DIS 0x00
|
||||
#define SCC_WR1_RX_INT_FIR 0x08
|
||||
#define SCC_WR1_INT_ALL_RX 0x10
|
||||
#define SCC_WR1_RX_INT_SPE 0x18
|
||||
#define SCC_WR1_RDMA_RECTR 0x20
|
||||
#define SCC_WR1_RDMA_FUNC 0x40
|
||||
#define SCC_WR1_RDMA_EN 0x80
|
||||
|
||||
/* bit values for write register 3 */
|
||||
/* receive parameters and control */
|
||||
|
||||
#define SCC_WR3_RX_EN 0x01
|
||||
#define SCC_WR3_SYNC_CHAR 0x02
|
||||
#define SCC_WR3_ADR_SEARCH 0x04
|
||||
#define SCC_WR3_RX_CRC_EN 0x08
|
||||
#define SCC_WR3_ENTER_HUNT 0x10
|
||||
#define SCC_WR3_AUTO_EN 0x20
|
||||
#define SCC_WR3_RX_5_BITS 0x00
|
||||
#define SCC_WR3_RX_7_BITS 0x40
|
||||
#define SCC_WR3_RX_6_BITS 0x80
|
||||
#define SCC_WR3_RX_8_BITS 0xc0
|
||||
|
||||
/* bit values for write register 4 */
|
||||
/* tx/rx misc parameters and modes */
|
||||
|
||||
#define SCC_WR4_PAR_EN 0x01
|
||||
#define SCC_WR4_PAR_EVEN 0x02
|
||||
#define SCC_WR4_SYNC_EN 0x00
|
||||
#define SCC_WR4_1_STOP 0x04
|
||||
#define SCC_WR4_2_STOP 0x0c
|
||||
#define SCC_WR4_8_SYNC 0x00
|
||||
#define SCC_WR4_16_SYNC 0x10
|
||||
#define SCC_WR4_SDLC 0x20
|
||||
#define SCC_WR4_EXT_SYNC 0x30
|
||||
#define SCC_WR4_1_CLOCK 0x00
|
||||
#define SCC_WR4_16_CLOCK 0x40
|
||||
#define SCC_WR4_32_CLOCK 0x80
|
||||
#define SCC_WR4_64_CLOCK 0xc0
|
||||
|
||||
/* bit values for write register 5 */
|
||||
/* transmit parameter and controls */
|
||||
|
||||
#define SCC_WR5_TX_CRC_EN 0x01
|
||||
#define SCC_WR5_RTS 0x02
|
||||
#define SCC_WR5_SDLC 0x04
|
||||
#define SCC_WR5_TX_EN 0x08
|
||||
#define SCC_WR5_SEND_BRK 0x10
|
||||
|
||||
#define SCC_WR5_TX_5_BITS 0x00
|
||||
#define SCC_WR5_TX_7_BITS 0x20
|
||||
#define SCC_WR5_TX_6_BITS 0x40
|
||||
#define SCC_WR5_TX_8_BITS 0x60
|
||||
#define SCC_WR5_DTR 0x80
|
||||
|
||||
/* write register 6 */
|
||||
/* sync chars or sdlc address field */
|
||||
|
||||
/* write register 7 */
|
||||
/* sync char or sdlc flag */
|
||||
|
||||
/* write register 8 */
|
||||
/* transmit buffer */
|
||||
|
||||
/* bit values for write register 9 */
|
||||
/* master interrupt control */
|
||||
|
||||
#define SCC_WR9_VIS 0x01
|
||||
#define SCC_WR9_NV 0x02
|
||||
#define SCC_WR9_DLC 0x04
|
||||
#define SCC_WR9_MIE 0x08
|
||||
#define SCC_WR9_STATUS_HI 0x10
|
||||
#define SCC_WR9_NO_RST 0x00
|
||||
#define SCC_WR9_CH_B_RST 0x40
|
||||
#define SCC_WR9_CH_A_RST 0x80
|
||||
#define SCC_WR9_HDWR_RST 0xc0
|
||||
|
||||
/* bit values for write register 10 */
|
||||
/* misc tx/rx control bits */
|
||||
|
||||
#define SCC_WR10_6_BIT_SYNC 0x01
|
||||
#define SCC_WR10_LOOP_MODE 0x02
|
||||
#define SCC_WR10_ABORT_UND 0x04
|
||||
#define SCC_WR10_MARK_IDLE 0x08
|
||||
#define SCC_WR10_ACT_POLL 0x10
|
||||
#define SCC_WR10_NRZ 0x00
|
||||
#define SCC_WR10_NRZI 0x20
|
||||
#define SCC_WR10_FM1 0x40
|
||||
#define SCC_WR10_FM0 0x60
|
||||
#define SCC_WR10_CRC_PRESET 0x80
|
||||
|
||||
/* bit values for write register 11 */
|
||||
/* clock mode control */
|
||||
|
||||
#define SCC_WR11_OUT_XTAL 0x00
|
||||
#define SCC_WR11_OUT_TX_CLK 0x01
|
||||
#define SCC_WR11_OUT_BR_GEN 0x02
|
||||
#define SCC_WR11_OUT_DPLL 0x03
|
||||
#define SCC_WR11_TRXC_OI 0x04
|
||||
#define SCC_WR11_TX_RTXC 0x00
|
||||
#define SCC_WR11_TX_TRXC 0x08
|
||||
#define SCC_WR11_TX_BR_GEN 0x10
|
||||
#define SCC_WR11_TX_DPLL 0x18
|
||||
#define SCC_WR11_RX_RTXC 0x00
|
||||
#define SCC_WR11_RX_TRXC 0x20
|
||||
#define SCC_WR11_RX_BR_GEN 0x40
|
||||
#define SCC_WR11_RX_DPLL 0x60
|
||||
#define SCC_WR11_RTXC_XTAL 0x80
|
||||
|
||||
/* write register 12 */
|
||||
/* lower byte of baud rate generator time constant */
|
||||
|
||||
/* write register 13 */
|
||||
/* upper byte of baud rate generator time constant */
|
||||
|
||||
/* bit values for write register 14 */
|
||||
/* misc control bits */
|
||||
|
||||
#define SCC_WR14_BR_EN 0x01
|
||||
#define SCC_WR14_BR_SRC 0x02
|
||||
#define SCC_WR14_DTR_FUNC 0x04
|
||||
#define SCC_WR14_AUTO_ECHO 0x08
|
||||
#define SCC_WR14_LCL_LOOP 0x10
|
||||
#define SCC_WR14_NULL 0x00
|
||||
#define SCC_WR14_SEARCH 0x20
|
||||
#define SCC_WR14_RST_CLK 0x40
|
||||
#define SCC_WR14_DIS_DPLL 0x60
|
||||
#define SCC_WR14_SRC_BR 0x80
|
||||
#define SCC_WR14_SRC_RTXC 0xa0
|
||||
#define SCC_WR14_FM_MODE 0xc0
|
||||
#define SCC_WR14_NRZI 0xe0
|
||||
|
||||
/* bit values for write register 15 */
|
||||
/* external/status interrupt control */
|
||||
|
||||
#define SCC_WR15_ZERO_CNT 0x02
|
||||
#define SCC_WR15_CD_IE 0x08
|
||||
#define SCC_WR15_SYNC_IE 0x10
|
||||
#define SCC_WR15_CTS_IE 0x20
|
||||
#define SCC_WR15_TX_UND_IE 0x40
|
||||
#define SCC_WR15_BREAK_IE 0x80
|
||||
|
||||
/* bit values for read register 0 */
|
||||
/* tx/rx buffer status and external status */
|
||||
|
||||
#define SCC_RR0_RX_AVAIL 0x01
|
||||
#define SCC_RR0_ZERO_CNT 0x02
|
||||
#define SCC_RR0_TX_EMPTY 0x04
|
||||
#define SCC_RR0_CD 0x08
|
||||
#define SCC_RR0_SYNC 0x10
|
||||
#define SCC_RR0_CTS 0x20
|
||||
#define SCC_RR0_TX_UND 0x40
|
||||
#define SCC_RR0_BREAK 0x80
|
||||
|
||||
/* bit values for read register 1 */
|
||||
|
||||
#define SCC_RR1_ALL_SENT 0x01
|
||||
#define SCC_RR1_RES_CD_2 0x02
|
||||
#define SCC_RR1_RES_CD_1 0x01
|
||||
#define SCC_RR1_RES_CD_0 0x08
|
||||
#define SCC_RR1_PAR_ERR 0x10
|
||||
#define SCC_RR1_RX_OV_ERR 0x20
|
||||
#define SCC_RR1_CRC_ERR 0x40
|
||||
#define SCC_RR1_END_FRAME 0x80
|
||||
|
||||
/* read register 2 */
|
||||
/* interrupt vector */
|
||||
|
||||
/* bit values for read register 3 */
|
||||
/* interrupt pending register */
|
||||
|
||||
#define SCC_RR3_B_EXT_IP 0x01
|
||||
#define SCC_RR3_B_TX_IP 0x02
|
||||
#define SCC_RR3_B_RX_IP 0x04
|
||||
#define SCC_RR3_A_EXT_IP 0x08
|
||||
#define SCC_RR3_A_TX_IP 0x10
|
||||
#define SCC_RR3_A_RX_IP 0x20
|
||||
|
||||
/* read register 8 */
|
||||
/* receive data register */
|
||||
|
||||
/* bit values for read register 10 */
|
||||
/* misc status bits */
|
||||
|
||||
#define SCC_RR10_ON_LOOP 0x02
|
||||
#define SCC_RR10_LOOP_SEND 0x10
|
||||
#define SCC_RR10_2_CLK_MIS 0x40
|
||||
#define SCC_RR10_1_CLK_MIS 0x80
|
||||
|
||||
/* read register 12 */
|
||||
/* lower byte of time constant */
|
||||
|
||||
/* read register 13 */
|
||||
/* upper byte of time constant */
|
||||
|
||||
/* bit values for read register 15 */
|
||||
/* external/status ie bits */
|
||||
|
||||
#define SCC_RR15_ZERO_CNT 0x02
|
||||
#define SCC_RR15_CD_IE 0x08
|
||||
#define SCC_RR15_SYNC_IE 0x10
|
||||
#define SCC_RR15_CTS_IE 0x20
|
||||
#define SCC_RR15_TX_UND_IE 0x40
|
||||
#define SCC_RR15_BREAK_IE 0x80
|
||||
|
||||
typedef struct _z85c30_context
|
||||
{
|
||||
unsigned8 ucModemCtrl;
|
||||
} z85c30_context;
|
||||
|
||||
/*
|
||||
* The following macro calculates the Baud constant. For the Z85C30 chip.
|
||||
*
|
||||
* Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
|
||||
* eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
|
||||
*/
|
||||
#define Z85C30_Baud( _baud_rate ) \
|
||||
( (Z85C30_CLOCK /( 16 * 2 * _baud_rate)) - 2)
|
||||
|
||||
#define Z85C30_Status_Is_RX_character_available(_status) \
|
||||
((_status) & SCC_RR0_RX_AVAIL)
|
||||
|
||||
#define Z85C30_Status_Is_TX_buffer_empty(_status) \
|
||||
((_status) & SCC_RR0_TX_EMPTY)
|
||||
|
||||
#define Z85C30_Status_Is_CTS_asserted(_status) \
|
||||
((_status) & SCC_RR0_CTS)
|
||||
|
||||
#define Z85C30_Status_Is_break_abort(_status) \
|
||||
((_status) & SCC_RR0_BREAK)
|
||||
|
||||
/*
|
||||
* Private routines
|
||||
*/
|
||||
static boolean z85c30_probe(int minor);
|
||||
|
||||
static void z85c30_init(int minor);
|
||||
|
||||
static int z85c30_open(
|
||||
int major,
|
||||
int minor,
|
||||
void * arg
|
||||
);
|
||||
|
||||
static int z85c30_close(
|
||||
int major,
|
||||
int minor,
|
||||
void * arg
|
||||
);
|
||||
|
||||
static void z85c30_write_polled(
|
||||
int minor,
|
||||
char cChar
|
||||
);
|
||||
|
||||
static void z85c30_assert_RTS(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void z85c30_negate_RTS(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void z85c30_assert_DTR(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void z85c30_negate_DTR(
|
||||
int minor
|
||||
);
|
||||
|
||||
static void z85c30_initialize_interrupts(int minor);
|
||||
|
||||
static int z85c30_flush(int major, int minor, void *arg);
|
||||
|
||||
static int z85c30_write_support_int(
|
||||
int minor,
|
||||
const char *buf,
|
||||
int len
|
||||
);
|
||||
|
||||
static int z85c30_write_support_polled(
|
||||
int minor,
|
||||
const char *buf,
|
||||
int len
|
||||
);
|
||||
|
||||
static int z85c30_inbyte_nonblocking_polled(
|
||||
int minor
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user