arm mcux-sdk: Address unused parameter warnings

Add "(void) param;" annotation to address unused parameter warnings. Found with GCC's warning -Wunused-parameter.
2026-09-22 07:06:42 +08:00 · 2025-10-10 22:01:39 +00:00
parent e9f922fc2b
commit d38f790263
47 changed files with 389 additions and 5 deletions
@@ -487,6 +487,10 @@ uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot)
 */
 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+    (void) freq;
+#endif
    uint32_t i;
    CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
    USB1->USBCMD |= USBHS_USBCMD_RST_MASK;
@@ -514,6 +518,10 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
 */
 bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+    (void) freq;
+#endif
    uint32_t i = 0;
    CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
    USB2->USBCMD |= USBHS_USBCMD_RST_MASK;
@@ -539,6 +547,10 @@ bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
 */
 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+    (void) freq;
+#endif
    static const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
    if ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) != 0U)
    {
@@ -1335,6 +1347,10 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
 */
 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+    (void) freq;
+#endif
    static const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
    CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll);
    USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
@@ -1096,6 +1096,9 @@ static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
                                    uint32_t configRegister,
                                    uint32_t inputOnfield)
 {
+#ifdef __rtems__
+    (void) configRegister;
+#endif
    *((volatile uint32_t *)muxRegister) =
        IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);

@@ -1128,6 +1131,12 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
                                       uint32_t configRegister,
                                       uint32_t configValue)
 {
+#ifdef __rtems__
+    (void) muxRegister;
+    (void) muxMode;
+    (void) inputRegister;
+    (void) inputDaisy;
+#endif
    if (configRegister != 0UL)
    {
        *((volatile uint32_t *)configRegister) = configValue;
@@ -1648,6 +1648,10 @@ uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex)
 */
 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+    (void) freq;
+#endif
    return true;
 }
 /*! brief Enable USB HS PHY PLL clock.
@@ -1661,6 +1665,9 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
 */
 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+#endif
    uint32_t phyPllDiv  = 0U;
    uint16_t multiplier = 0U;
    bool err            = false;
@@ -1768,10 +1775,17 @@ void CLOCK_DisableUsbhs0PhyPllClock(void)
 }
 bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+    (void) freq;
+#endif
    return true;
 }
 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
+#ifdef __rtems__
+    (void) src;
+#endif
    uint32_t phyPllDiv  = 0U;
    uint16_t multiplier = 0U;
    bool err            = false;
@@ -1637,6 +1637,9 @@ static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
                                    uint32_t configRegister,
                                    uint32_t inputOnfield)
 {
+#ifdef __rtems__
+    (void) configRegister;
+#endif
    *((volatile uint32_t *)muxRegister) =
        IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);

@@ -1669,6 +1672,12 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
                                       uint32_t configRegister,
                                       uint32_t configValue)
 {
+#ifdef __rtems__
+    (void) muxRegister;
+    (void) muxMode;
+    (void) inputRegister;
+    (void) inputDaisy;
+#endif
    if (configRegister != 0UL)
    {
        *((volatile uint32_t *)configRegister) = configValue;
@@ -633,6 +633,9 @@ static inline void PGMC_MIF_LockLowPowerConfigurationFields(PGMC_MIF_Type *base)
 */
 static inline void PGMC_PPC_TriggerPMICStandbySoftMode(PGMC_PPC_Type *base, bool enable)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    if (enable)
    {
        PGMC_PPC0->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK;
@@ -499,6 +499,9 @@ void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enabl
 */
 static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL);
 }

@@ -565,6 +568,9 @@ void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enabl
 */
 static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL);
 }

@@ -29,6 +29,9 @@

 void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    if (reset)
    {
        IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK;
@@ -41,6 +44,9 @@ void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset)

 void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    /* Pixel link control */
    VIDEO_MUX->PLM_CTRL.RW = 0U;

@@ -64,6 +70,9 @@ void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk)

 void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK;

    /* Pixel link control */
@@ -847,6 +847,9 @@ status_t ASRC_TransferNonBlocking(ASRC_Type *base, asrc_handle_t *handle, asrc_t
 */
 status_t ASRC_TransferGetConvertedCount(ASRC_Type *base, asrc_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -55,6 +55,11 @@ static void ASRC_OutEDMACallback(edma_handle_t *handle, void *userData, bool don
 ******************************************************************************/
 static void ASRC_InEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+    (void) done;
+    (void) tcds;
+#endif
    asrc_edma_private_handle_t *privHandle = (asrc_edma_private_handle_t *)userData;
    asrc_edma_handle_t *asrcHandle         = privHandle->handle;
    asrc_in_edma_handle_t *asrcInHandle    = &(privHandle->handle->in);
@@ -78,6 +83,11 @@ static void ASRC_InEDMACallback(edma_handle_t *handle, void *userData, bool done

 static void ASRC_OutEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+    (void) done;
+    (void) tcds;
+#endif
    asrc_edma_private_handle_t *privHandle = (asrc_edma_private_handle_t *)userData;
    asrc_edma_handle_t *asrcHandle         = privHandle->handle;
    asrc_out_edma_handle_t *asrcOutHandle  = &(privHandle->handle->out);
@@ -375,6 +385,9 @@ status_t ASRC_TransferEDMA(ASRC_Type *base, asrc_edma_handle_t *handle, asrc_tra
 */
 void ASRC_TransferInAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    /* Disable dma */
@@ -399,6 +412,10 @@ void ASRC_TransferInAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
 */
 void ASRC_TransferOutAbortEDMA(ASRC_Type *base, asrc_edma_handle_t *handle)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
+    assert(handle != NULL);
    assert(handle != NULL);

    /* Disable dma */
@@ -300,6 +300,9 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
 */
 void CDOG_Deinit(CDOG_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    NVIC_DisableIRQ(CDOG_IRQn);

 #if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
@@ -964,6 +964,9 @@ static status_t dcp_hash_check_context(dcp_hash_ctx_internal_t *ctxInternal, con
 */
 static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    status_t status;

    status = kStatus_InvalidArgument;
@@ -468,6 +468,9 @@ static void ENET_SetHandler(ENET_Type *base,
                            const enet_buffer_config_t *bufferConfig,
                            uint32_t srcClock_Hz)
 {
+#ifdef __rtems__
+    (void) srcClock_Hz;
+#endif
    uint8_t count;
    uint32_t instance                   = ENET_GetInstance(base);
    const enet_buffer_config_t *buffCfg = bufferConfig;
@@ -526,6 +529,9 @@ static void ENET_SetMacController(ENET_Type *base,
                                  uint8_t *macAddr,
                                  uint32_t srcClock_Hz)
 {
+#ifdef __rtems__
+    (void) handle;
+#endif
 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
    if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(base) == 1)
    {
@@ -786,6 +792,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle,
                                        const enet_config_t *config,
                                        const enet_buffer_config_t *bufferConfig)
 {
+#ifdef __rtems__
+    (void) handle;
+#endif
    assert(config != NULL);
    assert(bufferConfig != NULL);

@@ -852,6 +861,9 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle,
                                        const enet_config_t *config,
                                        const enet_buffer_config_t *bufferConfig)
 {
+#ifdef __rtems__
+    (void) handle;
+#endif
    assert(config != NULL);
    assert(bufferConfig != NULL);

@@ -1716,6 +1728,9 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ri
 status_t ENET_ReadFrame(
    ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts)
 {
+#ifdef __rtems__
+    (void) ts;
+#endif
    assert(handle != NULL);
    assert(FSL_FEATURE_ENET_INSTANCE_QUEUEn(base) != -1);
    assert(ringId < (uint8_t)FSL_FEATURE_ENET_INSTANCE_QUEUEn(base));
@@ -1871,6 +1886,9 @@ status_t ENET_SendFrame(ENET_Type *base,
                        bool tsFlag,
                        void *context)
 {
+#ifdef __rtems__
+    (void) tsFlag;
+#endif
    assert(handle != NULL);
    assert(data != NULL);
    assert(FSL_FEATURE_ENET_INSTANCE_QUEUEn(base) != -1);
@@ -2186,6 +2204,10 @@ status_t ENET_GetRxBuffer(ENET_Type *base,
                          bool *isLastBuff,
                          uint32_t *ts)
 {
+#ifdef __rtems__
+    (void) base;
+    (void) ts;
+#endif
    assert(handle != NULL);
    assert(ringId < (uint8_t)FSL_FEATURE_ENET_QUEUE);
    assert(handle->rxBdRing[ringId].rxBdBase != NULL);
@@ -2808,6 +2830,9 @@ status_t ENET_SendFrameZeroCopy(ENET_Type *base,
                                bool tsFlag,
                                void *context)
 {
+#ifdef __rtems__
+    (void) tsFlag;
+#endif
    assert(handle != NULL);
    assert(data != NULL);
    assert(ringId < (uint8_t)FSL_FEATURE_ENET_QUEUE);
@@ -3990,4 +4015,4 @@ void ENET1_1588_Timer_DriverIRQHandler(void)
    SDK_ISR_EXIT_BARRIER;
 }
 #endif /* ENET1 */
-#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
+#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
@@ -1129,6 +1129,9 @@ status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, ui
 */
 static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled)
 {
+#ifdef __rtems__
+    (void) rxEnabled;
+#endif
    uint32_t ecrReg = base->ECR;

 #if defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY
@@ -2043,4 +2046,4 @@ void ENET_TimeStampIRQHandler(ENET_Type *base, enet_handle_t *handle);

 /*! @}*/

-#endif /* _FSL_ENET_H_ */
+#endif /* _FSL_ENET_H_ */
@@ -1563,6 +1563,9 @@ static void FLEXCAN_GetSegments(CAN_Type *base,
                                uint32_t tqNum,
                                flexcan_timing_config_t *pTimingConfig)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    uint32_t ideal_sp;
    uint32_t seg1Max, proSegMax;
    uint32_t seg1Temp;
@@ -2027,6 +2030,9 @@ bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base,
                                             uint32_t sourceClock_Hz,
                                             flexcan_timing_config_t *pTimingConfig)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    /* Observe bit rate maximums */
    assert(bitRate <= MAX_CANFD_BITRATE);
    assert(bitRateFD <= MAX_CANFD_BITRATE);
@@ -3735,6 +3741,9 @@ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,

 status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);

    status_t result = kStatus_Success;
@@ -1336,6 +1336,9 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
 */
 status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    if (NULL == count)
    {
        return kStatus_InvalidArgument;
@@ -762,6 +762,9 @@ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t
 */
 status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status     = kStatus_Success;
@@ -790,6 +793,9 @@ status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handl
 */
 status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status     = kStatus_Success;
@@ -64,6 +64,11 @@ static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, boo
 ******************************************************************************/
 static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+    (void) done;
+    (void) tcds;
+#endif
    flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
    flexio_i2s_edma_handle_t *flexio_i2sHandle   = privHandle->handle;

@@ -84,6 +89,11 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo

 static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+    (void) done;
+    (void) tcds;
+#endif
    flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
    flexio_i2s_edma_handle_t *flexio_i2sHandle   = privHandle->handle;

@@ -397,6 +407,9 @@ void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_
 */
 status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -426,6 +439,9 @@ status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_e
 */
 status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -1244,6 +1244,9 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
 */
 status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -76,6 +76,9 @@ static flexio_spi_master_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_SPI_HA

 static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+#endif
    tcds                                                      = tcds;
    flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;

@@ -101,6 +104,9 @@ static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool t

 static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+#endif
    tcds                                                      = tcds;
    flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;

@@ -433,6 +439,9 @@ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
                                               flexio_spi_master_edma_handle_t *handle,
                                               size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -668,6 +668,9 @@ void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t
 */
 status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);
    assert(count != NULL);

@@ -857,6 +860,9 @@ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle
 */
 status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);
    assert(count != NULL);

@@ -361,6 +361,9 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
                                                 flexio_uart_edma_handle_t *handle,
                                                 size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);
    assert(handle->rxEdmaHandle != NULL);
    assert(count != NULL);
@@ -390,6 +393,9 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
 */
 status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);
    assert(handle->txEdmaHandle != NULL);
    assert(count != NULL);
@@ -1021,6 +1021,9 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
 */
 status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);

    status_t result = kStatus_Success;
@@ -143,6 +143,9 @@ void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base,
                                    flexspi_edma_handle_t *handle,
                                    flexspi_edma_transfer_nsize_t nsize)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    handle->nsize = nsize;
 }

@@ -31,6 +31,9 @@
 */
 void IEE_APC_GlobalEnable(IEE_APC_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    /* APC_x bits in GPR2 to GPR25 only take effect when this bit is set high */
    IOMUXC_LPSR_GPR->GPR25 |= IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK;
    __DSB();
@@ -46,6 +49,9 @@ void IEE_APC_GlobalEnable(IEE_APC_Type *base)
 */
 void IEE_APC_GlobalDisable(IEE_APC_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    /* APC_x bits in GPR2 to GPR25 only take effect when this bit is set high */
    IOMUXC_LPSR_GPR->GPR25 &= ~IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK;
    __DSB();
@@ -64,6 +70,9 @@ void IEE_APC_GlobalDisable(IEE_APC_Type *base)
 */
 status_t IEE_APC_SetRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, uint32_t startAddr, uint32_t endAddr)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    /* bit[2:0] of adress must be zero
     *
     * Note: For i.MXRT1170, region is [bot:top), the end is open interval. So the bit[2:0] of the end address must
@@ -148,6 +157,9 @@ status_t IEE_APC_SetRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, ui
 */
 status_t IEE_APC_LockRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, iee_apc_domain_t domain)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    if (region == kIEE_APC_Region0)
    {
        /* Locks write into APC Region 0 BOT address */
@@ -354,6 +366,9 @@ status_t IEE_APC_LockRegionConfig(IEE_APC_Type *base, iee_apc_region_t region, i
 */
 void IEE_APC_RegionEnable(IEE_APC_Type *base, iee_apc_region_t region)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    if (region == kIEE_APC_Region0)
    {
        IOMUXC_LPSR_GPR->GPR18 |= IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK;
@@ -212,6 +212,9 @@ status_t KEYMGR_SlotControl(KEY_MANAGER_Type *base, domain_slot_config_t *config
 */
 void KEYMGR_Init(KEY_MANAGER_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
    CLOCK_EnableClock(kCLOCK_Key_Manager);
 #endif
@@ -2189,6 +2189,9 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *
 */
 status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    status_t status = kStatus_Success;

    assert(NULL != handle);
@@ -438,6 +438,9 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
 */
 status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -523,6 +526,11 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl

 static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) dmaHandle;
+    (void) isTransferDone;
+    (void) tcds;
+#endif
    lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData;

    if (NULL == handle)
@@ -1005,6 +1005,9 @@ static bool LPSPI_MasterTransferWriteAllTxData(LPSPI_Type *base,

 static bool LPSPI_MasterTransferClearTCR(LPSPI_Type *base, lpspi_transfer_blocking_param_t *stateParams)
 {
+#ifdef __rtems__
+    (void) stateParams;
+#endif
 #if SPI_RETRY_TIMES
    uint32_t waitTimes = SPI_RETRY_TIMES;
    while ((LPSPI_GetTxFifoCount(base) == LPSPI_GetRxFifoSize(base)) && (--waitTimes != 0U))
@@ -1062,6 +1065,9 @@ static bool LPSPI_MasterTransferReadDataInFifo(LPSPI_Type *base,

 static bool LPSPI_MasterTransferReadDataInFifoNoBuf(LPSPI_Type *base, lpspi_transfer_blocking_param_t *stateParams)
 {
+#ifdef __rtems__
+    (void) stateParams;
+#endif
 #if SPI_RETRY_TIMES
    uint32_t waitTimes = SPI_RETRY_TIMES;
    while (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) && (--waitTimes != 0U))
@@ -1495,6 +1501,9 @@ static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t
 */
 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -1928,6 +1937,9 @@ static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *
 */
 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -523,6 +523,10 @@ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
                                     bool transferDone,
                                     uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) transferDone;
+    (void) tcds;
+#endif
    assert(edmaHandle != NULL);
    assert(g_lpspiEdmaPrivateHandle != NULL);

@@ -593,6 +597,9 @@ void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t
 */
 status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -956,6 +963,10 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
                                    bool transferDone,
                                    uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) transferDone;
+    (void) tcds;
+#endif
    assert(edmaHandle != NULL);
    assert(g_lpspiEdmaPrivateHandle != NULL);

@@ -1026,6 +1037,9 @@ void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *h
 */
 status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    if (NULL == count)
@@ -170,6 +170,9 @@ uint32_t LPUART_GetInstance(LPUART_Type *base)
 */
 size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);

    size_t size;
@@ -1581,6 +1584,9 @@ void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
 */
 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);
    assert(NULL != count);

@@ -1893,6 +1899,10 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)
 */
 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)
 {
+#ifdef __rtems__
+    (void) base;
+    (void) irqHandle;
+#endif
    /* To be implemented by User. */
 }
 #if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
@@ -424,6 +424,9 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha
 */
 status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);
    assert(NULL != handle->rxEdmaHandle);
    assert(NULL != count);
@@ -455,6 +458,9 @@ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handl
 */
 status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);
    assert(NULL != handle->txEdmaHandle);
    assert(NULL != count);
@@ -831,6 +831,10 @@ void DSI_GetDphyDefaultConfig(dsi_dphy_config_t *config, uint32_t txHsBitClk_Hz,
 void DSI_SetApbPacketControl(
    const MIPI_DSI_Type *base, uint16_t wordCount, uint8_t virtualChannel, dsi_tx_data_type_t dataType, uint8_t flags)
 {
+#ifdef __rtems__
+    (void) base;
+    (void) virtualChannel;
+#endif
    uint32_t pktCtrl = PKT_CONTROL_WORD_COUNT(wordCount) | PKT_CONTROL_HEADER_TYPE(dataType);

 #if defined(DSI_HOST_PKT_CONTROL_VC)
@@ -1375,6 +1379,9 @@ void DSI_TransferAbort(const MIPI_DSI_Type *base, dsi_handle_t *handle)
 */
 void DSI_TransferHandleIRQ(const MIPI_DSI_Type *base, dsi_handle_t *handle)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(NULL != handle);

    status_t status;
@@ -143,6 +143,9 @@ static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig)
 /* Initializes OCOTP controller. */
 void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz)
 {
+#ifdef __rtems__
+    (void) srcClock_Hz;
+#endif
    assert(NULL != base);
 #if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
    assert(0UL != srcClock_Hz);
@@ -86,6 +86,10 @@ static edma_modulo_t PDM_TransferMappingChannel(uint32_t *channel)

 static void PDM_EDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) done;
+    (void) tcds;
+#endif
    pdm_edma_private_handle_t *privHandle = (pdm_edma_private_handle_t *)userData;
    pdm_edma_handle_t *pdmHandle          = privHandle->handle;

@@ -451,6 +455,9 @@ void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)
 */
 status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    *count = handle->receivedBytes;
@@ -80,6 +80,9 @@ static status_t puf_waitForInit(PUF_Type *base)
 static void puf_powerOn(PUF_Type *base, puf_config_t *conf)
 {
 #if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0)
+#ifdef __rtems__
+    (void) conf;
+#endif
    /* RT6xxs */
    base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK);
    base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK);
@@ -91,6 +94,9 @@ static void puf_powerOn(PUF_Type *base, puf_config_t *conf)
    {
    }
 #else  /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */
+#ifdef __rtems__
+    (void) conf;
+#endif
    /* LPCXpresso55s69 & LPCXpresso54S018 */
    base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK;
    while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL))
@@ -1171,6 +1171,9 @@ status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_subm
 */
 uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    return s_pwmGetPwmDutyCycle[subModule][pwmChannel];
 }

@@ -1313,6 +1313,9 @@ static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)
        return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT);
    }
 #else
+#ifdef __rtems__
+    (void) axiIndex;
+#endif
    return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT);
 #endif
 }
@@ -751,6 +751,9 @@ void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, b
 */
 uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    return s_qtmrGetPwmDutyCycle[channel];
 }

@@ -91,6 +91,14 @@ void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base)
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 #if defined(RDC_SEMA42_CLOCKS)
    CLOCK_EnableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]);
+#else
+#ifdef __rtems__
+    (void) base;
+#endif
+#endif
+#else
+#ifdef __rtems__
+    (void) base;
 #endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
@@ -107,6 +115,14 @@ void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base)
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 #if defined(RDC_SEMA42_CLOCKS)
    CLOCK_DisableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]);
+#else
+#ifdef __rtems__
+    (void) base;
+#endif
+#endif
+#else
+#ifdef __rtems__
+    (void) base;
 #endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
@@ -1851,6 +1851,9 @@ void SAI_TxSetFormat(I2S_Type *base,
                     uint32_t mclkSourceClockHz,
                     uint32_t bclkSourceClockHz)
 {
+#ifdef __rtems__
+    (void) mclkSourceClockHz;
+#endif
    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);

    uint32_t bclk = 0;
@@ -1994,6 +1997,9 @@ void SAI_RxSetFormat(I2S_Type *base,
                     uint32_t mclkSourceClockHz,
                     uint32_t bclkSourceClockHz)
 {
+#ifdef __rtems__
+    (void) mclkSourceClockHz;
+#endif
    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);

    uint32_t bclk = 0;
@@ -2562,6 +2568,9 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa
 */
 status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status           = kStatus_Success;
@@ -2590,6 +2599,9 @@ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *
 */
 status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status           = kStatus_Success;
@@ -3828,4 +3840,4 @@ void SAI6_DriverIRQHandler(void)
    }
    SDK_ISR_EXIT_BARRIER;
 }
-#endif /* SAI6 */
+#endif /* SAI6 */
@@ -94,6 +94,9 @@ static uint32_t SAI_GetInstance(I2S_Type *base)

 static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) done;
+#endif
    sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData;
    sai_edma_handle_t *saiHandle          = privHandle->handle;
    status_t status                       = kStatus_SAI_TxBusy;
@@ -132,6 +135,9 @@ static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done,

 static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) done;
+#endif
    sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData;
    sai_edma_handle_t *saiHandle          = privHandle->handle;
    status_t status                       = kStatus_SAI_RxBusy;
@@ -959,6 +965,9 @@ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
 */
 status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -988,6 +997,9 @@ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle,
 */
 status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -1019,6 +1031,9 @@ status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *hand
 */
 uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    uint32_t validSlot = 0U;

    for (uint32_t i = 0U; i < (uint32_t)SAI_XFER_QUEUE_SIZE; i++)
@@ -96,8 +96,14 @@ uint32_t SEMA4_GetInstance(SEMA4_Type *base)
 void SEMA4_Init(SEMA4_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-#if defined(SEMA4_CLOCKS)
-    CLOCK_EnableClock(s_sema4Clocks[SEMA4_GetInstance(base)]);
+  #if defined(SEMA4_CLOCKS)
+      CLOCK_EnableClock(s_sema4Clocks[SEMA4_GetInstance(base)]);
+  #else
+      (void) base;
+  #endif
+#else
+#ifdef __rtems__
+    (void) base;
 #endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
@@ -114,6 +120,14 @@ void SEMA4_Deinit(SEMA4_Type *base)
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 #if defined(SEMA4_CLOCKS)
    CLOCK_DisableClock(s_sema4Clocks[SEMA4_GetInstance(base)]);
+#else
+  #ifdef __rtems__
+      (void) base;
+  #endif
+#endif
+#else
+#ifdef __rtems__
+    (void) base;
 #endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
@@ -249,6 +249,10 @@ void SNVS_HP_Init(SNVS_Type *base)
     defined(SNVS_HP_CLOCKS))
    uint32_t instance = SNVS_HP_GetInstance(base);
    CLOCK_EnableClock(s_snvsHpClock[instance]);
+#else
+#ifdef __rtems__
+    (void) base;
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }

@@ -263,6 +267,10 @@ void SNVS_HP_Deinit(SNVS_Type *base)
     defined(SNVS_HP_CLOCKS))
    uint32_t instance = SNVS_HP_GetInstance(base);
    CLOCK_DisableClock(s_snvsHpClock[instance]);
+#else
+#ifdef __rtems__
+    (void) base;
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }

@@ -270,6 +270,10 @@ void SNVS_LP_Deinit(SNVS_Type *base)
     defined(SNVS_LP_CLOCKS))
    uint32_t instance = SNVS_LP_GetInstance(base);
    CLOCK_DisableClock(s_snvsLpClock[instance]);
+#else
+#ifdef __rtems__
+    (void) base;
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }

@@ -542,6 +542,9 @@ status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *hand
 */
 status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status     = kStatus_Success;
@@ -570,6 +573,9 @@ status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, si
 */
 status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status     = kStatus_Success;
@@ -85,6 +85,11 @@ static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool don
 ******************************************************************************/
 static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+    (void) done;
+    (void) tcds;
+#endif
    spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData;
    spdif_edma_handle_t *spdifHandle        = privHandle->handle;

@@ -105,6 +110,11 @@ static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool don

 static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
+#ifdef __rtems__
+    (void) handle;
+    (void) done;
+    (void) tcds;
+#endif
    spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData;
    spdif_edma_handle_t *spdifHandle        = privHandle->handle;

@@ -550,6 +560,9 @@ void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handl
 */
 status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -579,6 +592,9 @@ status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *h
 */
 status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
    assert(handle != NULL);

    status_t status = kStatus_Success;
@@ -79,6 +79,9 @@ static void XRDC2_MakeDXACP(const xrdc2_access_policy_t policy[FSL_FEATURE_XRDC2
 */
 void XRDC2_Init(XRDC2_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
 }

 /*!
@@ -90,6 +93,9 @@ void XRDC2_Init(XRDC2_Type *base)
 */
 void XRDC2_Deinit(XRDC2_Type *base)
 {
+#ifdef __rtems__
+    (void) base;
+#endif
 }

 /*!