microblaze: Rework for RTEMS 6

This reworks the existing MicroBlaze architecture port and BSP to
achieve basic functionality using the latest RTEMS APIs.

bsps/include/bsp/fatal.h

@@ -174,6 +174,9 @@ typedef enum {
   IMXRT_FATAL_LPI2C_HW_INIT_FAILED,
   IMXRT_FATAL_LPI2C_REGISTER_FAILED,
   IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE,
+
+  /* MicroBlaze fatal codes */
+  MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16),
 } bsp_fatal_code;
 
 RTEMS_NO_RETURN static inline void

bsps/microblaze/include/bsp/linker-symbols.h

@@ -1,5 +1,7 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /*
- *  Copyright (C) 2015 Hesham Almatary
+ * Copyright (C) 2015 Hesham Almatary
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -7,8 +9,8 @@
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

bsps/microblaze/include/common/xil_types.h

@@ -0,0 +1,197 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 7.00  mus  01/07/19 Add cpp extern macro
+* 7.1   aru  08/19/19 Shift the value in UPPER_32_BITS only if it
+*                     is 64-bit processor
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief    Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief    Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
+ */
+#if defined (__aarch64__) || defined (__arch64__)
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+#else
+#define UPPER_32_BITS(n) 0U
+#endif
+/**
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/

bsps/microblaze/include/dev/serial/uartlite.h

@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI UART Lite terminal definitions
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_SHARED_UARTLITE_H
+#define LIBBSP_MICROBLAZE_SHARED_UARTLITE_H
+
+#include <rtems/termiostypes.h>
+
+#include <dev/serial/uartlite_l.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+  rtems_termios_device_context base;
+  uintptr_t address;
+  uint32_t initial_baud;
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  bool transmitting;
+#endif
+} uart_lite_context;
+
+extern const rtems_termios_device_handler microblaze_uart_fns;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_MICROBLAZE_SHARED_UARTLITE_H */

bsps/microblaze/microblaze_fpga/clock/clock.c

@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI Timer clock support
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/fatal.h>
+#include <bsp/timer.h>
+
+#include <rtems.h>
+#include <rtems/irq-extension.h>
+#include <rtems/timecounter.h>
+
+static rtems_timecounter_simple mblaze_tc;
+
+static uint32_t microblaze_tc_get( rtems_timecounter_simple *tc )
+{
+  volatile Microblaze_Timer *timer = _Microblaze_Timer;
+  return timer->tcr0;
+}
+
+static bool microblaze_tc_is_pending( rtems_timecounter_simple *tc )
+{
+  volatile Microblaze_Timer *timer = _Microblaze_Timer;
+  return ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0;
+}
+
+static uint32_t microblaze_tc_get_timecount( struct timecounter *tc )
+{
+  return rtems_timecounter_simple_downcounter_get(
+    tc,
+    microblaze_tc_get,
+    microblaze_tc_is_pending
+  );
+}
+
+static void microblaze_clock_initialize( void )
+{
+  volatile Microblaze_Timer *timer = _Microblaze_Timer;
+  /* Set load register to 0 */
+  timer->tlr0 = 0;
+  /* Reset the timer and interrupt */
+  timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | MICROBLAZE_TIMER_TCSR0_LOAD0;
+  /* Release the reset */
+  timer->tcsr0 = 0;
+  /*
+   * Enable interrupt, auto reload mode, external interrupt signal,
+   * and down counter
+   */
+  timer->tcsr0 =  MICROBLAZE_TIMER_TCSR0_ARHT0 | MICROBLAZE_TIMER_TCSR0_ENIT0 |
+                  MICROBLAZE_TIMER_TCSR0_GENT0 | MICROBLAZE_TIMER_TCSR0_UDT0;
+
+  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
+  uint32_t counter_frequency_in_hz = BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY;
+  uint32_t counter_ticks_per_clock_tick =
+    ( counter_frequency_in_hz * us_per_tick ) / 1000000;
+
+  /* Set a reset value for the timer counter */
+  timer->tlr0 = counter_ticks_per_clock_tick;
+  uint32_t control_status_reg = timer->tcsr0;
+  /* Load the reset value into the counter register */
+  timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0;
+  /* Enable the timer */
+  timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0;
+
+  rtems_timecounter_simple_install(
+    &mblaze_tc,
+    counter_frequency_in_hz,
+    counter_ticks_per_clock_tick,
+    microblaze_tc_get_timecount
+  );
+}
+
+static void microblaze_clock_at_tick( rtems_timecounter_simple *tc )
+{
+  volatile Microblaze_Timer *timer = _Microblaze_Timer;
+  if ( ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) {
+    return;
+  }
+  /* Clear the interrupt */
+  timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT;
+}
+
+static void microblaze_tc_tick( void )
+{
+  rtems_timecounter_simple_downcounter_tick(
+    &mblaze_tc,
+    microblaze_tc_get,
+    microblaze_clock_at_tick
+  );
+}
+
+static void microblaze_clock_handler_install( rtems_interrupt_handler isr )
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  sc = rtems_interrupt_handler_install(
+    0,
+    "Clock",
+    RTEMS_INTERRUPT_UNIQUE,
+    isr,
+    NULL
+  );
+
+  if ( sc != RTEMS_SUCCESSFUL ) {
+    bsp_fatal( MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL );
+  }
+}
+
+#define Clock_driver_support_initialize_hardware() microblaze_clock_initialize()
+#define Clock_driver_support_install_isr( isr ) \
+  microblaze_clock_handler_install( isr )
+#define Clock_driver_timecounter_tick() microblaze_tc_tick()
+
+/* Include shared source clock driver code */
+#include "../../shared/dev/clock/clockimpl.h"

bsps/microblaze/microblaze_fpga/console/console-io.c

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze console configuration
+ */
+
+/*
+ * Copyright (C) 2015 Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/console-termios.h>
+#include <dev/serial/uartlite.h>
+
+#include <bspopts.h>
+
+uart_lite_context microblaze_qemu_uart_context = {
+  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ),
+  .address = BSP_MICROBLAZE_FPGA_UART_BASE,
+  .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+  {
+    .device_file = "/dev/ttyS0",
+    .probe = console_device_probe_default,
+    .handler = &microblaze_uart_fns,
+    .context = &microblaze_qemu_uart_context.base
+  }
+};
+
+const size_t console_device_count = RTEMS_ARRAY_SIZE( console_device_table );

bsps/microblaze/microblaze_fpga/console/debug-io.c

@@ -1,13 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /**
  * @file
  *
- * @ingroup microblaze_uart
+ * @ingroup RTEMSBSPsMicroblaze
  *
- * @brief Console Configuration.
+ * @brief MicroBlaze debug IO support
  */
 
 /*
- *  Copyright (C) 2015 Hesham Almatary
+ * Copyright (C) 2015 Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -15,8 +18,8 @@
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -31,44 +34,33 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <dev/serial/uartlite_l.h>
 #include <rtems/bspIo.h>
 
-#include <libchip/serial.h>
-
 #include <bspopts.h>
-#include <bsp/uart.h>
 
-console_tbl Console_Configuration_Ports [] = {
-    {
-      .sDeviceName = "/dev/ttyS0",
-      .deviceType = SERIAL_CUSTOM,
-      .pDeviceFns = &microblaze_uart_fns,
-      .deviceProbe = NULL,
-      .pDeviceFlow = NULL,
-      .ulCtrlPort1 = UART_BASEADDRESS,
-      .ulCtrlPort2 = 0,
-      .ulClock = 9600,
-      .ulIntVector = 0
-    }
-};
-
-#define PORT_COUNT \
-  (sizeof(Console_Configuration_Ports) \
-    / sizeof(Console_Configuration_Ports [0]))
-
-unsigned long Console_Configuration_Count = PORT_COUNT;
-
-static void output_char(char c)
+static void output_char( char c )
 {
-  const console_fns *con =
-    Console_Configuration_Ports [Console_Port_Minor].pDeviceFns;
-
-  if (c == '\n') {
-    con->deviceWritePolled((int) Console_Port_Minor, '\r');
+  if ( c == '\n' ) {
+    XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, '\r' );
   }
-  con->deviceWritePolled((int) Console_Port_Minor, c);
+  XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, c );
+}
+
+static int xUartLite_RecvByte( int minor )
+{
+  if ( XUartLite_IsReceiveEmpty( BSP_MICROBLAZE_FPGA_UART_BASE ) ) {
+    return -1;
+  }
+
+  return XUartLite_ReadReg( BSP_MICROBLAZE_FPGA_UART_BASE, XUL_RX_FIFO_OFFSET );
+}
+
+static int get_char( void )
+{
+  return xUartLite_RecvByte( 0 );
 }
 
 BSP_output_char_function_type BSP_output_char = output_char;
 
-BSP_polling_getchar_function_type BSP_poll_char = NULL;
+BSP_polling_getchar_function_type BSP_poll_char = get_char;

bsps/microblaze/microblaze_fpga/include/bsp.h

@@ -1,5 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief Core BSP definitions
+ */
+
 /*
- *  Copyright (C) 2015 Hesham Almatary
+ * Copyright (C) 2015 Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -7,8 +18,8 @@
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -23,26 +34,20 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _BSP_H
-#define _BSP_H
+#ifndef LIBBSP_MICROBLAZE_FPGA_BSP_H
+#define LIBBSP_MICROBLAZE_FPGA_BSP_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #include <bspopts.h>
+#include <bsp/default-initial-extension.h>
 
 #include <rtems.h>
-#include <rtems/iosupp.h>
-#include <rtems/console.h>
-#include <rtems/clockdrv.h>
-
-/* support for simulated clock tick */
-Thread clock_driver_sim_idle_body(uintptr_t);
-#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif
+#endif /* LIBBSP_MICROBLAZE_FPGA_BSP_H */

bsps/microblaze/microblaze_fpga/include/bsp/intc.h

@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI Interrupt Controller definitions
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_FPGA_INTC_H
+#define LIBBSP_MICROBLAZE_FPGA_INTC_H
+
+#include <bspopts.h>
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+  /* Interrupt Status Register */
+  uint32_t isr;
+  uint32_t ipr;
+  /* Interrupt Enable Register */
+  uint32_t ier;
+  /* Interrupt Acknowledge Register */
+  uint32_t iar;
+  uint32_t sie;
+  uint32_t cie;
+  uint32_t ivr;
+#define MICROBLAZE_INTC_MER_HIE BSP_BIT32(1)
+#define MICROBLAZE_INTC_MER_ME BSP_BIT32(0)
+  /* Master Enable Register */
+  uint32_t mer;
+  /* Interrupt Mode Register, this is present only for Fast Interrupt */
+  uint32_t imr;
+  /* Interrupt Level Register */
+  uint32_t ilr;
+} Microblaze_INTC;
+
+#define _Microblaze_INTC ((volatile Microblaze_INTC *) BSP_MICROBLAZE_FPGA_INTC_BASE)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_MICROBLAZE_FPGA_INTC_H */

bsps/microblaze/microblaze_fpga/include/bsp/irq.h

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief BSP IRQ definitions
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_FPGA_IRQ_H
+#define LIBBSP_MICROBLAZE_FPGA_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#endif /* ASM */
+
+#define BSP_INTERRUPT_VECTOR_COUNT 32
+
+#endif /* LIBBSP_MICROBLAZE_FPGA_IRQ_H */

bsps/microblaze/microblaze_fpga/include/bsp/timer.h

@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI Timer definitions
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_MICROBLAZE_FPGA_TIMER_H
+#define LIBBSP_MICROBLAZE_FPGA_TIMER_H
+
+#include <bspopts.h>
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+#define MICROBLAZE_TIMER_TCSR0_T0INT BSP_BIT32(8)
+#define MICROBLAZE_TIMER_TCSR0_ENT0 BSP_BIT32(7)
+#define MICROBLAZE_TIMER_TCSR0_ENIT0 BSP_BIT32(6)
+#define MICROBLAZE_TIMER_TCSR0_LOAD0 BSP_BIT32(5)
+#define MICROBLAZE_TIMER_TCSR0_ARHT0 BSP_BIT32(4)
+#define MICROBLAZE_TIMER_TCSR0_GENT0 BSP_BIT32(2)
+#define MICROBLAZE_TIMER_TCSR0_UDT0 BSP_BIT32(1)
+  /* Control/Status register */
+  uint32_t tcsr0;
+  /* Load register */
+  uint32_t tlr0;
+  /* Timer counter register */
+  uint32_t tcr0;
+} Microblaze_Timer;
+
+#define _Microblaze_Timer ((volatile Microblaze_Timer *) BSP_MICROBLAZE_FPGA_TIMER_BASE)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_MICROBLAZE_FPGA_TIMER_H */

bsps/microblaze/microblaze_fpga/include/tm27.h

@@ -1,6 +1,15 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief BSP tm27 header
+ */
+
 /*
- *  COPYRIGHT (c) 1989-2011.
- *  On-Line Applications Research Corporation (OAR).
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -8,8 +17,8 @@
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -32,17 +41,18 @@
 #define __tm27_h
 
 /*
- *  Define the interrupt mechanism for Time Test 27
+ * Time Test 27 cannot be implemented reliably because the AXI interrupt
+ * controller is not guaranteed to support software interrupts.
  */
 
 #define MUST_WAIT_FOR_INTERRUPT 0
 
 #define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */
 
-#define Cause_tm27_intr()  /* XXX */
+#define Cause_tm27_intr()  /* empty */
 
-#define Clear_tm27_intr()  /* XXX */
+#define Clear_tm27_intr()  /* empty */
 
 #define Lower_tm27_intr() /* empty */
 
-#endif
+#endif /* __tm27_h */

bsps/microblaze/microblaze_fpga/irq/irq.c

@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze interrupt support
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/intc.h>
+#include <bsp/irq-generic.h>
+
+#include <rtems/score/cpu.h>
+
+static void ack_interrupt( uint8_t source )
+{
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  intc->iar = 0x1 << source;
+}
+
+rtems_status_code bsp_interrupt_get_attributes(
+  rtems_vector_number         vector,
+  rtems_interrupt_attributes *attributes
+)
+{
+  attributes->is_maskable = true;
+  attributes->maybe_enable = true;
+  attributes->maybe_disable = true;
+  attributes->can_clear = true;
+  attributes->cleared_by_acknowledge = true;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_is_pending(
+  rtems_vector_number vector,
+  bool               *pending
+)
+{
+  bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
+  bsp_interrupt_assert( pending != NULL );
+  *pending = false;
+  return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_raise( rtems_vector_number vector )
+{
+  bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
+  return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_clear( rtems_vector_number vector )
+{
+  bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
+
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  intc->iar = 0x1 << vector;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_is_enabled(
+  rtems_vector_number vector,
+  bool               *enabled
+)
+{
+  bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
+  bsp_interrupt_assert( enabled != NULL );
+
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  uint32_t mask = 1 << vector;
+
+  *enabled = (intc->ier & mask) != 0;
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector )
+{
+  bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
+
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  uint32_t mask = 1 << vector;
+
+  intc->ier |= mask;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector )
+{
+  bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
+
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  uint32_t mask = 1 << vector;
+
+  intc->ier &= ~mask;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+void bsp_interrupt_facility_initialize( void )
+{
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  /*
+   * Enable HW interrupts on the interrupt controller. This happens before
+   * interrupts are enabled on the processor.
+   */
+  intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE;
+}
+
+void bsp_interrupt_dispatch( uint32_t source )
+{
+  volatile Microblaze_INTC *intc = _Microblaze_INTC;
+  uint32_t vector_number = 0;
+
+  if ( source == 0xFF ) {
+    /* Read interrupt controller to get the source */
+    vector_number = intc->isr;
+
+    /* Handle and the first interrupt that is set */
+    uint8_t interrupt_status = 0;
+    for ( int i = 0; i < 32; i++ ) {
+      interrupt_status = vector_number >> i & 0x1;
+      if ( interrupt_status != 0 ) {
+        /* save current ILR */
+        uint32_t interrupt_levels = intc->ilr;
+        /* set ILR to block out every interrupt less than or equal to priority of i */
+        intc->ilr = 0xFFFFFFFF >> (32 - i);
+        bsp_interrupt_handler_dispatch( i );
+        ack_interrupt( i );
+        /* restore ILR */
+        intc->ilr = interrupt_levels;
+        break;
+      }
+    }
+  } else {
+    vector_number = source;
+
+    /* Fast interrupt mode. Handle interrupt. Ack happens automatically */
+    bsp_interrupt_handler_dispatch( vector_number );
+  }
+}

bsps/microblaze/microblaze_fpga/start/_exception_handler.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 /* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -34,5 +36,17 @@
 	.align 2
 
 	_exception_handler:
+#ifndef __rtems__
 	rtsd    r17, 0
 	nop
+#else /* __rtems__ */
+	/* Subtract stack frame */
+	addik r1, r1, -52
+
+	swi r5, r1, 8
+
+	addi r5, r0, 0xFFFF
+
+	braid _ISR_Handler
+	nop
+#endif /* __rtems__ */

bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 /* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -34,5 +36,17 @@
 	.align 2
 
 	_hw_exception_handler:
-	rted    r17, 0
+#ifndef __rtems__
+	rtsd    r17, 0
 	nop
+#else /* __rtems__ */
+	/* Subtract stack frame */
+	addik r1, r1, -52
+
+	swi r5, r1, 8
+
+	addi r5, r0, 0xFFFF
+
+	braid _ISR_Handler
+	nop
+#endif /* __rtems__ */

bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 /* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -34,5 +36,18 @@
 	.align 2
 
 	_interrupt_handler:
+#ifndef __rtems__
 	rtid    r14, 0
 	nop
+#else /* __rtems__ */
+	/* Subtract stack frame */
+	addik r1, r1, -52
+
+	swi r5, r1, 8
+
+	/* Indicate unknown interrupt source */
+	addi r5, r0, 0xFF
+
+	braid _ISR_Handler
+	nop
+#endif /* __rtems__ */

bsps/microblaze/microblaze_fpga/start/bspreset.c

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief BSP Reset
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems.h>
+#include <bsp/bootcard.h>
+
+void bsp_reset( void )
+{
+  __asm__ volatile (
+    "brai 0xFFFFFFFFFFFFFFFF"
+  );
+}

bsps/microblaze/microblaze_fpga/start/bspstart.c

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief BSP Startup
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+
+void bsp_start( void )
+{
+  bsp_interrupt_initialize();
+}

bsps/microblaze/microblaze_fpga/start/crtinit.S

@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are
+   met:
+
+   1.  Redistributions source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer.
+
+   2.  Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+   3.  Neither the name of Xilinx nor the names of its contributors may be
+   used to endorse or promote products derived from this software without
+   specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
+   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+	.globl _crtinit
+	.align 2
+	.ent _crtinit
+	.type _crtinit, @function
+_crtinit:
+	addi	r1, r1, -20			   	/* Save Link register	 */
+	swi	r15, r1, 0
+
+#ifndef __rtems__
+	addi	r6, r0, __sbss_start		  	/* clear SBSS */
+	addi	r7, r0, __sbss_end
+	rsub	r18, r6, r7
+	blei	r18, .Lendsbss
+
+.Lloopsbss:
+	swi	r0, r6, 0
+	addi	r6, r6, 4
+	rsub	r18, r6, r7
+	bgti	r18, .Lloopsbss
+.Lendsbss:
+#endif /* __rtems__ */
+
+#ifndef __rtems__
+	addi	r6, r0, __bss_start			 /* clear BSS */
+	addi	r7, r0, __bss_end
+#else
+	addi  r6, r0, bsp_section_bss_begin
+	addi  r7, r0, bsp_section_bss_end
+#endif	/* __rtems__ */
+	rsub	r18, r6, r7
+	blei	r18, .Lendbss
+.Lloopbss:
+	swi	r0, r6, 0
+	addi	r6, r6, 4
+	rsub	r18, r6, r7
+	bgti	r18, .Lloopbss
+.Lendbss:
+
+#ifndef __rtems__
+	brlid	r15, _program_init		 	 /* Initialize the program  */
+	nop
+
+	brlid   r15, __init					 /* Invoke language initialization functions */
+	nop
+#endif /* __rtems__ */
+
+	addi	r6, r0, 0					   /* Initialize argc = 1 and argv = NULL and envp = NULL  */
+	addi	r7, r0, 0
+#ifndef __rtems__
+	brlid	r15, main					   /* Execute the program */
+#else
+	brlid	r15, boot_card
+#endif /* __rtems__ */
+	addi	r5, r0, 0
+
+	addik   r19, r3, 0					  /* Save return value */
+
+#ifndef __rtems__
+	brlid   r15, __fini					 /* Invoke language cleanup functions */
+	nop
+
+	brlid	r15, _program_clean			 /* Cleanup the program  */
+	nop
+#endif /* __rtems__ */
+
+	lw r15, r1, r0					 /* Return back to CRT   */
+
+	addik r3, r19, 0					  /* Restore return value */
+	rtsd r15, 8
+	addi r1, r1, 20
+	.end _crtinit

bsps/microblaze/shared/cache/cache.c

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze cache support
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "../../../bsps/shared/cache/cacheimpl.h"

bsps/microblaze/shared/dev/serial/uartlite.c

@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze AXI UART Lite support
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/irq.h>
+#include <dev/serial/uartlite.h>
+
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+static void microblaze_uart_interrupt( void *arg )
+{
+  rtems_termios_tty *tty = arg;
+  uart_lite_context *ctx = rtems_termios_get_device_context( tty );
+
+  while ( !XUartLite_IsReceiveEmpty( ctx->address ) ) {
+    char c = (char) XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET );
+    rtems_termios_enqueue_raw_characters( tty, &c, 1 );
+  }
+
+  while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx ) ) {
+    rtems_termios_dequeue_characters( tty, 1 );
+  }
+}
+#endif
+
+static bool uart_first_open(
+  struct rtems_termios_tty *tty,
+  rtems_termios_device_context *base,
+  struct termios *term,
+  rtems_libio_open_close_args_t *args
+)
+{
+  uart_lite_context *ctx = (uart_lite_context *) base;
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  rtems_status_code sc;
+#endif
+
+  rtems_termios_set_initial_baud( tty, ctx->initial_baud );
+
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  XUartLite_EnableIntr( ctx->address );
+  sc = rtems_interrupt_handler_install(
+    1,
+    "UART",
+    RTEMS_INTERRUPT_SHARED,
+    microblaze_uart_interrupt,
+    tty
+  );
+  if ( sc != RTEMS_SUCCESSFUL ) {
+    return false;
+  }
+#endif
+
+  return true;
+}
+
+static void uart_last_close(
+  rtems_termios_tty *tty,
+  rtems_termios_device_context *base,
+  rtems_libio_open_close_args_t *args
+)
+{
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  rtems_interrupt_handler_remove( 1, microblaze_uart_interrupt, tty );
+#endif
+}
+
+#ifndef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+static int uart_read_polled( rtems_termios_device_context *base )
+{
+  uart_lite_context *ctx = (uart_lite_context *) base;
+
+  if ( XUartLite_IsReceiveEmpty( ctx->address ) ) {
+    return -1;
+  }
+
+  return XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET );
+}
+#endif
+
+static void uart_write(
+  rtems_termios_device_context *base,
+  const char *s,
+  size_t n
+)
+{
+  uart_lite_context *ctx = (uart_lite_context *) base;
+
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  if ( n > 0 ) {
+    ctx->transmitting = true;
+    XUartLite_SendByte( ctx->address, s[0] );
+  } else {
+    ctx->transmitting = false;
+  }
+#else
+  size_t i = 0;
+
+  for ( i = 0; i < n; ++i ) {
+    XUartLite_SendByte( ctx->address, s[i] );
+  }
+#endif
+}
+
+const rtems_termios_device_handler microblaze_uart_fns = {
+  .first_open = uart_first_open,
+  .last_close = uart_last_close,
+  .write = uart_write,
+#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+  .mode = TERMIOS_IRQ_DRIVEN
+#else
+  .poll_read = uart_read_polled,
+  .mode = TERMIOS_POLLED
+#endif
+};

bsps/microblaze/shared/dev/serial/uartlite_l.c

@@ -0,0 +1,99 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @file xuartlite_l.c
+* @addtogroup uartlite_v3_5
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/25/02 First release
+* 1.12a rpm  07/16/07 Fixed arg type for RecvByte
+* 2.00a ktn  10/20/09 The macros have been renamed to remove _m from the name.
+* 3.2   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototypes of XUartLite_SendByte,
+*                     XUartLite_RecvByte APIs.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#ifndef __rtems__
+#include "xuartlite_l.h"
+#else
+#include <dev/serial/uartlite_l.h>
+#endif /* __rtems__ */
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the UART. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	Data is the byte of data to send
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data)
+{
+	while (XUartLite_IsTransmitFull(BaseAddress));
+
+	XUartLite_WriteReg(BaseAddress, XUL_TX_FIFO_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the UART. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param	BaseAddress is the base address of the device
+*
+* @return	The byte of data received.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 XUartLite_RecvByte(UINTPTR BaseAddress)
+{
+	while (XUartLite_IsReceiveEmpty(BaseAddress));
+
+	return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET);
+}
+
+/** @} */

bsps/microblaze/shared/start/start.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 /* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -34,76 +36,79 @@
          Address                Vector type                 Label
          -------                -----------                 ------
 
-	# 0x00 #		(-- IMM --)
-	# 0x04 #                Reset                       _start1
+		# 0x00 #				(-- IMM --)
+		# 0x04 #				Reset                       _start1
 
-	# 0x08 #		(-- IMM --)
-	# 0x0c #		Software Exception          _exception_handler
+		# 0x08 #				(-- IMM --)
+		# 0x0c #				Software Exception          _exception_handler
 
-	# 0x10 #		(-- IMM --)
-	# 0x14 #		Hardware Interrupt          _interrupt_handler
+		# 0x10 #				(-- IMM --)
+		# 0x14 #				Hardware Interrupt          _interrupt_handler
 
-        # 0x18 #                (-- IMM --)
-        # 0x1C #                Breakpoint Exception        (-- Don't Care --)
+		# 0x18 #				(-- IMM --)
+		# 0x1C #				Breakpoint Exception        (-- Don't Care --)
 
-        # 0x20 #                (-- IMM --)
-        # 0x24 #                Hardware Exception          _hw_exception_handler
+		# 0x20 #				(-- IMM --)
+		# 0x24 #				Hardware Exception          _hw_exception_handler
 
 */
 
 
 	.globl _start
-        .section .vectors.reset, "ax"
+	.section .vectors.reset, "ax"
 	.align 2
-        .ent _start
-        .type _start, @function
+	.ent _start
+	.type _start, @function
 _start:
-        brai    _start1
-        .end _start
+	brai _start1
+	.end _start
 
-        .section .vectors.sw_exception, "ax"
-        .align 2
+	.section .vectors.sw_exception, "ax"
+	.align 2
 _vector_sw_exception:
-        brai    _exception_handler
+	brai _exception_handler
 
-        .section .vectors.interrupt, "ax"
-        .align 2
+	.section .vectors.interrupt, "ax"
+	.align 2
 _vector_interrupt:
-        brai    _interrupt_handler
+	brai _interrupt_handler
 
-        .section .vectors.hw_exception, "ax"
-        .align 2
+	.section .vectors.hw_exception, "ax"
+	.align 2
 _vector_hw_exception:
-        brai    _hw_exception_handler
+	brai _hw_exception_handler
 
-        .section .text
-        .globl _start1
-        .align 2
-        .ent _start1
-        .type _start1, @function
+	.section .text
+	.globl _start1
+	.align 2
+	.ent _start1
+	.type _start1, @function
 _start1:
-	//la	r13, r0, _SDA_BASE_         /* Set the Small Data Anchors and the stack pointer */
-	//la	r2, r0, _SDA2_BASE_
-	la	r1, r0, bsp_section_stack_begin-16           /* 16 bytes (4 words are needed by crtinit for args and link reg */
+	//la r13, r0, _SDA_BASE_         /* Set the Small Data Anchors and the stack pointer */
+	//la r2, r0, _SDA2_BASE_
+	la r1, r0, _ISR_Stack_area_end-16           /* 16 bytes (4 words are needed by crtinit for args and link reg */
 
-	brlid	r15, _crtinit               /* Initialize BSS and run program */
+	brlid r15, _crtinit               /* Initialize BSS and run program */
 	nop
 
-        brlid   r15, exit                   /* Call exit with the return value of main */
-        addik   r5, r3, 0
-
-        /* Control does not reach here */
-        .end _start1
+#ifndef __rtems__
+	brlid   r15, exit                   /* Call exit with the return value of main */
+	addik   r5, r3, 0
+#endif /* __rtems__ */
 
+	/* Control does not reach here */
+	.end _start1
 
+#ifndef __rtems__
 /*
-        _exit
-        Our simple _exit
+	_exit
+	Our simple _exit
 */
-        .globl _exit
-        .align 2
-        .ent _exit
-        .type _exit, @function
+	.globl _exit
+	.align 2
+	.ent _exit
+	.type _exit, @function
 _exit:
-        bri     0
+	bri     0
 	.end _exit
+#endif /* __rtems__ */

c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S

@@ -1,85 +0,0 @@
-## Copyright (c) 2015, Hesham Almatary
-## Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
-##
-## Redistribution and use in source and binary forms, with or without
-## modification, are permitted provided that the following conditions are
-## met:
-##
-## 1.  Redistributions source code must retain the above copyright notice,
-## this list of conditions and the following disclaimer.
-##
-## 2.  Redistributions in binary form must reproduce the above copyright
-## notice, this list of conditions and the following disclaimer in the
-## documentation and/or other materials provided with the distribution.
-##
-## 3.  Neither the name of Xilinx nor the names of its contributors may be
-## used to endorse or promote products derived from this software without
-## specific prior written permission.
-##
-## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
-## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#
-# sim-crtinit.s
-#
-# Default second stage of C run-time initialization that does not peform
-# BSS initialization to zero. Typical use is on a simulator.
-#
-
-	.globl _crtinit
-	.align 2
-	.ent _crtinit
-
-_crtinit:
-	addi	r1, r1, -20               	/* Save Link register	 */
-	swi	r15, r1, 0
-
-#ifndef __rtems__
-	brlid	r15, _program_init              /* Initialize the program  */
-	nop
-
-        brlid   r15, __init                     /* Invoke language initialization functions */
-        nop
-#endif
-
-
-  /* Init .bss */
-  addi  r6, r0, bsp_section_bss_begin
-  addi  r7, r0, bsp_section_bss_end
-
-_clear_bss_loop:
-  swi   r0, r6, 0
-
-  addi  r6, r6, 4
-  cmpu  r8, r6, r7
-  bgti  r8, _clear_bss_loop
-
-	addi	r6, r0, 0                       /* Initialize argc = 1 and argv = NULL and envp = NULL  */
-	addi	r7, r0, 0
-	brlid	r15, boot_card                  /* Execute the program */
-	addi	r5, r0, 0
-
-        addik   r19, r3, 0                      /* Save return value */
-
-#ifndef __rtems__
-        brlid   r15, __fini                     /* Invoke language cleanup functions */
-        nop
-
-	brlid	r15, _program_clean             /* Cleanup the program  */
-	nop
-#endif
-
-	lw	r15, r1, r0                     /* Return back to CRT   */
-        addik   r3, r19, 0                      /* Restore return value */
-	rtsd	r15, 8
-	addi	r1, r1, 20
-	.end _crtinit

cpukit/score/cpu/microblaze/__tls_get_addr.c

@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze thread-local storage implementation
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/score/threadimpl.h>
+#include <rtems/score/tls.h>
+
+#include <assert.h>
+
+void *__tls_get_addr( const TLS_Index *ti );
+
+void *__tls_get_addr( const TLS_Index *ti )
+{
+  const Thread_Control *executing = _Thread_Get_executing();
+  void *tls_block = (char *) executing->Start.tls_area
+    + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+
+  return (char *) tls_block + ti->offset;
+}

cpukit/score/cpu/microblaze/cpu_asm.S

@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze interrupt handler implementation
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/asm.h>
+#include <rtems/score/percpu.h>
+
+	.text
+	.globl _ISR_Handler
+	.align 2
+
+_ISR_Handler:
+	/* Save stack frame */
+	swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+	swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+	swi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+	swi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+	swi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+	swi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+	swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+	swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+	swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+	swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+	swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+
+	xori r3, r5, 0xFFFF
+	beqi r3, do_exception
+
+	/* Disable dispatching */
+	lwi r3, r0, _Per_CPU_Information + 16
+	addik r3, r3, 1
+	swi r3, r0, _Per_CPU_Information + 16
+
+	swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+
+	/* Is SP < INTERRUPT_STACK_LOW? */
+	lwi r4, r0, _Per_CPU_Information
+	rsubk r3, r4, r1
+	blei r3, switch_to_interrupt_stack
+
+	/* Is SP > INTERRUPT_STACK_HIGH? */
+	lwi r4, r0, _Per_CPU_Information + 4
+	rsubk r3, r4, r1
+	bgei r3, switch_to_interrupt_stack
+
+	bri on_interrupt_stack
+
+switch_to_interrupt_stack:
+	add r4, r0, r1
+	lwi r1, r0, _Per_CPU_Information + 4
+	addik r1, r1, -52
+	swi r4, r1, 0
+
+on_interrupt_stack:
+	/* Add 1 to ISR_NEST_LEVEL */
+	lwi r3, r0, _Per_CPU_Information + 8
+	addik r3, r3, 1
+	swi r3, r0, _Per_CPU_Information + 8
+
+	bralid r15, bsp_interrupt_dispatch
+	nop
+
+	/* Subtract 1 from ISR_NEST_LEVEL */
+	lwi r3, r0, _Per_CPU_Information + 8
+	addik r3, r3, -1
+	swi r3, r0, _Per_CPU_Information + 8
+
+	/* Is ISR_NEST_LEVEL > 0? */
+	bgti r3, after_stack_switch
+
+	/* Switch back to interrupted thread stack */
+	lwi r1, r1, 0
+
+after_stack_switch:
+	/* Subtract 1 from THREAD_DISPATCH_DISABLE_LEVEL */
+	lwi r3, r0, _Per_CPU_Information + 16
+	addik r3, r3, -1
+	swi r3, r0, _Per_CPU_Information + 16
+
+	/* Is THREAD_DISPATCH_DISABLE_LEVEL != 0? */
+	bnei r3, quick_exit
+
+	/* Is DISPATCH_NEEDED == 0? */
+	lwi r3, r0, _Per_CPU_Information + 20
+	beqi r3, quick_exit
+
+	/* Return to interrupted thread and make it do a dispatch */
+	addik r14, r0, thread_dispatch
+	rtid r14, 0
+	nop
+
+quick_exit:
+	/* Simple return from nested interrupt */
+	/* Restore registers */
+	lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+	lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+	lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+	lwi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+	lwi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+	lwi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+	lwi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+	lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+	lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+	lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+	lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+	lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+	lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+
+	/* Remove stack frame */
+	addik r1, r1, 52
+
+	rtid r14, 0
+	nop
+
+thread_dispatch:
+	/* Reserve stack */
+	addik r1, r1, -52
+	/* Save scratch registers */
+	swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+	swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+	swi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+	swi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+	swi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+	swi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+	swi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+	swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+	swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+	swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+	swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+	swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+	swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+
+	bralid r15, _Thread_Dispatch
+	nop
+
+	/* Restore scratch registers */
+	lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+	lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+	lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+	lwi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+	lwi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+	lwi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+	lwi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+	lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+	lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+	lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+	lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+	lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+	lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+	/* Free stack space */
+	addik r1, r1, 52
+
+	bri quick_exit
+
+do_exception:
+	/* exception no longer in progress */
+	mfs r3, rmsr
+	andni r3, r3, 0x200
+	mts rmsr, r3
+	addi r5, r0, 9
+	add r6, r0, r1
+
+	brai _Terminate

cpukit/score/cpu/microblaze/include/rtems/asm.h

@@ -1,29 +1,41 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief MicroBlaze assembler support
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
- *  COPYRIGHT:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
- *  This file is based on similar code found in newlib available
- *  from ftp.cygnus.com.  The file which was used had no copyright
- *  notice.  This file is freely distributable as long as the source
- *  of the file is noted.  This file is:
- *
- *  Copyright (c) 2015, Hesham Almatary
- *  COPYRIGHT (c) 1994-2006.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  $Id: asm.h,v 1.16 2006/01/16 15:12:12 joel Exp $
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef _RTEMS_ASM_H
@@ -36,6 +48,7 @@
 #ifndef ASM
 #define ASM
 #endif
+
 #include <rtems/score/cpuopts.h>
 
 #ifndef __USER_LABEL_PREFIX__

cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze atomic support
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
+#define _RTEMS_SCORE_ATOMIC_CPU_H
+
+#include <rtems/score/cpustdatomic.h>
+
+#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */

cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief CPU Port Implementation API
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_CPUIMPL_H
+#define _RTEMS_SCORE_CPUIMPL_H
+
+#include <rtems/score/cpu.h>
+
+/**
+ * @defgroup RTEMSScoreCPUMicroBlaze MicroBlaze
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze Architecture Support
+ *
+ * @{
+ */
+
+#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_INTERRUPT_FRAME_SIZE 52
+
+#define MICROBLAZE_INTERRUPT_FRAME_R3   0
+#define MICROBLAZE_INTERRUPT_FRAME_R4   4
+#define MICROBLAZE_INTERRUPT_FRAME_R5   8
+#define MICROBLAZE_INTERRUPT_FRAME_R6  12
+#define MICROBLAZE_INTERRUPT_FRAME_R7  16
+#define MICROBLAZE_INTERRUPT_FRAME_R8  20
+#define MICROBLAZE_INTERRUPT_FRAME_R9  24
+#define MICROBLAZE_INTERRUPT_FRAME_R10 28
+#define MICROBLAZE_INTERRUPT_FRAME_R11 32
+#define MICROBLAZE_INTERRUPT_FRAME_R12 36
+#define MICROBLAZE_INTERRUPT_FRAME_R14 40
+#define MICROBLAZE_INTERRUPT_FRAME_R15 44
+#define MICROBLAZE_INTERRUPT_FRAME_R18 48
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _CPU_Context_volatile_clobber( uintptr_t pattern );
+
+void _CPU_Context_validate( uintptr_t pattern );
+
+RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+{
+  __asm__ volatile ( ".word 0x0" );
+}
+
+RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+{
+  __asm__ volatile ( "nop" );
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+/** @} */
+
+#endif /* _RTEMS_SCORE_CPUIMPL_H */

cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h

@@ -1,7 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief MicroBlaze architecture support
+ */
+
 /*
- *  Copyright (c) 2015, Hesham Almatary
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -9,8 +18,8 @@
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -25,58 +34,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the NO CPU port.
- *
- *  $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $
- *
- */
-
-
-#ifndef _RTEMS_SCORE_NO_CPU_H
-#define _RTEMS_SCORE_NO_CPU_H
+#ifndef _RTEMS_SCORE_MICROBLAZE_H
+#define _RTEMS_SCORE_MICROBLAZE_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/*
- *  This file contains the information required to build
- *  RTEMS for a particular member of the NO CPU family.
- *  It does this by setting variables to indicate which
- *  implementation dependent features are present in a particular
- *  member of the family.
- *
- *  This is a good place to list all the known CPU models
- *  that this port supports and which RTEMS CPU model they correspond
- *  to.
- */
-
-#if defined(rtems_multilib)
-/*
- *  Figure out all CPU Model Feature Flags based upon compiler
- *  predefines.
- */
-
-#define CPU_MODEL_NAME  "rtems_multilib"
-#define NOCPU_HAS_FPU     1
-
-#else
-/* if defined(__MICROBLAZE__) */
-
 #define CPU_MODEL_NAME  "MicroBlaze"
-#define NOCPU_HAS_FPU     1
-
-/*
-#else
-
-#error "Unsupported CPU Model"
-*/
-
-#endif
+#define NOCPU_HAS_FPU   1
 
 /*
  *  Define the name of the CPU family.
@@ -88,4 +54,4 @@ extern "C" {
 }
 #endif
 
-#endif /* _RTEMS_SCORE_NO_CPU_H */
+#endif /* _RTEMS_SCORE_MICROBLAZE_H */

cpukit/score/cpu/microblaze/microblaze-context-switch.S

@@ -1,5 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze context switch implementation
+ */
+
 /*
- *  Copyright (c) 2015, Hesham Almatary
+ * Copyright (c) 2015, Hesham Almatary
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -7,8 +18,8 @@
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -59,6 +70,10 @@ SYM(_CPU_Context_switch):
     swi     r30, r5, 72
     swi     r31, r5, 76
 
+    mfs     r21, rmsr
+    swi     r21, r5, 80
+
+
 SYM(restore):
     lwi     r1,  r6, 0
     lwi     r13, r6, 4
@@ -79,6 +94,10 @@ SYM(restore):
     lwi     r28, r6, 64
     lwi     r29, r6, 68
     lwi     r30, r6, 72
+
+    lwi     r31, r6, 80
+    mts     rmsr, r31
+
     lwi     r31, r6, 76
 
     rtsd    r15, 8

cpukit/score/cpu/microblaze/microblaze-context-validate.S

@@ -0,0 +1,117 @@
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+#define FRAME_OFFSET_R19 0
+#define FRAME_OFFSET_R20 4
+#define FRAME_OFFSET_R21 8
+#define FRAME_OFFSET_R22 12
+#define FRAME_OFFSET_R23 16
+#define FRAME_OFFSET_R24 20
+#define FRAME_OFFSET_R25 24
+#define FRAME_OFFSET_R26 28
+#define FRAME_OFFSET_R27 32
+#define FRAME_OFFSET_R28 36
+#define FRAME_OFFSET_R29 40
+#define FRAME_OFFSET_R30 44
+#define FRAME_OFFSET_R31 48
+
+#define FRAME_SIZE (FRAME_OFFSET_R31 + 4)
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_validate)
+
+SYM(_CPU_Context_validate):
+
+	/* Save */
+	addik r1, r1, -FRAME_SIZE
+	swi r19, r1, FRAME_OFFSET_R19
+	swi r20, r1, FRAME_OFFSET_R20
+	swi r21, r1, FRAME_OFFSET_R21
+	swi r22, r1, FRAME_OFFSET_R22
+	swi r23, r1, FRAME_OFFSET_R23
+	swi r24, r1, FRAME_OFFSET_R24
+	swi r25, r1, FRAME_OFFSET_R25
+	swi r26, r1, FRAME_OFFSET_R26
+	swi r27, r1, FRAME_OFFSET_R27
+	swi r28, r1, FRAME_OFFSET_R28
+	swi r29, r1, FRAME_OFFSET_R29
+	swi r30, r1, FRAME_OFFSET_R30
+	swi r31, r1, FRAME_OFFSET_R31
+
+	/* Fill */
+
+	add r4, r0, r3
+
+	/* r7 contains the stack pointer */
+	add r7, r0, r1
+
+.macro fill_register reg
+	addi r4, r4, 1
+	add \reg, r0, r4
+.endm
+
+	fill_register r21
+	fill_register r22
+	fill_register r23
+	fill_register r24
+	fill_register r25
+	fill_register r26
+	fill_register r27
+	fill_register r28
+	fill_register r29
+	fill_register r30
+	fill_register r31
+
+	/* Check */
+check:
+
+.macro check_register reg
+	addi r4, r4, 1
+	cmp r6, \reg, r4
+	bnei r6, restore
+.endm
+
+	cmp r6, r7, r1
+	bnei r6, restore
+
+	add r4, r0, r3
+
+	check_register r21
+	check_register r22
+	check_register r23
+	check_register r24
+	check_register r25
+	check_register r26
+	check_register r27
+	check_register r28
+	check_register r29
+	check_register r30
+	check_register r31
+
+	brai check
+
+	/* Restore */
+restore:
+
+	lwi r19, r1, FRAME_OFFSET_R19
+	lwi r20, r1, FRAME_OFFSET_R20
+	lwi r21, r1, FRAME_OFFSET_R21
+	lwi r22, r1, FRAME_OFFSET_R22
+	lwi r23, r1, FRAME_OFFSET_R23
+	lwi r24, r1, FRAME_OFFSET_R24
+	lwi r25, r1, FRAME_OFFSET_R25
+	lwi r26, r1, FRAME_OFFSET_R26
+	lwi r27, r1, FRAME_OFFSET_R27
+	lwi r28, r1, FRAME_OFFSET_R28
+	lwi r29, r1, FRAME_OFFSET_R29
+	lwi r30, r1, FRAME_OFFSET_R30
+	lwi r31, r1, FRAME_OFFSET_R31
+
+	addik r1, r1, FRAME_SIZE
+
+	bra r15

cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S

@@ -0,0 +1,28 @@
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+.text
+.align 4
+
+PUBLIC(_CPU_Context_volatile_clobber)
+
+SYM(_CPU_Context_volatile_clobber):
+
+.macro clobber_register reg
+	addi r5, r5, -1
+	add \reg, r0, r5
+.endm
+
+	clobber_register r3
+	clobber_register r4
+	clobber_register r6
+	clobber_register r7
+	clobber_register r8
+	clobber_register r9
+	clobber_register r10
+
+	rtsd	r15, 8
+	nop

spec/build/bsps/microblaze/grp.yml

@@ -0,0 +1,15 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/microblaze/include/bsp/linker-symbols.h
+ldflags: []
+links: []
+type: build
+use-after: []
+use-before: []

spec/build/bsps/microblaze/microblaze_fpga/abi.yml

@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default:
+- -mlittle-endian
+- -mno-xl-soft-div
+- -mno-xl-soft-mul
+- -Wl,-EL
+default-by-variant: []
+description: |
+  ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build

spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml

@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: microblaze
+bsp: kcu105
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+enabled-by: true
+family: microblaze_fpga
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: tstkcu105_qemu
+- role: build-dependency
+  uid: ../../opto0
+source:
+- bsps/shared/start/bspreset-loop.c
+type: build

spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml

@@ -0,0 +1,24 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: microblaze
+bsp: kcu105_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+enabled-by: true
+family: microblaze_fpga
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: tstkcu105_qemu
+- role: build-dependency
+  uid: ../../opto0
+source:
+- bsps/microblaze/microblaze_fpga/start/bspreset.c
+type: build

spec/build/bsps/microblaze/microblaze_fpga/grp.yml

@@ -0,0 +1,36 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+enabled-by: true
+includes: []
+install: []
+ldflags: []
+links:
+- role: build-dependency
+  uid: ../grp
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: obj
+- role: build-dependency
+  uid: start
+- role: build-dependency
+  uid: optconsoleinterrupts
+- role: build-dependency
+  uid: optintcbaseaddress
+- role: build-dependency
+  uid: opttimerbaseaddress
+- role: build-dependency
+  uid: opttimerfrequency
+- role: build-dependency
+  uid: optuartlitebaseaddress
+- role: build-dependency
+  uid: ../../obj
+- role: build-dependency
+  uid: ../../objirq
+- role: build-dependency
+  uid: ../../bspopts
+type: build
+use-after: []
+use-before: []

spec/build/bsps/microblaze/microblaze_fpga/obj.yml

@@ -0,0 +1,47 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}
+  source:
+  - bsps/microblaze/microblaze_fpga/include/bsp.h
+  - bsps/microblaze/microblaze_fpga/include/tm27.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/microblaze/microblaze_fpga/include/bsp/irq.h
+  - bsps/microblaze/include/common/xil_types.h
+  - bsps/microblaze/include/dev/serial/uartlite.h
+  - bsps/microblaze/include/dev/serial/uartlite_l.h
+links: []
+source:
+- bsps/microblaze/microblaze_fpga/clock/clock.c
+- bsps/microblaze/microblaze_fpga/console/console-io.c
+- bsps/microblaze/microblaze_fpga/console/debug-io.c
+- bsps/microblaze/microblaze_fpga/irq/irq.c
+- bsps/microblaze/microblaze_fpga/start/_exception_handler.S
+- bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S
+- bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
+- bsps/microblaze/microblaze_fpga/start/bspreset.c
+- bsps/microblaze/microblaze_fpga/start/bspstart.c
+- bsps/microblaze/microblaze_fpga/start/crtinit.S
+- bsps/microblaze/shared/dev/serial/uartlite.c
+- bsps/microblaze/shared/dev/serial/uartlite_l.c
+- bsps/shared/cache/nocache.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/dev/cpucounter/cpucounterfrequency.c
+- bsps/shared/dev/cpucounter/cpucounterread.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/serial/console-termios-init.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/gettargethash-default.c
+- bsps/shared/start/sbrk.c
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml

@@ -0,0 +1,15 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: true
+default-by-variant: []
+description: |
+  use interrupt driven mode for console
+enabled-by: true
+links: []
+name: BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x41200000
+default-by-variant: []
+description: |
+  base address of the AXI Interrupt Controller
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_INTC_BASE
+type: build

spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x41C00000
+default-by-variant: []
+description: |
+  base address of the AXI Timer
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_TIMER_BASE
+type: build

spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 100000000
+default-by-variant: []
+description: |
+  frequency of the AXI Timer
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: 0x40600000
+default-by-variant: []
+description: |
+  base address of the AXI UART Lite
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_UART_BASE
+type: build

spec/build/bsps/microblaze/microblaze_fpga/start.yml

@@ -0,0 +1,14 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+asflags: []
+build-type: start-file
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+enabled-by: true
+includes: []
+install-path: ${BSP_LIBDIR}
+links: []
+source:
+- bsps/microblaze/shared/start/start.S
+target: start.o
+type: build

spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml

@@ -0,0 +1,14 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- set-test-state:
+    # expected to fail, don't compile these
+    minimum: exclude
+build-type: option
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+default: null
+default-by-variant: []
+description: ''
+enabled-by: true
+links: []
+type: build

spec/build/cpukit/cpumicroblaze.yml

@@ -0,0 +1,29 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+cppflags: []
+cxxflags: []
+enabled-by:
+- microblaze
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/rtems
+  source:
+  - cpukit/score/cpu/microblaze/include/rtems/asm.h
+- destination: ${BSP_INCLUDEDIR}/rtems/score
+  source:
+  - cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+  - cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h
+  - cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+  - cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h
+links: []
+source:
+- cpukit/score/cpu/microblaze/__tls_get_addr.c
+- cpukit/score/cpu/microblaze/microblaze-context-switch.S
+- cpukit/score/cpu/microblaze/microblaze-context-validate.S
+- cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S
+- cpukit/score/cpu/microblaze/cpu.c
+- cpukit/score/cpu/microblaze/cpu_asm.S
+type: build

spec/build/cpukit/librtemscpu.yml

@@ -471,6 +471,8 @@ links:
   uid: cpum68k
 - role: build-dependency
   uid: cpumips
+- role: build-dependency
+  uid: cpumicroblaze
 - role: build-dependency
   uid: cpumoxie
 - role: build-dependency