mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-21 15:39:19 +08:00
2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>
PR 1781/bsps * bf52x/include: Added additional MMR. * bf52x/interrupt: The BF52X processors have a different System interrupt controller than present in the 53X range of processors. The 52X have 8 interrupt assignment registers. The implementation uses tables to increase predictability. * serial/uart.?: Added DMA based and interrupt based transfer support. The uart code used a single ISR for TX and RX and tried to identify and multiplex inside the ISR. In the new code the type of interrupt is identified by the central ISR dispatcher bf52x/interrupt or interrupt/. This simplifies the UART ISR.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,17 @@
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2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>
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PR 1781/bsps
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* bf52x/include: Added additional MMR.
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* bf52x/interrupt: The BF52X processors have a different
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System interrupt controller than present in the 53X range of
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processors. The 52X have 8 interrupt assignment registers. The
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implementation uses tables to increase predictability.
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* serial/uart.?: Added DMA based and interrupt based transfer
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support. The uart code used a single ISR for TX and RX and tried
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to identify and multiplex inside the ISR. In the new code the
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type of interrupt is identified by the central ISR dispatcher
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bf52x/interrupt or interrupt/. This simplifies the UART ISR.
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2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
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* timer/timer.c:
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@@ -10,9 +10,31 @@ EXTRA_DIST =
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noinst_PROGRAMS =
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include_bspdir = $(includedir)/bsp
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include_libcpudir = $(includedir)/libcpu
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include_bsp_HEADERS =
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include_libcpu_HEADERS =
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############
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# Start of bf52x files
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if bf52x
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include_HEADERS = bf52x/include/bf52x.h
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## INTERRUPT
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include_bsp_HEADERS += bf52x/interrupt/interrupt.h
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noinst_PROGRAMS += bf52x/interrupt.rel
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bf52x_interrupt_rel_SOURCES = bf52x/interrupt/interrupt.c \
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bf52x/interrupt/interrupt.h
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bf52x_interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
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bf52x_interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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endif
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# endof bf52x
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############
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include_libcpu_HEADERS += include/bf533.h
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include_libcpu_HEADERS += include/bf537.h
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include_libcpu_HEADERS += include/cecRegs.h
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@@ -47,12 +69,17 @@ mmu_rel_SOURCES = mmu/mmu.c
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mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)
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mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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if bf52x
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else
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include_libcpu_HEADERS += interrupt/interrupt.h
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noinst_PROGRAMS += interrupt.rel
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interrupt_rel_SOURCES = interrupt/interrupt.c
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interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
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interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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endif
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noinst_PROGRAMS += clock.rel
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clock_rel_SOURCES = clock/clock.c
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clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
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@@ -0,0 +1,133 @@
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/**
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*@file bf52x.h
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*
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*@brief
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* - This file provides the register address for the 52X model. The file is
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* based on the 533 implementation with some addition to support 52X range of
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* processors.
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*
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* Target: TLL6527v1-0
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* Compiler:
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*
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* COPYRIGHT (c) 2010 by ECE Northeastern University.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license
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*
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* @author Rohan Kangralkar, ECE, Northeastern University
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* (kangralkar.r@husky.neu.edu)
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*
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* LastChange:
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* $Id$
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*
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*/
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#ifndef _BF52X_H_
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#define _BF52X_H_
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/* register (or register block) addresses */
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#define SIC_BASE_ADDRESS 0xffc00100
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#define WDOG_BASE_ADDRESS 0xffc00200
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#define RTC_BASE_ADDRESS 0xffc00300
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#define UART0_BASE_ADDRESS 0xffc00400
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#define UART1_BASE_ADDRESS 0xffc02000
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#define SPI_BASE_ADDRESS 0xffc00500
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#define TIMER_BASE_ADDRESS 0xffc00600
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#define TIMER_CHANNELS 3
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#define TIMER_PITCH 0x10
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#define TIMER0_BASE_ADDRESS 0xffc00600
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#define TIMER1_BASE_ADDRESS 0xffc00610
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#define TIMER2_BASE_ADDRESS 0xffc00620
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#define TIMER_ENABLE 0xffc00640
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#define TIMER_DISABLE 0xffc00644
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#define TIMER_STATUS 0xffc00648
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#define PORTFIO_BASE_ADDRESS 0xffc00700
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#define SPORT0_BASE_ADDRESS 0xffc00800
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#define SPORT1_BASE_ADDRESS 0xffc00900
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#define EBIU_BASE_ADDRESS 0xffc00a00
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#define DMA_TC_PER 0xffc00b0c
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#define DMA_TC_CNT 0xffc00b10
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#define DMA_BASE_ADDRESS 0xffc00c00
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#define DMA_CHANNELS 8
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#define DMA_PITCH 0x40
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#define DMA0_BASE_ADDRESS 0xffc00c00
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#define DMA1_BASE_ADDRESS 0xffc00c40
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#define DMA2_BASE_ADDRESS 0xffc00c80
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#define DMA3_BASE_ADDRESS 0xffc00cc0
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#define DMA4_BASE_ADDRESS 0xffc00d00
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#define DMA5_BASE_ADDRESS 0xffc00d40
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#define DMA6_BASE_ADDRESS 0xffc00d80
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#define DMA7_BASE_ADDRESS 0xffc00dc0
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#define DMA8_BASE_ADDRESS 0xffc00e00
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#define DMA9_BASE_ADDRESS 0xffc00e40
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#define DMA10_BASE_ADDRESS 0xffc00e80
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#define DMA11_BASE_ADDRESS 0xffc00ec0
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#define MDMA_BASE_ADDRESS 0xffc00e00
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#define MDMA_CHANNELS 2
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#define MDMA_D_S 0x40
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#define MDMA_PITCH 0x80
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#define MDMA0D_BASE_ADDRESS 0xffc00e00
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#define MDMA0S_BASE_ADDRESS 0xffc00e40
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#define MDMA1D_BASE_ADDRESS 0xffc00e80
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#define MDMA1S_BASE_ADDRESS 0xffc00ec0
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#define PPI_BASE_ADDRESS 0xffc01000
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/* register fields */
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#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800
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#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11
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#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700
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#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8
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#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0
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#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4
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#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f
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#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0
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#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800
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#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11
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#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700
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#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8
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#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0
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#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4
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#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f
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#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0
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#define TIMER_ENABLE_TIMEN2 0x0004
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#define TIMER_ENABLE_TIMEN1 0x0002
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#define TIMER_ENABLE_TIMEN0 0x0001
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#define TIMER_DISABLE_TIMDIS2 0x0004
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#define TIMER_DISABLE_TIMDIS1 0x0002
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#define TIMER_DISABLE_TIMDIS0 0x0001
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#define TIMER_STATUS_TRUN2 0x00004000
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#define TIMER_STATUS_TRUN1 0x00002000
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#define TIMER_STATUS_TRUN0 0x00001000
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#define TIMER_STATUS_TOVF_ERR2 0x00000040
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#define TIMER_STATUS_TOVF_ERR1 0x00000020
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#define TIMER_STATUS_TOVF_ERR0 0x00000010
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#define TIMER_STATUS_TIMIL2 0x00000004
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#define TIMER_STATUS_TIMIL1 0x00000002
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#define TIMER_STATUS_TIMIL0 0x00000001
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/* Core Event Controller vectors */
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#define CEC_EMULATION_VECTOR 0
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#define CEC_RESET_VECTOR 1
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#define CEC_NMI_VECTOR 2
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#define CEC_EXCEPTIONS_VECTOR 3
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#define CEC_HARDWARE_ERROR_VECTOR 5
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#define CEC_CORE_TIMER_VECTOR 6
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#define CEC_INTERRUPT_BASE_VECTOR 7
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#define CEC_INTERRUPT_COUNT 9
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/* System Interrupt Controller vectors */
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#define SIC_IAR_COUNT 8
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#endif /* _BF52X_H_ */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
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/**
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*@file interrupt.h
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*
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*@brief
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* - This file implements interrupt dispatcher. The init code is taken from
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* the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
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* registers some portion is written twice.
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*
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* Target: TLL6527v1-0
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* Compiler:
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*
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* COPYRIGHT (c) 2010 by ECE Northeastern University.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license
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*
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* @author Rohan Kangralkar, ECE, Northeastern University
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* (kangralkar.r@husky.neu.edu)
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*
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* LastChange:
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* $Id$
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*
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*/
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#ifndef _BFIN_INTERRUPT_H_
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#define _BFIN_INTERRUPT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** The type of interrupts handled by the SIC
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*/
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typedef enum {
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IRQ_PLL_WAKEUP_INTERRUPT, /* 0 */
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IRQ_DMA_ERROR_0, /* 1 */
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IRQ_DMAR0_BLOCK_INTERRUPT, /* 2 */
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IRQ_DMAR1_BLOCK_INTERRUPT, /* 3 */
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IRQ_DMAR0_OVERFLOW_ERROR, /* 4 */
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IRQ_DMAR1_OVERFLOW_ERROR, /* 5 */
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IRQ_PPI_STATUS, /* 6 */
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IRQ_MAC_STATUS, /* 7 */
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IRQ_SPORT0_STATUS, /* 8 */
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IRQ_SPORT1_STATUS, /* 9 */
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IRQ_RESERVED_10, /* 10 */
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IRQ_RESERVED_11, /* 11 */
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IRQ_UART0_STATUS, /* 12 */
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IRQ_UART1_STATUS, /* 13 */
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IRQ_REAL_TIME_CLOCK, /* 14 */
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IRQ_DMA0_PPI_NFC, /* 15 */
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IRQ_DMA3_SPORT0_RX, /* 16 */
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IRQ_DMA4_SPORT0_TX, /* 17 */
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IRQ_DMA5_SPORT1_RX, /* 18 */
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IRQ_DMA6_SPORT1_TX, /* 19 */
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IRQ_TWI_INTERRUPT, /* 20 */
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IRQ_DMA7_SPI, /* 21 */
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IRQ_DMA8_UART0_RX, /* 22 */
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IRQ_DMA9_UART0_TX, /* 23 */
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IRQ_DMA10_UART1_RX, /* 24 */
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IRQ_DMA11_UART1_TX, /* 25 */
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IRQ_OTP, /* 26 */
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IRQ_GP_COUNTER, /* 27 */
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IRQ_DMA1_MAC_RX_HOSTDP, /* 28 */
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IRQ_PORT_H_INTERRUPT_A, /* 29 */
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IRQ_DMA2_MAC_TX_NFC, /* 30 */
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IRQ_PORT_H_INTERRUPT_B, /* 31 */
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SIC_ISR0_MAX, /* 32 ***/
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IRQ_TIMER0 = SIC_ISR0_MAX, /* 32 */
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IRQ_TIMER1, /* 33 */
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IRQ_TIMER2, /* 34 */
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IRQ_TIMER3, /* 35 */
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IRQ_TIMER4, /* 36 */
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IRQ_TIMER5, /* 37 */
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IRQ_TIMER6, /* 38 */
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IRQ_TIMER7, /* 39 */
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IRQ_PORT_G_INTERRUPT_A, /* 40 */
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IRQ_PORT_G_INTERRUPT_B, /* 41 */
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IRQ_MDMA0_STREAM_0_INTERRUPT, /* 42 */
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IRQ_MDMA1_STREAM_0_INTERRUPT, /* 43 */
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IRQ_SOFTWARE_WATCHDOG_INTERRUPT, /* 44 */
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IRQ_PORT_F_INTERRUPT_A, /* 45 */
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IRQ_PORT_F_INTERRUPT_B, /* 46 */
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IRQ_SPI_STATUS, /* 47 */
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IRQ_NFC_STATUS, /* 48 */
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IRQ_HOSTDP_STATUS, /* 49 */
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IRQ_HOREAD_DONE_INTERRUPT, /* 50 */
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IRQ_RESERVED_19, /* 51 */
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IRQ_USB_INT0_INTERRUPT, /* 52 */
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IRQ_USB_INT1_INTERRUPT, /* 53 */
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IRQ_USB_INT2_INTERRUPT, /* 54 */
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IRQ_USB_DMAINT, /* 55 */
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IRQ_MAX, /* 56 */
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} e_isr_t;
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/* source is the source to the SIC (the bit number in SIC_ISR). isr is
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the function that will be called when the interrupt is active. */
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typedef struct bfin_isr_s {
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#if INTERRUPT_USE_TABLE
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e_isr_t source;
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void (*pFunc)(void *arg);
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void *pArg;
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int priority; /** not used */
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#else
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int source;
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void (*isr)(void *arg);
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void *_arg;
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/* the following are for internal use only */
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uint32_t mask0;
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uint32_t mask1;
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uint32_t vector;
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struct bfin_isr_s *next;
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#endif
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} bfin_isr_t;
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/**
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* This routine registers a new ISR. It will write a new entry to the IVT table
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* @param isr contains a callback function and source
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* @return rtems status code
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*/
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rtems_status_code bfin_interrupt_register(bfin_isr_t *isr);
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|
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/**
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* This function unregisters a registered interrupt handler.
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* @param isr
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*/
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rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr);
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|
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/**
|
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* blackfin interrupt initialization routine. It initializes the bfin ISR
|
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* dispatcher. It will also create SIC CEC map which will be used for
|
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* identifying the ISR.
|
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*/
|
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void bfin_interrupt_init(void);
|
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|
||||
|
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#ifdef __cplusplus
|
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}
|
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#endif
|
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|
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#endif /* _BFIN_INTERRUPT_H_ */
|
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|
||||
@@ -24,6 +24,10 @@ RTEMS_PROG_CCAS
|
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RTEMS_CHECK_NETWORKING
|
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AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
|
||||
|
||||
# AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "bf52x")
|
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AM_CONDITIONAL(bf52x, test "$RTEMS_CPU_MODEL" = "bf52x")
|
||||
|
||||
|
||||
RTEMS_AMPOLISH3
|
||||
|
||||
# Explicitly list all Makefiles here
|
||||
|
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@@ -16,8 +16,14 @@
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/* register addresses */
|
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|
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#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c)
|
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#define SIC_IMASK_PITCH (0x40)
|
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|
||||
#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020)
|
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#define SIC_ISR_PITCH (0x40)
|
||||
|
||||
#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010)
|
||||
#define SIC_IAR_PITCH 0x04
|
||||
|
||||
#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010)
|
||||
#if SIC_IAR_COUNT > 1
|
||||
#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014)
|
||||
@@ -28,7 +34,7 @@
|
||||
#if SIC_IAR_COUNT > 3
|
||||
#define SIC_IAR3 (SIC_BASE_ADDRESS + 0x001c)
|
||||
#endif
|
||||
#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020)
|
||||
|
||||
#define SIC_IWR (SIC_BASE_ADDRESS + 0x0024)
|
||||
|
||||
|
||||
|
||||
@@ -13,11 +13,30 @@ all-am: $(PREINSTALL_FILES)
|
||||
PREINSTALL_FILES =
|
||||
CLEANFILES = $(PREINSTALL_FILES)
|
||||
|
||||
$(PROJECT_INCLUDE)/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)
|
||||
@: > $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
|
||||
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
|
||||
@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
|
||||
if bf52x
|
||||
$(PROJECT_INCLUDE)/bf52x.h: bf52x/include/bf52x.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bf52x.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bf52x.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/interrupt.h: bf52x/interrupt/interrupt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/interrupt.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/interrupt.h
|
||||
endif
|
||||
$(PROJECT_INCLUDE)/libcpu/bf533.h: include/bf533.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bf533.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bf533.h
|
||||
@@ -102,10 +121,12 @@ $(PROJECT_INCLUDE)/libcpu/mmu.h: mmu/mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
|
||||
|
||||
if bf52x
|
||||
else
|
||||
$(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
|
||||
|
||||
endif
|
||||
$(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
|
||||
|
||||
+387
-159
File diff suppressed because it is too large
Load Diff
@@ -8,52 +8,133 @@
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* Modified:
|
||||
* $Author$ Added interrupt support and DMA support
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _uart_h_
|
||||
#define _uart_h_
|
||||
|
||||
#ifndef _UART_H_
|
||||
#define _UART_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/** bfin_uart_channel object
|
||||
*/
|
||||
typedef struct {
|
||||
const char *name;
|
||||
void *base_address;
|
||||
bool use_interrupts;
|
||||
int force_baud;
|
||||
/* the following are for internal use */
|
||||
void *termios;
|
||||
uint8_t volatile flags;
|
||||
const char *name; /** Holds name of the device */
|
||||
uint32_t uart_baseAddress; /** UART base address */
|
||||
uint32_t uart_rxDmaBaseAddress; /** RX DMA base address */
|
||||
uint32_t uart_txDmaBaseAddress; /** TX DMA base address */
|
||||
bool uart_useInterrupts; /** are interrupts used */
|
||||
bool uart_useDma; /** is dma used */
|
||||
int uart_baud; /** baud rate, 0 for default */
|
||||
|
||||
void *termios; /** termios associated */
|
||||
uint8_t volatile flags; /** flags for internal use */
|
||||
uint16_t length; /** length for internal use */
|
||||
} bfin_uart_channel_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t freq;
|
||||
int num_channels;
|
||||
bfin_uart_channel_t *channels;
|
||||
} bfin_uart_config_t;
|
||||
|
||||
/**
|
||||
* @param base_address defines the UART base address
|
||||
* @param source defines the source that caused the interrupt. This argument
|
||||
* will help us in identifying if Rx or TX caused the interrupt.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t base_address;
|
||||
int source;
|
||||
} bfin_uart_arg_t;
|
||||
|
||||
char bfin_uart_poll_read(int minor);
|
||||
|
||||
|
||||
char bfin_uart_poll_read(rtems_device_minor_number minor);
|
||||
|
||||
void bfin_uart_poll_write(int minor, char c);
|
||||
|
||||
|
||||
/**
|
||||
* Uart initialization function.
|
||||
* @param major major number of the device
|
||||
* @param config configuration parameters
|
||||
* @return rtems status code
|
||||
*/
|
||||
rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
|
||||
bfin_uart_config_t *config);
|
||||
bfin_uart_config_t *config);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* Opens the device in different modes. The supported modes are
|
||||
* 1. Polling
|
||||
* 2. Interrupt
|
||||
* 3. DMA
|
||||
* At exit the uart_Exit function will be called to flush the device.
|
||||
*
|
||||
* @param major Major number of the device
|
||||
* @param minor Minor number of the device
|
||||
* @param arg
|
||||
* @return
|
||||
*/
|
||||
rtems_device_driver bfin_uart_open(rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *arg);
|
||||
rtems_device_minor_number minor, void *arg);
|
||||
|
||||
void bfin_uart_isr(int source);
|
||||
|
||||
|
||||
/**
|
||||
* This function implements TX dma ISR. It clears the IRQ and dequeues a char
|
||||
* The channel argument will have the base address. Since there are two uart
|
||||
* and both the uarts can use the same tx dma isr.
|
||||
*
|
||||
* TODO: 1. Error checking 2. sending correct length ie after looking at the
|
||||
* number of elements the uart transmitted.
|
||||
*
|
||||
* @param _arg argument passed to the interrupt handler. It contains the
|
||||
* channel argument.
|
||||
*/
|
||||
void bfinUart_txDmaIsr(void *_arg);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* RX DMA ISR.
|
||||
* The polling route is used for receiving the characters. This is a place
|
||||
* holder for future implementation.
|
||||
* @param _arg
|
||||
*/
|
||||
void bfinUart_rxDmaIsr(void *_arg);
|
||||
|
||||
|
||||
/**
|
||||
* This function implements TX ISR. The function gets called when the TX FIFO is
|
||||
* empty. It clears the interrupt and dequeues the character. It only tx one
|
||||
* character at a time.
|
||||
*
|
||||
* TODO: error handling.
|
||||
* @param _arg gets the channel information.
|
||||
*/
|
||||
void bfinUart_txIsr(void *_arg);
|
||||
|
||||
|
||||
/**
|
||||
* This function implements RX ISR
|
||||
*/
|
||||
void bfinUart_rxIsr(void *_arg);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _uart_h_ */
|
||||
#endif /* _UART_H_ */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user