mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-08-21 19:47:14 +08:00
Forgot to remove these when code moved.
This commit is contained in:
Joel Sherrill
@@ -1,2 +0,0 @@
|
||||
Makefile
|
||||
Makefile.in
|
||||
@@ -1,55 +0,0 @@
|
||||
##
|
||||
## $Id$
|
||||
##
|
||||
|
||||
AUTOMAKE_OPTIONS = foreign 1.4
|
||||
ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
|
||||
|
||||
C_FILES = cpu.c
|
||||
C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o)
|
||||
|
||||
ROOT_H_FILES =
|
||||
RTEMS_SCORE_H_FILES = cpu.h c_isr.inl
|
||||
noinst_HEADERS = $(ROOT_H_FILES) $(RTEMS_SCORE_H_FILES)
|
||||
|
||||
S_FILES = cpu_asm.S
|
||||
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
|
||||
|
||||
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
|
||||
include $(top_srcdir)/../../../../../automake/lib.am
|
||||
|
||||
#
|
||||
# (OPTIONAL) Add local stuff here using +=
|
||||
#
|
||||
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/rtems/score \
|
||||
$(ROOT_H_FILES:%=$(PROJECT_INCLUDE)/%) \
|
||||
$(RTEMS_SCORE_H_FILES:%=$(PROJECT_INCLUDE)/rtems/score/%)
|
||||
|
||||
$(PROJECT_INCLUDE):
|
||||
$(mkinstalldirs) $@
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score:
|
||||
$(mkinstalldirs) $@
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/%: %
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
$(PROJECT_INCLUDE)/%: %
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
REL = ../$(ARCH)/rtems-cpu.rel
|
||||
|
||||
$(REL): $(C_O_FILES) $(S_O_FILES)
|
||||
test -d ../$(ARCH) || mkdir ../$(ARCH)
|
||||
$(make-rel)
|
||||
|
||||
all-local: $(ARCH) $(PREINSTALL_FILES) $(REL)
|
||||
## all-local: $(ARCH)/rtems.o
|
||||
all-local: $(TMPINSTALL_FILES)
|
||||
|
||||
CLEANDIRS = ../o-optimize ../o-debug ../o-profile
|
||||
|
||||
EXTRA_DIST = $(C_FILES) $(S_FILES)
|
||||
|
||||
include $(top_srcdir)/../../../../../automake/local.am
|
||||
@@ -1,9 +0,0 @@
|
||||
RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
|
||||
{
|
||||
register unsigned int isr_nesting_level;
|
||||
/*
|
||||
* Move from special purpose register 0 (mfspr SPRG0, r3)
|
||||
*/
|
||||
asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level));
|
||||
return isr_nesting_level;
|
||||
}
|
||||
@@ -1,116 +0,0 @@
|
||||
/*
|
||||
* PowerPC CPU Dependent Source
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/cpu.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
*
|
||||
* The license and distribution terms for this file may be found in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/context.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
|
||||
/* _CPU_Initialize
|
||||
*
|
||||
* This routine performs processor dependent initialization.
|
||||
*
|
||||
* INPUT PARAMETERS:
|
||||
* cpu_table - CPU table to initialize
|
||||
* thread_dispatch - address of disptaching routine
|
||||
*/
|
||||
|
||||
void _CPU_Initialize(
|
||||
rtems_cpu_table *cpu_table,
|
||||
void (*thread_dispatch) /* ignored on this CPU */
|
||||
)
|
||||
{
|
||||
_CPU_Table = *cpu_table;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Context_Initialize
|
||||
*/
|
||||
|
||||
void _CPU_Context_Initialize(
|
||||
Context_Control *the_context,
|
||||
unsigned32 *stack_base,
|
||||
unsigned32 size,
|
||||
unsigned32 new_level,
|
||||
void *entry_point,
|
||||
boolean is_fp
|
||||
)
|
||||
{
|
||||
unsigned32 msr_value;
|
||||
unsigned32 sp;
|
||||
|
||||
sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
|
||||
*((unsigned32 *)sp) = 0;
|
||||
the_context->gpr1 = sp;
|
||||
|
||||
_CPU_MSR_GET( msr_value );
|
||||
|
||||
if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
|
||||
msr_value |= MSR_EE;
|
||||
}
|
||||
else {
|
||||
msr_value &= ~MSR_EE;
|
||||
}
|
||||
|
||||
the_context->msr = msr_value;
|
||||
|
||||
/*
|
||||
* The FP bit of the MSR should only be enabled if this is a floating
|
||||
* point task. Unfortunately, the vfprintf_r routine in newlib
|
||||
* ends up pushing a floating point register regardless of whether or
|
||||
* not a floating point number is being printed. Serious restructuring
|
||||
* of vfprintf.c will be required to avoid this behavior. At this
|
||||
* time (7 July 1997), this restructuring is not being done.
|
||||
*/
|
||||
|
||||
/*if ( is_fp ) */
|
||||
the_context->msr |= PPC_MSR_FP;
|
||||
|
||||
the_context->pc = (unsigned32)entry_point;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Install_interrupt_stack
|
||||
*/
|
||||
|
||||
void _CPU_Install_interrupt_stack( void )
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,396 +0,0 @@
|
||||
|
||||
/* cpu_asm.s 1.1 - 95/12/04
|
||||
*
|
||||
* This file contains the assembly code for the PowerPC implementation
|
||||
* of RTEMS.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
|
||||
/*
|
||||
* Offsets for various Contexts
|
||||
*/
|
||||
.set GP_1, 0
|
||||
.set GP_2, (GP_1 + 4)
|
||||
.set GP_13, (GP_2 + 4)
|
||||
.set GP_14, (GP_13 + 4)
|
||||
|
||||
.set GP_15, (GP_14 + 4)
|
||||
.set GP_16, (GP_15 + 4)
|
||||
.set GP_17, (GP_16 + 4)
|
||||
.set GP_18, (GP_17 + 4)
|
||||
|
||||
.set GP_19, (GP_18 + 4)
|
||||
.set GP_20, (GP_19 + 4)
|
||||
.set GP_21, (GP_20 + 4)
|
||||
.set GP_22, (GP_21 + 4)
|
||||
|
||||
.set GP_23, (GP_22 + 4)
|
||||
.set GP_24, (GP_23 + 4)
|
||||
.set GP_25, (GP_24 + 4)
|
||||
.set GP_26, (GP_25 + 4)
|
||||
|
||||
.set GP_27, (GP_26 + 4)
|
||||
.set GP_28, (GP_27 + 4)
|
||||
.set GP_29, (GP_28 + 4)
|
||||
.set GP_30, (GP_29 + 4)
|
||||
|
||||
.set GP_31, (GP_30 + 4)
|
||||
.set GP_CR, (GP_31 + 4)
|
||||
.set GP_PC, (GP_CR + 4)
|
||||
.set GP_MSR, (GP_PC + 4)
|
||||
|
||||
.set FP_0, 0
|
||||
.set FP_1, (FP_0 + 4)
|
||||
.set FP_2, (FP_1 + 4)
|
||||
.set FP_3, (FP_2 + 4)
|
||||
.set FP_4, (FP_3 + 4)
|
||||
.set FP_5, (FP_4 + 4)
|
||||
.set FP_6, (FP_5 + 4)
|
||||
.set FP_7, (FP_6 + 4)
|
||||
.set FP_8, (FP_7 + 4)
|
||||
.set FP_9, (FP_8 + 4)
|
||||
.set FP_10, (FP_9 + 4)
|
||||
.set FP_11, (FP_10 + 4)
|
||||
.set FP_12, (FP_11 + 4)
|
||||
.set FP_13, (FP_12 + 4)
|
||||
.set FP_14, (FP_13 + 4)
|
||||
.set FP_15, (FP_14 + 4)
|
||||
.set FP_16, (FP_15 + 4)
|
||||
.set FP_17, (FP_16 + 4)
|
||||
.set FP_18, (FP_17 + 4)
|
||||
.set FP_19, (FP_18 + 4)
|
||||
.set FP_20, (FP_19 + 4)
|
||||
.set FP_21, (FP_20 + 4)
|
||||
.set FP_22, (FP_21 + 4)
|
||||
.set FP_23, (FP_22 + 4)
|
||||
.set FP_24, (FP_23 + 4)
|
||||
.set FP_25, (FP_24 + 4)
|
||||
.set FP_26, (FP_25 + 4)
|
||||
.set FP_27, (FP_26 + 4)
|
||||
.set FP_28, (FP_27 + 4)
|
||||
.set FP_29, (FP_28 + 4)
|
||||
.set FP_30, (FP_29 + 4)
|
||||
.set FP_31, (FP_30 + 4)
|
||||
.set FP_FPSCR, (FP_31 + 4)
|
||||
|
||||
.set IP_LINK, 0
|
||||
.set IP_0, (IP_LINK + 8)
|
||||
.set IP_2, (IP_0 + 4)
|
||||
|
||||
.set IP_3, (IP_2 + 4)
|
||||
.set IP_4, (IP_3 + 4)
|
||||
.set IP_5, (IP_4 + 4)
|
||||
.set IP_6, (IP_5 + 4)
|
||||
|
||||
.set IP_7, (IP_6 + 4)
|
||||
.set IP_8, (IP_7 + 4)
|
||||
.set IP_9, (IP_8 + 4)
|
||||
.set IP_10, (IP_9 + 4)
|
||||
|
||||
.set IP_11, (IP_10 + 4)
|
||||
.set IP_12, (IP_11 + 4)
|
||||
.set IP_13, (IP_12 + 4)
|
||||
.set IP_28, (IP_13 + 4)
|
||||
|
||||
.set IP_29, (IP_28 + 4)
|
||||
.set IP_30, (IP_29 + 4)
|
||||
.set IP_31, (IP_30 + 4)
|
||||
.set IP_CR, (IP_31 + 4)
|
||||
|
||||
.set IP_CTR, (IP_CR + 4)
|
||||
.set IP_XER, (IP_CTR + 4)
|
||||
.set IP_LR, (IP_XER + 4)
|
||||
.set IP_PC, (IP_LR + 4)
|
||||
|
||||
.set IP_MSR, (IP_PC + 4)
|
||||
.set IP_END, (IP_MSR + 16)
|
||||
|
||||
BEGIN_CODE
|
||||
/*
|
||||
* _CPU_Context_save_fp_context
|
||||
*
|
||||
* This routine is responsible for saving the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*/
|
||||
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_save_fp)
|
||||
PROC (_CPU_Context_save_fp):
|
||||
#if (PPC_HAS_FPU == 1)
|
||||
lwz r3, 0(r3)
|
||||
stfs f0, FP_0(r3)
|
||||
stfs f1, FP_1(r3)
|
||||
stfs f2, FP_2(r3)
|
||||
stfs f3, FP_3(r3)
|
||||
stfs f4, FP_4(r3)
|
||||
stfs f5, FP_5(r3)
|
||||
stfs f6, FP_6(r3)
|
||||
stfs f7, FP_7(r3)
|
||||
stfs f8, FP_8(r3)
|
||||
stfs f9, FP_9(r3)
|
||||
stfs f10, FP_10(r3)
|
||||
stfs f11, FP_11(r3)
|
||||
stfs f12, FP_12(r3)
|
||||
stfs f13, FP_13(r3)
|
||||
stfs f14, FP_14(r3)
|
||||
stfs f15, FP_15(r3)
|
||||
stfs f16, FP_16(r3)
|
||||
stfs f17, FP_17(r3)
|
||||
stfs f18, FP_18(r3)
|
||||
stfs f19, FP_19(r3)
|
||||
stfs f20, FP_20(r3)
|
||||
stfs f21, FP_21(r3)
|
||||
stfs f22, FP_22(r3)
|
||||
stfs f23, FP_23(r3)
|
||||
stfs f24, FP_24(r3)
|
||||
stfs f25, FP_25(r3)
|
||||
stfs f26, FP_26(r3)
|
||||
stfs f27, FP_27(r3)
|
||||
stfs f28, FP_28(r3)
|
||||
stfs f29, FP_29(r3)
|
||||
stfs f30, FP_30(r3)
|
||||
stfs f31, FP_31(r3)
|
||||
mffs f2
|
||||
stfs f2, FP_FPSCR(r3)
|
||||
#endif
|
||||
blr
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore_fp_context
|
||||
*
|
||||
* This routine is responsible for restoring the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* Sometimes a macro implementation of this is in cpu.h which dereferences
|
||||
* the ** and a similarly named routine in this file is passed something
|
||||
* like a (Context_Control_fp *). The general rule on making this decision
|
||||
* is to avoid writing assembly language.
|
||||
*/
|
||||
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_restore_fp)
|
||||
PROC (_CPU_Context_restore_fp):
|
||||
#if (PPC_HAS_FPU == 1)
|
||||
lwz r3, 0(r3)
|
||||
lfs f2, FP_FPSCR(r3)
|
||||
mtfsf 255, f2
|
||||
lfs f0, FP_0(r3)
|
||||
lfs f1, FP_1(r3)
|
||||
lfs f2, FP_2(r3)
|
||||
lfs f3, FP_3(r3)
|
||||
lfs f4, FP_4(r3)
|
||||
lfs f5, FP_5(r3)
|
||||
lfs f6, FP_6(r3)
|
||||
lfs f7, FP_7(r3)
|
||||
lfs f8, FP_8(r3)
|
||||
lfs f9, FP_9(r3)
|
||||
lfs f10, FP_10(r3)
|
||||
lfs f11, FP_11(r3)
|
||||
lfs f12, FP_12(r3)
|
||||
lfs f13, FP_13(r3)
|
||||
lfs f14, FP_14(r3)
|
||||
lfs f15, FP_15(r3)
|
||||
lfs f16, FP_16(r3)
|
||||
lfs f17, FP_17(r3)
|
||||
lfs f18, FP_18(r3)
|
||||
lfs f19, FP_19(r3)
|
||||
lfs f20, FP_20(r3)
|
||||
lfs f21, FP_21(r3)
|
||||
lfs f22, FP_22(r3)
|
||||
lfs f23, FP_23(r3)
|
||||
lfs f24, FP_24(r3)
|
||||
lfs f25, FP_25(r3)
|
||||
lfs f26, FP_26(r3)
|
||||
lfs f27, FP_27(r3)
|
||||
lfs f28, FP_28(r3)
|
||||
lfs f29, FP_29(r3)
|
||||
lfs f30, FP_30(r3)
|
||||
lfs f31, FP_31(r3)
|
||||
#endif
|
||||
blr
|
||||
|
||||
|
||||
/* _CPU_Context_switch
|
||||
*
|
||||
* This routine performs a normal non-FP context switch.
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_switch)
|
||||
PROC (_CPU_Context_switch):
|
||||
sync
|
||||
isync
|
||||
/* This assumes that all the registers are in the given order */
|
||||
li r5, 32
|
||||
addi r3,r3,-4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r1, GP_1+4(r3)
|
||||
stw r2, GP_2+4(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r3, r3, GP_18+4
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stmw r13, GP_13-GP_18(r3)
|
||||
#else
|
||||
stw r13, GP_13+4(r3)
|
||||
stw r14, GP_14+4(r3)
|
||||
stw r15, GP_15+4(r3)
|
||||
stw r16, GP_16+4(r3)
|
||||
stw r17, GP_17+4(r3)
|
||||
stwu r18, GP_18+4(r3)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbz r5, r3
|
||||
#endif
|
||||
stw r19, GP_19-GP_18(r3)
|
||||
stw r20, GP_20-GP_18(r3)
|
||||
stw r21, GP_21-GP_18(r3)
|
||||
stw r22, GP_22-GP_18(r3)
|
||||
stw r23, GP_23-GP_18(r3)
|
||||
stw r24, GP_24-GP_18(r3)
|
||||
stw r25, GP_25-GP_18(r3)
|
||||
stw r26, GP_26-GP_18(r3)
|
||||
stw r27, GP_27-GP_18(r3)
|
||||
stw r28, GP_28-GP_18(r3)
|
||||
stw r29, GP_29-GP_18(r3)
|
||||
stw r30, GP_30-GP_18(r3)
|
||||
stw r31, GP_31-GP_18(r3)
|
||||
#endif
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r0, r4
|
||||
#endif
|
||||
mfcr r6
|
||||
stw r6, GP_CR-GP_18(r3)
|
||||
mflr r7
|
||||
stw r7, GP_PC-GP_18(r3)
|
||||
mfmsr r8
|
||||
stw r8, GP_MSR-GP_18(r3)
|
||||
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r1, GP_1(r4)
|
||||
lwz r2, GP_2(r4)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
addi r4, r4, GP_19
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lmw r13, GP_13-GP_19(r4)
|
||||
#else
|
||||
lwz r13, GP_13(r4)
|
||||
lwz r14, GP_14(r4)
|
||||
lwz r15, GP_15(r4)
|
||||
lwz r16, GP_16(r4)
|
||||
lwz r17, GP_17(r4)
|
||||
lwz r18, GP_18(r4)
|
||||
lwzu r19, GP_19(r4)
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r5, r4
|
||||
#endif
|
||||
lwz r20, GP_20-GP_19(r4)
|
||||
lwz r21, GP_21-GP_19(r4)
|
||||
lwz r22, GP_22-GP_19(r4)
|
||||
lwz r23, GP_23-GP_19(r4)
|
||||
lwz r24, GP_24-GP_19(r4)
|
||||
lwz r25, GP_25-GP_19(r4)
|
||||
lwz r26, GP_26-GP_19(r4)
|
||||
lwz r27, GP_27-GP_19(r4)
|
||||
lwz r28, GP_28-GP_19(r4)
|
||||
lwz r29, GP_29-GP_19(r4)
|
||||
lwz r30, GP_30-GP_19(r4)
|
||||
lwz r31, GP_31-GP_19(r4)
|
||||
#endif
|
||||
lwz r6, GP_CR-GP_19(r4)
|
||||
lwz r7, GP_PC-GP_19(r4)
|
||||
lwz r8, GP_MSR-GP_19(r4)
|
||||
mtcrf 255, r6
|
||||
mtlr r7
|
||||
mtmsr r8
|
||||
|
||||
blr
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore
|
||||
*
|
||||
* This routine is generallu used only to restart self in an
|
||||
* efficient manner. It may simply be a label in _CPU_Context_switch.
|
||||
*
|
||||
* NOTE: May be unnecessary to reload some registers.
|
||||
*/
|
||||
/*
|
||||
* ACB: Don't worry about cache optimisation here - this is not THAT critical.
|
||||
*/
|
||||
ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
|
||||
PUBLIC_PROC (_CPU_Context_restore)
|
||||
PROC (_CPU_Context_restore):
|
||||
lwz r5, GP_CR(r3)
|
||||
lwz r6, GP_PC(r3)
|
||||
lwz r7, GP_MSR(r3)
|
||||
mtcrf 255, r5
|
||||
mtlr r6
|
||||
mtmsr r7
|
||||
lwz r1, GP_1(r3)
|
||||
lwz r2, GP_2(r3)
|
||||
#if (PPC_USE_MULTIPLE == 1)
|
||||
lmw r13, GP_13(r3)
|
||||
#else
|
||||
lwz r13, GP_13(r3)
|
||||
lwz r14, GP_14(r3)
|
||||
lwz r15, GP_15(r3)
|
||||
lwz r16, GP_16(r3)
|
||||
lwz r17, GP_17(r3)
|
||||
lwz r18, GP_18(r3)
|
||||
lwz r19, GP_19(r3)
|
||||
lwz r20, GP_20(r3)
|
||||
lwz r21, GP_21(r3)
|
||||
lwz r22, GP_22(r3)
|
||||
lwz r23, GP_23(r3)
|
||||
lwz r24, GP_24(r3)
|
||||
lwz r25, GP_25(r3)
|
||||
lwz r26, GP_26(r3)
|
||||
lwz r27, GP_27(r3)
|
||||
lwz r28, GP_28(r3)
|
||||
lwz r29, GP_29(r3)
|
||||
lwz r30, GP_30(r3)
|
||||
lwz r31, GP_31(r3)
|
||||
#endif
|
||||
|
||||
blr
|
||||
|
||||
@@ -1,2 +0,0 @@
|
||||
Makefile
|
||||
Makefile.in
|
||||
@@ -1,58 +0,0 @@
|
||||
##
|
||||
## $Id$
|
||||
##
|
||||
|
||||
AUTOMAKE_OPTIONS = foreign 1.4
|
||||
ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
|
||||
|
||||
# C source names
|
||||
C_FILES = cpu.c
|
||||
C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o)
|
||||
|
||||
ROOT_H_FILES =
|
||||
RTEMS_SCORE_H_FILES = cpu.h c_isr.inl
|
||||
noinst_HEADERS = $(ROOT_H_FILES) $(RTEMS_SCORE_H_FILES)
|
||||
|
||||
# Assembly source names
|
||||
S_FILES = cpu_asm.S
|
||||
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
|
||||
|
||||
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
|
||||
include $(top_srcdir)/../../../../../automake/lib.am
|
||||
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/rtems/score \
|
||||
$(ROOT_H_FILES:%=$(PROJECT_INCLUDE)/%) \
|
||||
$(RTEMS_SCORE_H_FILES:%=$(PROJECT_INCLUDE)/rtems/score/%)
|
||||
|
||||
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/rtems$(LIB_VARIANT).o
|
||||
|
||||
$(PROJECT_RELEASE)/lib/rtems$(LIB_VARIANT).o: $(ARCH)/rtems.o
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
$(PROJECT_INCLUDE):
|
||||
$(mkinstalldirs) $@
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score:
|
||||
$(mkinstalldirs) $@
|
||||
|
||||
$(PROJECT_INCLUDE)/rtems/score/%: %
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
$(PROJECT_INCLUDE)/%: %
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
REL = $(ARCH)/rtems-cpu.rel
|
||||
|
||||
$(REL): $(C_O_FILES) $(S_O_FILES)
|
||||
test -d ../$(ARCH) || mkdir ../$(ARCH)
|
||||
$(make-rel)
|
||||
|
||||
all-local: $(ARCH) $(PREINSTALL_FILES) $(REL) $(ARCH)/rtems.o $(TMPINSTALL_FILES)
|
||||
|
||||
CLEANDIRS = ../o-optimize ../o-debug ../o-profile
|
||||
|
||||
UNUSED_FILES = irq_stub.S
|
||||
|
||||
EXTRA_DIST = TODO rtems.S $(C_FILES) $(S_FILES) $(UNUSED_FILES)
|
||||
|
||||
include $(top_srcdir)/../../../../../automake/local.am
|
||||
@@ -1,80 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
There are various issues regarding this port:
|
||||
|
||||
|
||||
|
||||
1) Legal
|
||||
|
||||
This port is written by Andrew Bray <andy@i-cubed.co.uk>, and
|
||||
is copyright 1995 i-cubed ltd.
|
||||
|
||||
This port was later updated by Joel Sherrill <joel@OARcorp.com>
|
||||
to test the support for the PPC603, PPC603e, and MPC604. This
|
||||
was tested on the PowerPC simulator PSIM and a VMEbus single board
|
||||
computer.
|
||||
|
||||
2) CPU support.
|
||||
|
||||
This release fully supports the PPC403GA, PPC403GB, PPC603, PPC603e,
|
||||
MPC604, MPC750, and numerous MPC8xx processors. A good faith attempt
|
||||
has been made to include support other models based upon available
|
||||
documentation including the MPC5xx. There are two interrupt structures
|
||||
supported by the PowerPC port. The newer structure is supported by
|
||||
all the MPC750 and MPC604 BSPs. This structure is required to use
|
||||
the RDBG remote debugging support.
|
||||
|
||||
This port was originally written and tested on the PPC403GA (using
|
||||
software floating point). Current ports are tested primarily on
|
||||
60x CPUs using the PowerPC simulator PSIM.
|
||||
|
||||
Andrew Bray received assistance during the initial porting effort
|
||||
from IBM and Blue Micro and we would like to gratefully acknowledge
|
||||
that help.
|
||||
|
||||
The support for the PPC602 processor is incomplete as only sketchy
|
||||
data is currently available. Perhaps this model has been dropped.
|
||||
|
||||
3) Application Binary Interface
|
||||
|
||||
In the context of RTEMS, the ABI is of interest for the following
|
||||
aspects:
|
||||
|
||||
a) Register usage. Which registers are used to provide static variable
|
||||
linkage, stack pointer etc.
|
||||
|
||||
b) Function calling convention. How parameters are passed, how function
|
||||
variables should be invoked, how values are returned, etc.
|
||||
|
||||
c) Stack frame layout.
|
||||
|
||||
I am aware of a number of ABIs for the PowerPC:
|
||||
|
||||
a) The PowerOpen ABI. This is the original Power ABI used on the RS/6000.
|
||||
This is the only ABI supported by versions of GCC before 2.7.0.
|
||||
|
||||
b) The SVR4 ABI. This is the ABI defined by SunSoft for the Solaris port
|
||||
to the PowerPC.
|
||||
|
||||
c) The Embedded ABI. This is an embedded ABI for PowerPC use, which has no
|
||||
operating system interface defined. It is promoted by SunSoft, Motorola,
|
||||
and Cygnus Support. Cygnus are porting the GNU toolchain to this ABI.
|
||||
|
||||
d) GCC 2.7.0. This compiler is partway along the road to supporting the EABI,
|
||||
but is currently halfway in between.
|
||||
|
||||
This port was built and tested using the PowerOpen ABI, with the following
|
||||
caveat: we used an ELF assembler and linker. So some attention may be
|
||||
required on the assembler files to get them through a traditional (XCOFF)
|
||||
PowerOpen assembler.
|
||||
|
||||
This port contains support for the other ABIs, but this may prove to be
|
||||
incomplete as it is untested.
|
||||
|
||||
The RTEMS PowerPC port supports EABI as the primary ABI. The powerpc-rtems
|
||||
GNU toolset configuration is EABI.
|
||||
|
||||
Andrew Bray, 4 December 1995
|
||||
Joel Sherrill, 16 July 1997
|
||||
@@ -1,8 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
Todo list:
|
||||
|
||||
Maybe decode external interrupts like the HPPA does.
|
||||
See c/src/lib/libcpu/powerpc/ppc403/ictrl/* for implementation on ppc403
|
||||
@@ -1,4 +0,0 @@
|
||||
RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
|
||||
{
|
||||
return (_ISR_Nest_level != 0);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,270 +0,0 @@
|
||||
/*
|
||||
* This file contains the interrupt handler assembly code for the PowerPC
|
||||
* implementation of RTEMS. It is #included from cpu_asm.s.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/* void __ISR_Handler()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
* The vector number is in r0. R0 has already been stacked.
|
||||
*
|
||||
*/
|
||||
PUBLIC_VAR (_CPU_IRQ_info )
|
||||
|
||||
/* Finish off the interrupt frame */
|
||||
stw r2, IP_2(r1)
|
||||
stw r3, IP_3(r1)
|
||||
stw r4, IP_4(r1)
|
||||
stw r5, IP_5(r1)
|
||||
stw r6, IP_6(r1)
|
||||
stw r7, IP_7(r1)
|
||||
stw r8, IP_8(r1)
|
||||
stw r9, IP_9(r1)
|
||||
stw r10, IP_10(r1)
|
||||
stw r11, IP_11(r1)
|
||||
stw r12, IP_12(r1)
|
||||
stw r13, IP_13(r1)
|
||||
stmw r28, IP_28(r1)
|
||||
mfcr r5
|
||||
mfctr r6
|
||||
mfxer r7
|
||||
mflr r8
|
||||
MFPC (r9)
|
||||
MFMSR (r10)
|
||||
/* Establish addressing */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r11, sprg3
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
#endif
|
||||
#if ( PPC_USE_DATA_CACHE )
|
||||
dcbt r0, r11
|
||||
#endif
|
||||
stw r5, IP_CR(r1)
|
||||
stw r6, IP_CTR(r1)
|
||||
stw r7, IP_XER(r1)
|
||||
stw r8, IP_LR(r1)
|
||||
stw r9, IP_PC(r1)
|
||||
stw r10, IP_MSR(r1)
|
||||
|
||||
lwz r30, Vector_table(r11)
|
||||
slwi r4,r0,2
|
||||
lwz r28, Nest_level(r11)
|
||||
add r4, r4, r30
|
||||
|
||||
lwz r30, 0(r28)
|
||||
mr r3, r0
|
||||
lwz r31, Stack(r11)
|
||||
/*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* if ( _ISR_Nest_level == 0 )
|
||||
* switch to software interrupt stack
|
||||
* #endif
|
||||
*/
|
||||
/* Switch stacks, here we must prevent ALL interrupts */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfmsr r5
|
||||
mfspr r6, sprg2
|
||||
#else
|
||||
lwz r6,msr_initial(r11)
|
||||
lis r5,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
|
||||
and r6,r6,r5
|
||||
mfmsr r5
|
||||
#endif
|
||||
mtmsr r6
|
||||
cmpwi r30, 0
|
||||
lwz r29, Disable_level(r11)
|
||||
subf r31,r1,r31
|
||||
bne LABEL (nested)
|
||||
stwux r1,r1,r31
|
||||
LABEL (nested):
|
||||
/*
|
||||
* _ISR_Nest_level++;
|
||||
*/
|
||||
lwz r31, 0(r29)
|
||||
addi r30,r30,1
|
||||
stw r30,0(r28)
|
||||
/* From here on out, interrupts can be re-enabled. RTEMS
|
||||
* convention says not.
|
||||
*/
|
||||
lwz r4,0(r4)
|
||||
/*
|
||||
* _Thread_Dispatch_disable_level++;
|
||||
*/
|
||||
addi r31,r31,1
|
||||
stw r31, 0(r29)
|
||||
/* SCE 980217
|
||||
*
|
||||
* We need address translation ON when we call our ISR routine
|
||||
|
||||
mtmsr r5
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* (*_ISR_Vector_table[ vector ])( vector );
|
||||
*/
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
lwz r6,0(r4)
|
||||
lwz r2,4(r4)
|
||||
mtlr r6
|
||||
lwz r11,8(r4)
|
||||
#endif
|
||||
#if (PPC_ABI == PPC_ABI_GCC27)
|
||||
lwz r2, Default_r2(r11)
|
||||
mtlr r4
|
||||
#lwz r2, 0(r2)
|
||||
#endif
|
||||
#if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI)
|
||||
mtlr r4
|
||||
lwz r2, Default_r2(r11)
|
||||
lwz r13, Default_r13(r11)
|
||||
#lwz r2, 0(r2)
|
||||
#lwz r13, 0(r13)
|
||||
#endif
|
||||
mr r4,r1
|
||||
blrl
|
||||
/* NOP marker for debuggers */
|
||||
or r6,r6,r6
|
||||
|
||||
/* We must re-disable the interrupts */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r11, sprg3
|
||||
mfspr r0, sprg2
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
lwz r0,msr_initial(r11)
|
||||
lis r30,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r30,r30,~PPC_MSR_DISABLE_MASK@l
|
||||
and r0,r0,r30
|
||||
#endif
|
||||
mtmsr r0
|
||||
lwz r30, 0(r28)
|
||||
lwz r31, 0(r29)
|
||||
|
||||
/*
|
||||
* if (--Thread_Dispatch_disable,--_ISR_Nest_level)
|
||||
* goto easy_exit;
|
||||
*/
|
||||
addi r30, r30, -1
|
||||
cmpwi r30, 0
|
||||
addi r31, r31, -1
|
||||
stw r30, 0(r28)
|
||||
stw r31, 0(r29)
|
||||
bne LABEL (easy_exit)
|
||||
cmpwi r31, 0
|
||||
|
||||
lwz r30, Switch_necessary(r11)
|
||||
|
||||
/*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* restore stack
|
||||
* #endif
|
||||
*/
|
||||
lwz r1,0(r1)
|
||||
bne LABEL (easy_exit)
|
||||
lwz r30, 0(r30)
|
||||
lwz r31, Signal(r11)
|
||||
|
||||
/*
|
||||
* if ( _Context_Switch_necessary )
|
||||
* goto switch
|
||||
*/
|
||||
cmpwi r30, 0
|
||||
lwz r28, 0(r31)
|
||||
li r6,0
|
||||
bne LABEL (switch)
|
||||
/*
|
||||
* if ( !_ISR_Signals_to_thread_executing )
|
||||
* goto easy_exit
|
||||
* _ISR_Signals_to_thread_executing = 0;
|
||||
*/
|
||||
cmpwi r28, 0
|
||||
beq LABEL (easy_exit)
|
||||
|
||||
/*
|
||||
* switch:
|
||||
* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
|
||||
*/
|
||||
LABEL (switch):
|
||||
stw r6, 0(r31)
|
||||
/* Re-enable interrupts */
|
||||
lwz r0, IP_MSR(r1)
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
lwz r2, Dispatch_r2(r11)
|
||||
#else
|
||||
/* R2 and R13 still hold their values from the last call */
|
||||
#endif
|
||||
mtmsr r0
|
||||
bl SYM (_Thread_Dispatch)
|
||||
/* NOP marker for debuggers */
|
||||
or r6,r6,r6
|
||||
/*
|
||||
* prepare to get out of interrupt
|
||||
*/
|
||||
/* Re-disable IRQs */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r0, sprg2
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
lwz r0,msr_initial(r11)
|
||||
lis r5,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
|
||||
and r0,r0,r5
|
||||
#endif
|
||||
mtmsr r0
|
||||
|
||||
/*
|
||||
* easy_exit:
|
||||
* prepare to get out of interrupt
|
||||
* return from interrupt
|
||||
*/
|
||||
LABEL (easy_exit):
|
||||
lwz r5, IP_CR(r1)
|
||||
lwz r6, IP_CTR(r1)
|
||||
lwz r7, IP_XER(r1)
|
||||
lwz r8, IP_LR(r1)
|
||||
lwz r9, IP_PC(r1)
|
||||
lwz r10, IP_MSR(r1)
|
||||
mtcrf 255,r5
|
||||
mtctr r6
|
||||
mtxer r7
|
||||
mtlr r8
|
||||
MTPC (r9)
|
||||
MTMSR (r10)
|
||||
lwz r0, IP_0(r1)
|
||||
lwz r2, IP_2(r1)
|
||||
lwz r3, IP_3(r1)
|
||||
lwz r4, IP_4(r1)
|
||||
lwz r5, IP_5(r1)
|
||||
lwz r6, IP_6(r1)
|
||||
lwz r7, IP_7(r1)
|
||||
lwz r8, IP_8(r1)
|
||||
lwz r9, IP_9(r1)
|
||||
lwz r10, IP_10(r1)
|
||||
lwz r11, IP_11(r1)
|
||||
lwz r12, IP_12(r1)
|
||||
lwz r13, IP_13(r1)
|
||||
lmw r28, IP_28(r1)
|
||||
lwz r1, 0(r1)
|
||||
@@ -1,132 +0,0 @@
|
||||
/* rtems.s
|
||||
*
|
||||
* This file contains the single entry point code for
|
||||
* the PowerPC implementation of RTEMS.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/rtems.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
|
||||
BEGIN_CODE
|
||||
/*
|
||||
* RTEMS
|
||||
*
|
||||
* This routine jumps to the directive indicated in r11.
|
||||
* This routine is used when RTEMS is linked by itself and placed
|
||||
* in ROM. This routine is the first address in the ROM space for
|
||||
* RTEMS. The user "calls" this address with the directive arguments
|
||||
* in the normal place.
|
||||
* This routine then jumps indirectly to the correct directive
|
||||
* preserving the arguments. The directive should not realize
|
||||
* it has been "wrapped" in this way. The table "_Entry_points"
|
||||
* is used to look up the directive.
|
||||
*/
|
||||
|
||||
ALIGN (4, 2)
|
||||
PUBLIC_PROC (RTEMS)
|
||||
PROC (RTEMS):
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
mflr r0
|
||||
stw r0, 8(r1)
|
||||
stwu r1, -64(r1)
|
||||
|
||||
/* Establish addressing */
|
||||
bl base
|
||||
base:
|
||||
mflr r12
|
||||
addi r12, r12, tabaddr - base
|
||||
|
||||
lwz r12, Entry_points-abase(r12)
|
||||
slwi r11, r11, 2
|
||||
lwzx r12, r12, r11
|
||||
|
||||
stw r2, 56(r1)
|
||||
lwz r0, 0(r12)
|
||||
mtlr r0
|
||||
lwz r2, 4(r12)
|
||||
lwz r11, 8(r12)
|
||||
blrl
|
||||
lwz r2, 56(r1)
|
||||
addi r1, r1, 64
|
||||
lwz r0, 8(r1)
|
||||
mtlr r0
|
||||
#else
|
||||
mflr r0
|
||||
stw r0, 4(r1)
|
||||
stwu r1, -16(r1)
|
||||
|
||||
/* Establish addressing */
|
||||
bl base
|
||||
base:
|
||||
mflr r12
|
||||
addi r12, r12, tabaddr - base
|
||||
|
||||
lwz r12, Entry_points-abase(r12)
|
||||
slwi r11, r11, 2
|
||||
lwzx r11, r12, r11
|
||||
|
||||
stw r2, 8(r1)
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
stw r13, 12(r1)
|
||||
#endif
|
||||
mtlr r11
|
||||
lwz r11, irqinfo-abase(r12)
|
||||
lwz r2, 0(r11)
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
lwz r13, 4(r11)
|
||||
#endif
|
||||
blrl
|
||||
lwz r2, 8(r1)
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
lwz r13, 12(r1)
|
||||
#endif
|
||||
addi r1, r1, 16
|
||||
lwz r0, 4(r1)
|
||||
mtlr r0
|
||||
#endif
|
||||
blr
|
||||
|
||||
|
||||
/* Addressability stuff */
|
||||
tabaddr:
|
||||
abase:
|
||||
EXTERN_VAR (_Entry_points)
|
||||
Entry_points:
|
||||
EXT_SYM_REF (_Entry_points)
|
||||
#if (PPC_ABI != PPC_ABI_POWEROPEN)
|
||||
EXTERN_VAR (_CPU_IRQ_info)
|
||||
irqinfo:
|
||||
EXT_SYM_REF (_CPU_IRQ_info)
|
||||
#endif
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
DESCRIPTOR (RTEMS)
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user