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cpukit/score/cpu/mips: Validate the context
The two routines were empty, so the validation task of spcontext01 spun in a loop which checked nothing. The zero register, the stack pointer, the global pointer and the k0 and k1 of the exception handler stay out of the pattern, and so do the registers of the FPU, which need it enabled in the status register of the coprocessor. Close #5691. Assisted-by: Claude:claude-opus-5 claude-code Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
This commit is contained in:
Sebastian Huber
committed by
Joel Sherrill
Joel Sherrill
parent
2798059616
commit
c6666a5a53
@@ -56,21 +56,9 @@
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extern "C" {
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#endif
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static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
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{
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(void) pattern;
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void _CPU_Context_volatile_clobber( uintptr_t pattern );
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/* TODO */
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}
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static inline void _CPU_Context_validate( uintptr_t pattern )
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{
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(void) pattern;
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while (1) {
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/* TODO */
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}
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}
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void _CPU_Context_validate( uintptr_t pattern );
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static inline void _CPU_Instruction_illegal( void )
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{
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@@ -0,0 +1,176 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2026 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/mips/iregdef.h>
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/*
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* The pattern arrives in a0 and stays there, AT is the temporary of the check.
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* The zero register, the stack pointer, the global pointer and the k0 and k1
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* of the exception handler are not part of the pattern. The thread pointer of
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* this port lives in the context and not in a register. The stack pointer is
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* compared through the frame, since no register is left for it.
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*
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* A hard float build saves the registers of the FPU in the floating point
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* context of a thread. They are not covered here, since that needs the FPU
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* enabled in the status register of the coprocessor and no BSP of the test
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* programme has one.
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*/
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#define FRAME_OFFSET_S0 0
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#define FRAME_OFFSET_S1 4
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#define FRAME_OFFSET_S2 8
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#define FRAME_OFFSET_S3 12
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#define FRAME_OFFSET_S4 16
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#define FRAME_OFFSET_S5 20
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#define FRAME_OFFSET_S6 24
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#define FRAME_OFFSET_S7 28
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#define FRAME_OFFSET_FP 32
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#define FRAME_OFFSET_RA 36
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#define FRAME_OFFSET_SP_XOR 40
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#define FRAME_SIZE 48
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.set noreorder
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.set noat
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.text
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FRAME(_CPU_Context_validate,sp,0,ra)
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addiu sp, sp, -FRAME_SIZE
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sw s0, FRAME_OFFSET_S0(sp)
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sw s1, FRAME_OFFSET_S1(sp)
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sw s2, FRAME_OFFSET_S2(sp)
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sw s3, FRAME_OFFSET_S3(sp)
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sw s4, FRAME_OFFSET_S4(sp)
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sw s5, FRAME_OFFSET_S5(sp)
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sw s6, FRAME_OFFSET_S6(sp)
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sw s7, FRAME_OFFSET_S7(sp)
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sw fp, FRAME_OFFSET_FP(sp)
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sw ra, FRAME_OFFSET_RA(sp)
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xor AT, sp, a0
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sw AT, FRAME_OFFSET_SP_XOR(sp)
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/* Fill */
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.macro fill_register reg, inc
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addiu \reg, a0, \inc
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.endm
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fill_register v0, 1
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fill_register v1, 2
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fill_register a1, 3
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fill_register a2, 4
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fill_register a3, 5
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fill_register t0, 6
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fill_register t1, 7
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fill_register t2, 8
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fill_register t3, 9
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fill_register t4, 10
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fill_register t5, 11
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fill_register t6, 12
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fill_register t7, 13
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fill_register t8, 14
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fill_register t9, 15
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fill_register s0, 16
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fill_register s1, 17
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fill_register s2, 18
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fill_register s3, 19
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fill_register s4, 20
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fill_register s5, 21
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fill_register s6, 22
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fill_register s7, 23
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fill_register fp, 24
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fill_register ra, 25
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/* Check */
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.macro check_register reg, inc
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addiu AT, a0, \inc
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bne \reg, AT, .Lrestore
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nop
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.endm
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.Lcheck:
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check_register v0, 1
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check_register v1, 2
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check_register a1, 3
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check_register a2, 4
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check_register a3, 5
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check_register t0, 6
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check_register t1, 7
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check_register t2, 8
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check_register t3, 9
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check_register t4, 10
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check_register t5, 11
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check_register t6, 12
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check_register t7, 13
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check_register t8, 14
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check_register t9, 15
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check_register s0, 16
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check_register s1, 17
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check_register s2, 18
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check_register s3, 19
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check_register s4, 20
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check_register s5, 21
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check_register s6, 22
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check_register s7, 23
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check_register fp, 24
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check_register ra, 25
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lw AT, FRAME_OFFSET_SP_XOR(sp)
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xor AT, AT, a0
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bne AT, sp, .Lrestore
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nop
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b .Lcheck
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nop
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/* Restore */
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.Lrestore:
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lw s0, FRAME_OFFSET_S0(sp)
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lw s1, FRAME_OFFSET_S1(sp)
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lw s2, FRAME_OFFSET_S2(sp)
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lw s3, FRAME_OFFSET_S3(sp)
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lw s4, FRAME_OFFSET_S4(sp)
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lw s5, FRAME_OFFSET_S5(sp)
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lw s6, FRAME_OFFSET_S6(sp)
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lw s7, FRAME_OFFSET_S7(sp)
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lw fp, FRAME_OFFSET_FP(sp)
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lw ra, FRAME_OFFSET_RA(sp)
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j ra
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addiu sp, sp, FRAME_SIZE
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ENDFRAME(_CPU_Context_validate)
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@@ -0,0 +1,69 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2026 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/mips/iregdef.h>
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/*
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* The caller saved registers of the ABI are v0, v1, a0 to a3 and t0 to t9.
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* a0 arrives with the pattern and is clobbered last.
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*/
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.set noreorder
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.text
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FRAME(_CPU_Context_volatile_clobber,sp,0,ra)
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.macro clobber_register reg, inc
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addiu \reg, a0, \inc
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.endm
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clobber_register v0, 1
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clobber_register v1, 2
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clobber_register a1, 3
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clobber_register a2, 4
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clobber_register a3, 5
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clobber_register t0, 6
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clobber_register t1, 7
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clobber_register t2, 8
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clobber_register t3, 9
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clobber_register t4, 10
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clobber_register t5, 11
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clobber_register t6, 12
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clobber_register t7, 13
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clobber_register t8, 14
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clobber_register t9, 15
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j ra
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clobber_register a0, 16
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ENDFRAME(_CPU_Context_volatile_clobber)
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@@ -28,6 +28,8 @@ links: []
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source:
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- cpukit/score/cpu/mips/cpu.c
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- cpukit/score/cpu/mips/cpu_asm.S
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- cpukit/score/cpu/mips/mips-context-validate.S
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- cpukit/score/cpu/mips/mips-context-volatile-clobber.S
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- cpukit/score/cpu/no_cpu/cpucounterfrequency.c
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- cpukit/score/cpu/no_cpu/cpucounterread.c
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type: build
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