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2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>

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* cpu.c, sse_test.c, rtems/score/cpu.h, rtems/score/i386.h,
	rtems/score/interrupts.h:
	Use "__asm__" instead of "asm" for improved c99-compliance.
This commit is contained in:
Ralf Corsepius
2011-02-11 09:14:20 +00:00
parent 01850cde14
commit c05f6238b9
6 changed files with 30 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpukit/score/cpu/i386/ChangeLog
+6
View File
@@ -1,3 +1,9 @@
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* cpu.c, sse_test.c, rtems/score/cpu.h, rtems/score/i386.h,
rtems/score/interrupts.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
2010-07-29 Gedare Bloom <giddyup44@yahoo.com>
PR 1635/cpukit
cpukit/score/cpu/i386/cpu.c
+6 -6
View File
@@ -35,7 +35,7 @@
void _CPU_Initialize(void)
{
#if CPU_HARDWARE_FP
register uint16_t fp_status asm ("ax");
register uint16_t fp_status __asm__ ("ax");
register Context_Control_fp *fp_context;
#endif
@@ -53,8 +53,8 @@ void _CPU_Initialize(void)
#if CPU_HARDWARE_FP
fp_status = 0xa5a5;
asm volatile( "fninit" );
asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
__asm__ volatile( "fninit" );
__asm__ volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
if ( fp_status == 0 ) {
@@ -63,7 +63,7 @@ void _CPU_Initialize(void)
#ifdef __SSE__
asm volatile( "fstcw %0":"=m"(fp_context->fpucw) );
#else
asm volatile( "fsave (%0)" : "=r" (fp_context)
__asm__ volatile( "fsave (%0)" : "=r" (fp_context)
: "0" (fp_context)
);
#endif
@@ -72,7 +72,7 @@ void _CPU_Initialize(void)
#ifdef __SSE__
asm volatile("stmxcsr %0":"=m"(fp_context->mxcsr));
__asm__ volatile("stmxcsr %0":"=m"(fp_context->mxcsr));
/* The BSP must enable the SSE extensions (early).
* If any SSE instruction was already attempted
@@ -111,7 +111,7 @@ uint32_t _CPU_ISR_Get_level( void )
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
while(1){
asm volatile ("hlt");
__asm__ volatile ("hlt");
}
return NULL;
}
cpukit/score/cpu/i386/rtems/score/cpu.h
+4 -4
View File
@@ -354,8 +354,8 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
#define _CPU_ISR_Set_level( _new_level ) \
{ \
if ( _new_level ) asm volatile ( "cli" ); \
else asm volatile ( "sti" ); \
if ( _new_level ) __asm__ volatile ( "cli" ); \
else __asm__ volatile ( "sti" ); \
}
uint32_t _CPU_ISR_Get_level( void );
@@ -456,7 +456,7 @@ uint32_t _CPU_ISR_Get_level( void );
#define _CPU_Fatal_halt( _error ) \
{ \
asm volatile ( "cli ; \
__asm__ volatile ( "cli ; \
movl %0,%%eax ; \
hlt" \
: "=r" ((_error)) : "0" ((_error)) \
@@ -483,7 +483,7 @@ uint32_t _CPU_ISR_Get_level( void );
\
_output = 0; \
\
asm volatile ( "bsfw %0,%1 " \
__asm__ volatile ( "bsfw %0,%1 " \
: "=r" (__value_in_register), "=r" (_output) \
: "0" (__value_in_register), "1" (_output) \
); \
cpukit/score/cpu/i386/rtems/score/i386.h
+6 -6
View File
@@ -125,7 +125,7 @@ static inline uint32_t i386_swap_u32(
uint32_t lout;
#if (I386_HAS_BSWAP == 0)
asm volatile( "rorw $8,%%ax;"
__asm__ volatile( "rorw $8,%%ax;"
"rorl $16,%0;"
"rorw $8,%%ax" : "=a" (lout) : "0" (value) );
#else
@@ -153,21 +153,21 @@ static inline unsigned int i386_get_cr0(void)
{
register unsigned int segment = 0;
asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
__asm__ volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
static inline void i386_set_cr0(unsigned int segment)
{
asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
__asm__ volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
}
static inline unsigned int i386_get_cr2(void)
{
register unsigned int segment = 0;
asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
__asm__ volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
@@ -176,14 +176,14 @@ static inline unsigned int i386_get_cr3(void)
{
register unsigned int segment = 0;
asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
__asm__ volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
static inline void i386_set_cr3(unsigned int segment)
{
asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
__asm__ volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
}
/* routines */
cpukit/score/cpu/i386/rtems/score/interrupts.h
+4 -4
View File
@@ -36,7 +36,7 @@ typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_d
#define i386_disable_interrupts( _level ) \
{ \
asm volatile ( "pushf ; \
__asm__ volatile ( "pushf ; \
cli ; \
pop %0" \
: "=rm" ((_level)) \
@@ -45,7 +45,7 @@ typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_d
#define i386_enable_interrupts( _level ) \
{ \
asm volatile ( "push %0 ; \
__asm__ volatile ( "push %0 ; \
popf" \
: : "rm" ((_level)) : "cc" \
); \
@@ -53,7 +53,7 @@ typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_d
#define i386_flash_interrupts( _level ) \
{ \
asm volatile ( "push %0 ; \
__asm__ volatile ( "push %0 ; \
popf ; \
cli" \
: : "rm" ((_level)) : "cc" \
@@ -64,7 +64,7 @@ typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_d
do { \
register uint32_t _eflags; \
\
asm volatile ( "pushf ; \
__asm__ volatile ( "pushf ; \
pop %0" \
: "=rm" ((_eflags)) \
); \
cpukit/score/cpu/i386/sse_test.c
+4 -4
View File
@@ -255,7 +255,7 @@ __v32 v = { x, x, x, x };
void
all_clobber(uint32_t v1, uint32_t v2);
asm(
__asm__ (
"all_clobber: \n"
" finit \n"
" movq 0(%esp), %xmm0 \n"
@@ -275,7 +275,7 @@ asm(
void
init_ctxt(Context_Control_sse *p_ctxt);
asm(
__asm__ (
"init_ctxt: \n"
" finit \n"
" mov 4(%esp), %eax\n"
@@ -398,7 +398,7 @@ int i;
#define __INTRAISE(x) " int $32+"#x" \n"
#define INTRAISE(x) __INTRAISE(x)
asm(
__asm__ (
"do_raise: \n"
" fwait \n"
" test %eax, %eax \n"
@@ -834,7 +834,7 @@ __vf f4;
#define MKCASE(X) case FPE_##X: msg="FPE_"#X; break;
#define CLRXMM(i) asm volatile("pxor %%xmm"#i", %%xmm"#i:::"xmm"#i)
#define CLRXMM(i) __asm__ volatile("pxor %%xmm"#i", %%xmm"#i:::"xmm"#i)
static void
fpe_act(int signum, siginfo_t *p_info, void *arg3)