mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-10-06 10:59:48 +08:00
dev/sc16is752: Add GPIO access via ioctl.
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@@ -107,6 +107,8 @@ extern "C" {
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#define EFR_RTS_FLOW_CTRL_EN (1u << 6)
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#define EFR_CTS_FLOW_CTRL_EN (1u << 7)
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/* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */
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#define SC16IS752_FIFO_DEPTH 64
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#ifdef __cplusplus
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@@ -282,6 +282,7 @@ static int sc16is752_ioctl(
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)
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{
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sc16is752_context *ctx = (sc16is752_context *)base;
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uint8_t regval;
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switch (request) {
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case SC16IS752_SET_SLEEP_MODE:
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@@ -290,6 +291,25 @@ static int sc16is752_ioctl(
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case SC16IS752_GET_SLEEP_MODE:
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*(int *)buffer = is_sleep_mode_enabled(ctx);
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break;
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case SC16IS752_SET_IOCONTROL:
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regval = (*(uint8_t *)buffer) & ~SC16IS752_IOCONTROL_SRESET;
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write_reg(ctx, SC16IS752_IOCONTROL, ®val, 1);
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break;
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case SC16IS752_GET_IOCONTROL:
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read_reg(ctx, SC16IS752_IOCONTROL, (uint8_t *)buffer, 1);
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break;
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case SC16IS752_SET_IODIR:
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write_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1);
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break;
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case SC16IS752_GET_IODIR:
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read_reg(ctx, SC16IS752_IODIR, (uint8_t *)buffer, 1);
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break;
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case SC16IS752_SET_IOSTATE:
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write_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1);
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break;
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case SC16IS752_GET_IOSTATE:
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read_reg(ctx, SC16IS752_IOSTATE, (uint8_t *)buffer, 1);
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break;
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default:
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rtems_set_errno_and_return_minus_one(EINVAL);
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}
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@@ -250,11 +250,56 @@ rtems_status_code sc16is752_spi_create(
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*/
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#define SC16IS752_SET_SLEEP_MODE _IOW('d', 0, int)
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/**
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* @brief Set the I/O Control bits except for the SRESET.
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*
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* Note that it will not be possible to set the SRESET. Otherwise the driver
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* might would have an undefined state.
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*/
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#define SC16IS752_SET_IOCONTROL _IOW('d', 1, uint8_t)
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/**
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* @brief Set the I/O pins direction register.
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*/
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#define SC16IS752_SET_IODIR _IOW('d', 2, uint8_t)
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/**
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* @brief Set the I/O pins state register.
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*/
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#define SC16IS752_SET_IOSTATE _IOW('d', 3, uint8_t)
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/**
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* @brief Returns non-zero in case the sleep mode is enabled, otherwise zero.
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*/
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#define SC16IS752_GET_SLEEP_MODE _IOR('d', 0, int)
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/**
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* @brief Read the I/O Control register.
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*/
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#define SC16IS752_GET_IOCONTROL _IOR('d', 1, uint8_t)
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/**
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* @brief Read the I/O pins direction register.
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*/
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#define SC16IS752_GET_IODIR _IOR('d', 2, uint8_t)
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/**
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* @brief Read the I/O pins state register.
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*/
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#define SC16IS752_GET_IOSTATE _IOR('d', 3, uint8_t)
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/**
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* @brief Bits for the IOCONTROL register.
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* @{
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*/
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#define SC16IS752_IOCONTROL_SRESET (1u << 3)
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#define SC16IS752_IOCONTROL_GPIO_3_0_OR_MODEM (1u << 2)
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#define SC16IS752_IOCONTROL_GPIO_7_4_OR_MODEM (1u << 1)
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#define SC16IS752_IOCONTROL_IOLATCH (1u << 0)
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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