Mirrors_Framework/rtems
1
0
Fork 0
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2026-09-23 11:36:59 +08:00
Code Issues Packages Projects Releases Wiki Activity

bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.

Browse Source 
The header files are generated by script make_header.py.
Current script's version can be found at:

https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python

Registers offsets and fields have been extracted from reference manual.

Signed-off-by: Premysl Houdek <kom541000@gmail.com>
This commit is contained in:
Premysl Houdek
2015-07-16 09:31:09 -07:00
committed by Joel Sherrill
parent 4784214a6a
commit bea49c9477
37 changed files with 14362 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libbsp/arm/tms570/Makefile.am
+39
View File
@@ -11,6 +11,8 @@ include $(top_srcdir)/../../../../automake/compile.am
include_bspdir = $(includedir)/bsp
include_bsp_ti_herculesdir = $(includedir)/bsp/ti_herc
dist_project_lib_DATA = bsp_specs
# ----------------------------
@@ -40,6 +42,43 @@ include_bsp_HEADERS += include/tms570-pom.h
include_bsp_HEADERS += include/tms570-sci-driver.h
include_bsp_HEADERS += include/system-clocks.h
include_bsp_ti_hercules_HEADERS = include/ti_herc/reg_adc.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_ccmsr.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_crc.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dcan.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dcc.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dma.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dmm.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_efuse.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emac.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emacm.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emif.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_esm.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_flash.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_flex_ray.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_gio.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_htu.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_i2c.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_iomm.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_lin.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_mdio.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_n2het.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pbist.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pll.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pmm.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_rti.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_rtp.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_sci.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_tcr.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_tcram.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_vim.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pom.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_spi.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_stc.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_sys.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_sys2.h
include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pcr.h
include_HEADERS += ../../shared/include/tm27.h
# ----------------------------
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
+626
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
+72
View File
@@ -0,0 +1,72 @@
/* The header file is generated by make_header.py from CCMSR.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_CCMSR
#define LIBBSP_ARM_tms570_CCMSR
#include <bsp/utility.h>
typedef struct{
uint32_t CCMSR; /*CCM-R4F Status Register*/
uint32_t CCMKEYR; /*CCM-R4F Key Register*/
} tms570_ccmsr_t;
/*---------------------TMS570_CCMSRCCMSR---------------------*/
/* field: CMPE - Compare Error */
#define TMS570_CCMSR_CCMSR_CMPE BSP_FLD32(16)
/* field: STC - Self-test Complete */
#define TMS570_CCMSR_CCMSR_STC BSP_FLD32(8)
/* field: STET - Self-test Error Type */
#define TMS570_CCMSR_CCMSR_STET BSP_FLD32(1)
/* field: STE - Self-test Error */
#define TMS570_CCMSR_CCMSR_STE BSP_FLD32(0)
/*--------------------TMS570_CCMSRCCMKEYR--------------------*/
/* field: MKEY - Mode Key */
#define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3)
#define TMS570_CCMSR_CCMKEYR_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_CCMSR_CCMKEYR_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
#endif /* LIBBSP_ARM_tms570_CCMSR */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
+427
View File
@@ -0,0 +1,427 @@
/* The header file is generated by make_header.py from CRC.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_CRC
#define LIBBSP_ARM_tms570_CRC
#include <bsp/utility.h>
typedef struct{
uint32_t CTRL0; /*CRC Global Control Register*/
uint8_t reserved1 [4];
uint32_t CTRL1; /*CRC Global Control Register 1*/
uint8_t reserved2 [4];
uint32_t CTRL2; /*CRC Global Control Register 2*/
uint8_t reserved3 [4];
uint32_t INTS; /*CRC Interrupt Enable Set Register*/
uint8_t reserved4 [4];
uint32_t INTR; /*CRC Interrupt Enable Reset Register*/
uint8_t reserved5 [4];
uint32_t STATUS; /*CRC Interrupt Status Register*/
uint8_t reserved6 [4];
uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/
uint8_t reserved7 [4];
uint32_t BUSY; /*CRC Busy Register*/
uint8_t reserved8 [4];
uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/
uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/
uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/
uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/
uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/
uint8_t reserved9 [12];
uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/
uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/
uint32_t REGL1; /*Channel 1 CRC Value Low Register*/
uint32_t REGH1; /*Channel 1 CRC Value High Register*/
uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/
uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/
uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/
uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/
uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/
uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/
uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/
uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/
uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/
uint8_t reserved10 [12];
uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/
uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/
uint32_t REGL2; /*Channel 2 CRC Value Low Register*/
uint32_t REGH2; /*Channel 2 CRC Value High Register*/
uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/
uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/
uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/
uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/
uint8_t reserved11 [128];
uint32_t BUS_SEL; /*Data Bus Selection Register*/
} tms570_crc_t;
/*----------------------TMS570_CRCCTRL0----------------------*/
/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8)
/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0)
/*----------------------TMS570_CRCCTRL1----------------------*/
/* field: PWDN - Power Down. */
#define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0)
/*----------------------TMS570_CRCCTRL2----------------------*/
/* field: CH2_MODE - Channel 2 Mode Selection */
#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4)
/* field: CH1_MODE - Channel 1 Mode Selection */
#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1)
#define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*-----------------------TMS570_CRCINTS-----------------------*/
/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12)
/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11)
/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10)
/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9)
/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8)
/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4)
/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3)
/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2)
/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1)
/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
#define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0)
/*-----------------------TMS570_CRCINTR-----------------------*/
/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12)
/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11)
/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10)
/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9)
/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8)
/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4)
/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
#define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3)
/* field: CH1_OVERENR - CH1_OVERENR */
#define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2)
/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1)
/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
#define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0)
/*----------------------TMS570_CRCSTATUS----------------------*/
/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12)
/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
#define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11)
/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
#define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10)
/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9)
/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
#define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8)
/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4)
/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
#define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3)
/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
#define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2)
/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1)
/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
#define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0)
/*-------------------TMS570_CRCINT_OFFS_REG-------------------*/
/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_CRCBUSY-----------------------*/
/* field: CH2_BUSY - CH2_BUSY. */
#define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8)
/* field: CH1_BUSY - CH1_BUSY. */
#define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0)
/*-------------------TMS570_CRCPCOUNT_REG1-------------------*/
/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
/*-------------------TMS570_CRCSCOUNT_REG1-------------------*/
/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_CRCCURSEC_REG1-------------------*/
/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_CRCWDTOPLD1---------------------*/
/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*---------------------TMS570_CRCBCTOPLD1---------------------*/
/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/
/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
#define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/
/* field: PSASIG1 - register. */
#define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_CRCREGL1----------------------*/
/* field: CRC1 - Channel 1 CRC Value Low Register. */
#define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_CRCREGH1----------------------*/
/* field: CRC1 - Channel 1 CRC Value Low Register. */
#define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/
/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/
/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_CRCRAW_DATAREGL1------------------*/
/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_CRCRAW_DATAREGH1------------------*/
/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_CRCPCOUNT_REG2-------------------*/
/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
/*-------------------TMS570_CRCSCOUNT_REG2-------------------*/
/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_CRCCURSEC_REG2-------------------*/
/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_CRCWDTOPLD2---------------------*/
/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*---------------------TMS570_CRCBCTOPLD2---------------------*/
/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/
/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
#define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/
/* field: PSASIG2 - Channel 2 PSA Signature High Register. */
#define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_CRCREGL2----------------------*/
/* field: CRC2 - stored at CRC2[31:0] register. */
#define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_CRCREGH2----------------------*/
/* field: CRC2 - Channel 2 CRC Value High Register. */
#define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/
/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/
/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_CRCRAW_DATAREGL2------------------*/
/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_CRCRAW_DATAREGH2------------------*/
/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_CRCBUS_SEL---------------------*/
/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
#define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2)
/* field: DTCMEn - Enable/disables the tracing of data TCM */
#define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1)
/* field: ITCMEn - Enable/disables the tracing of instruction TCM */
#define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_CRC */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
+962
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
+183
View File
@@ -0,0 +1,183 @@
/* The header file is generated by make_header.py from DCC.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_DCC
#define LIBBSP_ARM_tms570_DCC
#include <bsp/utility.h>
typedef struct{
uint32_t GCTRL; /*DCC Global Control Register*/
uint32_t REV; /*DCC Revision Id Register*/
uint32_t CNT0SEED; /*DCC Counter0 Seed Register*/
uint32_t VALID0SEED; /*DCC Valid0 Seed Register*/
uint32_t CNT1SEED; /*DCC Counter1 Seed Register*/
uint32_t STAT; /*DCC Status Register*/
uint32_t CNT0; /*DCC Counter0 Value Register*/
uint32_t VALID0; /*DCC Valid0 Value Register*/
uint32_t CNT1; /*DCC Counter1 Value Register*/
uint32_t CNT1CLKSRC; /*DCC Counter1 Clock Source Selection Register*/
uint32_t CNT0CLKSRC; /*DCC Counter0 Clock Source Selection Register*/
} tms570_dcc_t;
/*----------------------TMS570_DCCGCTRL----------------------*/
/* field: DONE_INT_ENA - Done Interrupt Enable. */
#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15)
#define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15)
#define TMS570_DCC_GCTRL_DONE_INT_ENA_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
/* field: SINGLE_SHOT - Single-Shot Mode Enable. */
#define TMS570_DCC_GCTRL_SINGLE_SHOT(val) BSP_FLD32(val,8, 11)
#define TMS570_DCC_GCTRL_SINGLE_SHOT_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_DCC_GCTRL_SINGLE_SHOT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: ERR_ENA - Error Interrupt Enable. */
#define TMS570_DCC_GCTRL_ERR_ENA(val) BSP_FLD32(val,4, 7)
#define TMS570_DCC_GCTRL_ERR_ENA_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_DCC_GCTRL_ERR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: DCC_ENA - DCC Enable. */
#define TMS570_DCC_GCTRL_DCC_ENA(val) BSP_FLD32(val,0, 3)
#define TMS570_DCC_GCTRL_DCC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-----------------------TMS570_DCCREV-----------------------*/
/* field: SCHEME - Reads return 01, writes have no effect. */
#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31)
#define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
#define TMS570_DCC_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
/* field: FUNC - Functional release number. Reads return 0x000, writes have no effect. */
#define TMS570_DCC_REV_FUNC(val) BSP_FLD32(val,16, 27)
#define TMS570_DCC_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27)
#define TMS570_DCC_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
/* field: RTL - Design release number. Reads return 0x00, writes have no effect. */
#define TMS570_DCC_REV_RTL(val) BSP_FLD32(val,11, 15)
#define TMS570_DCC_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
#define TMS570_DCC_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
/* field: MAJOR - Major revision number. Reads return 0x2, writes have no effect. */
#define TMS570_DCC_REV_MAJOR(val) BSP_FLD32(val,8, 10)
#define TMS570_DCC_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_DCC_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: CUSTOM - Custom version number. Reads return 0x0, writes have no effect. */
#define TMS570_DCC_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
#define TMS570_DCC_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
#define TMS570_DCC_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
/* field: MINOR - Minor revision number. Reads return 0x4, writes have no effect. */
#define TMS570_DCC_REV_MINOR(val) BSP_FLD32(val,0, 5)
#define TMS570_DCC_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*---------------------TMS570_DCCCNT0SEED---------------------*/
/* field: COUNT0_SEED - Seed value for DCC Counter0. */
#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
/*--------------------TMS570_DCCVALID0SEED--------------------*/
/* field: VALID0_SEED - XXX */
#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15)
#define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_DCCCNT1SEED---------------------*/
/* field: COUNT1_SEED - Seed value for DCC Counter1. */
#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
/*-----------------------TMS570_DCCSTAT-----------------------*/
/* field: DONE_FLG - Single-Shot Sequence Done flag. */
#define TMS570_DCC_STAT_DONE_FLG BSP_FLD32(1)
/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */
#define TMS570_DCC_STAT_ERR_FLG BSP_FLD32(0)
/*-----------------------TMS570_DCCCNT0-----------------------*/
/* field: COUNT0 - Current value of DCC Counter0. */
#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
/*----------------------TMS570_DCCVALID0----------------------*/
/* field: VALID0 - Current value for DCC Valid0. */
#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15)
#define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_DCCCNT1-----------------------*/
/* field: COUNT1 - Current value for DCC Counter1. */
#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
/*--------------------TMS570_DCCCNT1CLKSRC--------------------*/
/* field: KEY - Key to enable clock source selection for Counter1. */
#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15)
#define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15)
#define TMS570_DCC_CNT1CLKSRC_KEY_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
/* field: CNT1_CLKSRC - Clock Source for Counter1 when KEY is programmed to be 0xA. */
#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC(val) BSP_FLD32(val,0, 3)
#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*--------------------TMS570_DCCCNT0CLKSRC--------------------*/
/* field: CNT0_CLKSRC - Clock Source for Counter0 */
#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3)
#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
#endif /* LIBBSP_ARM_tms570_DCC */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
+732
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
+560
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
+132
View File
@@ -0,0 +1,132 @@
/* The header file is generated by make_header.py from EFUSE.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_EFUSE
#define LIBBSP_ARM_tms570_EFUSE
#include <bsp/utility.h>
typedef struct{
uint32_t EFCBOUND; /*EFC Boundary Control Register*/
uint8_t reserved1 [12];
uint32_t EFCPINS; /*EFC Pins Register*/
uint8_t reserved2 [12];
uint32_t EFC_ERR_STAT; /*EFC Error Status Register*/
uint8_t reserved3 [8];
uint32_t EFC_ST_CY; /*EFC Self Test Cycles Register*/
uint32_t EFC_ST_SIG; /*EFC Self Test Signature Register*/
} tms570_efuse_t;
/*--------------------TMS570_EFUSEEFCBOUND--------------------*/
/* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */
#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_FLD32(21)
/* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */
#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_FLD32(20)
/* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */
#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_FLD32(19)
/* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */
#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_FLD32(18)
/* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */
#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_FLD32(17)
/* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */
#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_FLD32(16)
/* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */
#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_FLD32(15)
/* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */
#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_FLD32(14)
/* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_FLD32(13)
/* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
#define TMS570_EFUSE_EFCBOUND_Input_Enable(val) BSP_FLD32(val,0, 3)
#define TMS570_EFUSE_EFCBOUND_Input_Enable_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_EFUSE_EFCBOUND_Input_Enable_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*--------------------TMS570_EFUSEEFCPINS--------------------*/
/* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */
#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_FLD32(15)
/* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */
#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_FLD32(14)
/* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */
#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_FLD32(12)
/* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */
#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_FLD32(11)
/* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */
#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_FLD32(10)
/*------------------TMS570_EFUSEEFC_ERR_STAT------------------*/
/* field: Instruc_Done - Instruction done. */
#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_FLD32(5)
/* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */
#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code(val) BSP_FLD32(val,0, 4)
#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*-------------------TMS570_EFUSEEFC_ST_CY-------------------*/
/* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */
#define TMS570_EFUSE_EFC_ST_CY_Cycles(val) BSP_FLD32(val,0, 31)
#define TMS570_EFUSE_EFC_ST_CY_Cycles_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_EFUSE_EFC_ST_CY_Cycles_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_EFUSEEFC_ST_SIG-------------------*/
/* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */
#define TMS570_EFUSE_EFC_ST_SIG_Signature(val) BSP_FLD32(val,0, 31)
#define TMS570_EFUSE_EFC_ST_SIG_Signature_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_EFUSE_EFC_ST_SIG_Signature_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_EFUSE */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
+239
View File
@@ -0,0 +1,239 @@
/* The header file is generated by make_header.py from EMAC.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_EMAC
#define LIBBSP_ARM_tms570_EMAC
#include <bsp/utility.h>
typedef struct{
uint32_t REVID; /*MDIO Revision ID Register*/
uint32_t CONTROL; /*MDIO Control Register*/
uint32_t ALIVE; /*PHY Alive Status register*/
uint32_t LINK; /*PHY Link Status Register*/
uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/
uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/
uint8_t reserved1 [8];
uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/
uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/
uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/
uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/
uint8_t reserved2 [80];
uint32_t USERACCESS0; /*MDIO User Access Register 0*/
uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/
uint32_t USERACCESS1; /*MDIO User Access Register 1*/
uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/
} tms570_emac_t;
/*----------------------TMS570_EMACREVID----------------------*/
/* field: REV - Identifies the MDIO Module revision. */
#define TMS570_EMAC_REVID_REV(val) BSP_FLD32(val,0, 31)
#define TMS570_EMAC_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_EMAC_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_EMACCONTROL---------------------*/
/* field: IDLE - State machine IDLE status bit. */
#define TMS570_EMAC_CONTROL_IDLE BSP_FLD32(31)
/* field: ENABLE - State machine enable control bit. */
#define TMS570_EMAC_CONTROL_ENABLE BSP_FLD32(30)
/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28)
#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: PREAMBLE - Preamble disable */
#define TMS570_EMAC_CONTROL_PREAMBLE BSP_FLD32(20)
/* field: FAULT - Fault indicator. */
#define TMS570_EMAC_CONTROL_FAULT BSP_FLD32(19)
/* field: FAULTENB - Fault detect enable. */
#define TMS570_EMAC_CONTROL_FAULTENB BSP_FLD32(18)
/* field: CLKDIV - Clock Divider bits. */
#define TMS570_EMAC_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
#define TMS570_EMAC_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMAC_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*----------------------TMS570_EMACALIVE----------------------*/
/* field: ALIVE - MDIO Alive bits. */
#define TMS570_EMAC_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
#define TMS570_EMAC_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_EMAC_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_EMACLINK----------------------*/
/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
#define TMS570_EMAC_LINK_LINK(val) BSP_FLD32(val,0, 31)
#define TMS570_EMAC_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_EMAC_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_EMACLINKINTRAW-------------------*/
/* field: USERPHY1 - MDIO Link change event, raw value. */
#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_FLD32(1)
/* field: USERPHY0 - MDIO Link change event, raw value. */
#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_FLD32(0)
/*------------------TMS570_EMACLINKINTMASKED------------------*/
/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
/*-------------------TMS570_EMACUSERINTRAW-------------------*/
/* field: USERACCESS1 - MDIO User command complete event bit. */
#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - MDIO User command complete event bit. */
#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_FLD32(0)
/*------------------TMS570_EMACUSERINTMASKED------------------*/
/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
/*-----------------TMS570_EMACUSERINTMASKSET-----------------*/
/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
/*----------------TMS570_EMACUSERINTMASKCLEAR----------------*/
/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
/*-------------------TMS570_EMACUSERACCESS0-------------------*/
/* field: GO - Go bit. */
#define TMS570_EMAC_USERACCESS0_GO BSP_FLD32(31)
/* field: WRITE - Write enable bit. */
#define TMS570_EMAC_USERACCESS0_WRITE BSP_FLD32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
#define TMS570_EMAC_USERACCESS0_ACK BSP_FLD32(29)
/* field: REGADR - Register address bits. */
#define TMS570_EMAC_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
#define TMS570_EMAC_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
#define TMS570_EMAC_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
#define TMS570_EMAC_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20)
#define TMS570_EMAC_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
#define TMS570_EMAC_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
/* field: DATA - User data bits. */
#define TMS570_EMAC_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15)
#define TMS570_EMAC_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMAC_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_EMACUSERPHYSEL0-------------------*/
/* field: LINKSEL - Link status determination select bit. */
#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_FLD32(7)
/* field: LINKINTENB - Link change interrupt enable. */
#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_EMAC_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*-------------------TMS570_EMACUSERACCESS1-------------------*/
/* field: GO - Go bit. */
#define TMS570_EMAC_USERACCESS1_GO BSP_FLD32(31)
/* field: WRITE - Write enable bit. */
#define TMS570_EMAC_USERACCESS1_WRITE BSP_FLD32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
#define TMS570_EMAC_USERACCESS1_ACK BSP_FLD32(29)
/* field: REGADR - Register address bits. */
#define TMS570_EMAC_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
#define TMS570_EMAC_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
#define TMS570_EMAC_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
#define TMS570_EMAC_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20)
#define TMS570_EMAC_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
#define TMS570_EMAC_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
/* field: DATA - User data bits. */
#define TMS570_EMAC_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15)
#define TMS570_EMAC_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMAC_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_EMACUSERPHYSEL1-------------------*/
/* field: LINKSEL - Link status determination select bit. */
#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_FLD32(7)
/* field: LINKINTENB - Link change interrupt enable. */
#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_EMAC_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
#endif /* LIBBSP_ARM_tms570_EMAC */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
+922
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
+471
View File
@@ -0,0 +1,471 @@
/* The header file is generated by make_header.py from EMIF.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_EMIF
#define LIBBSP_ARM_tms570_EMIF
#include <bsp/utility.h>
typedef struct{
uint32_t MIDR; /*Module ID Register*/
uint32_t AWCC; /*Asynchronous Wait Cycle Configuration Register*/
uint32_t SDCR; /*SDRAM Configuration Register*/
uint32_t SDRCR; /*SDRAM Refresh Control Register*/
uint32_t CE2CFG; /*Asynchronous 1 Configuration Register*/
uint32_t CE3CFG; /*Asynchronous 2 Configuration Register*/
uint32_t CE4CFG; /*Asynchronous 3 Configuration Register*/
uint32_t CE5CFG; /*Asynchronous 4 Configuration Register*/
uint32_t SDTIMR; /*SDRAM Timing Register*/
uint8_t reserved1 [24];
uint32_t SDSRETR; /*SDRAM Self Refresh Exit Timing Register*/
uint32_t INTRAW; /*EMIF Interrupt Raw Register*/
uint32_t INTMSK; /*EMIF Interrupt Mask Register*/
uint32_t INTMSKSET; /*EMIF Interrupt Mask Set Register*/
uint32_t INTMSKCLR; /*EMIF Interrupt Mask Clear Register*/
uint8_t reserved2 [24];
uint32_t PMCR; /*Page Mode Control Register*/
} tms570_emif_t;
/*----------------------TMS570_EMIFMIDR----------------------*/
/* field: REV - Module ID of EMIF. See the device-specific data manual. */
#define TMS570_EMIF_MIDR_REV(val) BSP_FLD32(val,0, 31)
#define TMS570_EMIF_MIDR_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_EMIF_MIDR_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_EMIFAWCC----------------------*/
/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
#define TMS570_EMIF_AWCC_WP1 BSP_FLD32(29)
/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
#define TMS570_EMIF_AWCC_WP0 BSP_FLD32(28)
/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
#define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23)
#define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23)
/* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */
#define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21)
#define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21)
#define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21)
/* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */
#define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19)
#define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19)
#define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19)
/* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */
#define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17)
#define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17)
#define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
/* field: MAX_EXT_WAIT - Maximum extended wait cycles. */
#define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7)
#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_EMIFSDCR----------------------*/
/* field: SR - Self-Refresh mode bit. */
#define TMS570_EMIF_SDCR_SR BSP_FLD32(31)
/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
#define TMS570_EMIF_SDCR_PD BSP_FLD32(30)
/* field: PDWR - Perform refreshes during power down. */
#define TMS570_EMIF_SDCR_PDWR BSP_FLD32(29)
/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
#define TMS570_EMIF_SDCR_NM BSP_FLD32(14)
/* field: CL - CAS Latency. */
#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
#define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11)
#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_FLD32(8)
/* field: IBANK - Internal SDRAM Bank size. */
#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
#define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6)
#define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */
#define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2)
#define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*----------------------TMS570_EMIFSDRCR----------------------*/
/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
/*---------------------TMS570_EMIFCE2CFG---------------------*/
/* field: SS - Select Strobe bit. */
#define TMS570_EMIF_CE2CFG_SS BSP_FLD32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
#define TMS570_EMIF_CE2CFG_EW BSP_FLD32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
#define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
#define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
#define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
#define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
#define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
#define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
#define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
#define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
#define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
#define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
#define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
#define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TA - Minimum Turn-Around time. */
#define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3)
#define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
#define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
#define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1)
#define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_EMIFCE3CFG---------------------*/
/* field: SS - Select Strobe bit. */
#define TMS570_EMIF_CE3CFG_SS BSP_FLD32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
#define TMS570_EMIF_CE3CFG_EW BSP_FLD32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
#define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
#define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
#define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
#define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
#define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
#define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
#define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
#define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
#define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
#define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
#define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
#define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TA - Minimum Turn-Around time. */
#define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3)
#define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
#define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
#define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1)
#define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_EMIFCE4CFG---------------------*/
/* field: SS - Select Strobe bit. */
#define TMS570_EMIF_CE4CFG_SS BSP_FLD32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
#define TMS570_EMIF_CE4CFG_EW BSP_FLD32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
#define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
#define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
#define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
#define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
#define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
#define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
#define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
#define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
#define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
#define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
#define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
#define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TA - Minimum Turn-Around time. */
#define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3)
#define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
#define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
#define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1)
#define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_EMIFCE5CFG---------------------*/
/* field: SS - Select Strobe bit. */
#define TMS570_EMIF_CE5CFG_SS BSP_FLD32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
#define TMS570_EMIF_CE5CFG_EW BSP_FLD32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
#define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
#define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
#define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
#define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
#define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
#define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
#define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
#define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
#define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
#define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
#define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
#define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3)
#define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
#define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
#define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1)
#define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_EMIFSDTIMR---------------------*/
/* field: T_RFC - Specifies the Trfc value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
#define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31)
/* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */
#define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26)
#define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26)
#define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
/* field: T_RCD - Specifies the Trcd value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22)
#define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22)
#define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
/* field: T_WR - Specifies the Twr value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18)
#define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18)
#define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
/* field: T_RAS - Specifies the Tras value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15)
#define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15)
#define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
/* field: T_RC - Specifies the Trc value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11)
#define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: T_RRD - Specifies the Trrd value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6)
#define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6)
#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/*---------------------TMS570_EMIFSDSRETR---------------------*/
/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*---------------------TMS570_EMIFINTRAW---------------------*/
/* field: WR - Wait Rise. */
#define TMS570_EMIF_INTRAW_WR BSP_FLD32(2)
/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
#define TMS570_EMIF_INTRAW_LT BSP_FLD32(1)
/* field: AT - Asynchronous Timeout. */
#define TMS570_EMIF_INTRAW_AT BSP_FLD32(0)
/*---------------------TMS570_EMIFINTMSK---------------------*/
/* field: WR_MASKED - Wait Rise Masked. */
#define TMS570_EMIF_INTMSK_WR_MASKED BSP_FLD32(2)
/* field: LT_MASKED - Masked Line Trap. */
#define TMS570_EMIF_INTMSK_LT_MASKED BSP_FLD32(1)
/* field: AT_MASKED - Asynchronous Timeout Masked. */
#define TMS570_EMIF_INTMSK_AT_MASKED BSP_FLD32(0)
/*--------------------TMS570_EMIFINTMSKSET--------------------*/
/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_FLD32(2)
/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_FLD32(1)
/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_FLD32(0)
/*--------------------TMS570_EMIFINTMSKCLR--------------------*/
/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_FLD32(2)
/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_FLD32(1)
/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_FLD32(0)
/*----------------------TMS570_EMIFPMCR----------------------*/
/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_FLD32(25)
/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_FLD32(24)
/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
#define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23)
#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_FLD32(17)
/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_FLD32(16)
/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
#define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15)
#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_FLD32(9)
/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_FLD32(8)
/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
#define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7)
#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_FLD32(1)
/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_EMIF */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
+215
View File
@@ -0,0 +1,215 @@
/* The header file is generated by make_header.py from ESM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_ESM
#define LIBBSP_ARM_tms570_ESM
#include <bsp/utility.h>
typedef struct{
uint32_t EEPAPR1; /*ESM Enable ERROR Pin Action/Response Register 1*/
uint32_t DEPAPR1; /*ESM Disable ERROR Pin Action/Response Register 1*/
uint32_t IESR1; /*ESM Interrupt Enable Set/Status Register 1*/
uint32_t IECR1; /*ESM Interrupt Enable Clear/Status Register 1*/
uint32_t ILSR1; /*Interrupt Level Set/Status Register 1*/
uint32_t ILCR1; /*Interrupt Level Clear/Status Register 1*/
uint32_t SR[3]; /*ESM Status Register*/
uint32_t EPSR; /*ESM ERROR Pin Status Register*/
uint32_t IOFFHR; /*ESM Interrupt Offset High Register*/
uint32_t IOFFLR; /*ESM Interrupt Offset Low Register*/
uint32_t LTCR; /*ESM Low-Time Counter Register*/
uint32_t LTCPR; /*ESM Low-Time Counter Preload Register*/
uint32_t EKR; /*ESM Error Key Register*/
uint32_t SSR2; /*ESM Status Shadow Register 2*/
uint32_t IEPSR4; /*ESM Influence ERROR Pin Set/Status Register 4*/
uint32_t IEPCR4; /*ESM Influence ERROR Pin Clear/Status Register 4*/
uint32_t IESR4; /*ESM Interrupt Enable Set/Status Register 4*/
uint32_t IECR4; /*ESM Interrupt Enable Clear/Status Register 4*/
uint32_t ILSR4; /*Interrupt Level Set/Status Register 4*/
uint32_t ILCR4; /*Interrupt Level Clear/Status Register 4*/
uint32_t SR4; /*ESM Status Register 4*/
} tms570_esm_t;
/*---------------------TMS570_ESMEEPAPR1---------------------*/
/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */
#define TMS570_ESM_EEPAPR1_IEPSET(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_EEPAPR1_IEPSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_EEPAPR1_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_ESMDEPAPR1---------------------*/
/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
#define TMS570_ESM_DEPAPR1_IEPCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_DEPAPR1_IEPCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_DEPAPR1_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_ESMIESR1----------------------*/
/* field: INTENSET - Set interrupt Enable */
#define TMS570_ESM_IESR1_INTENSET(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_IESR1_INTENSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_IESR1_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_ESMIECR1----------------------*/
/* field: INTENCLR - Clear Interrupt Enable */
#define TMS570_ESM_IECR1_INTENCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_IECR1_INTENCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_IECR1_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_ESMILSR1----------------------*/
/* field: INTLVLSET - Set Interrupt Priority */
#define TMS570_ESM_ILSR1_INTLVLSET(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_ILSR1_INTLVLSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_ILSR1_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_ESMILCR1----------------------*/
/* field: INTLVLCLR - Clear Interrupt Priority. */
#define TMS570_ESM_ILCR1_INTLVLCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_ILCR1_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_ILCR1_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------------TMS570_ESMSR------------------------*/
/* field: ESF - Error Status Flag. Provides status information on a pending error. */
#define TMS570_ESM_SR_ESF(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_SR_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_SR_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_ESMEPSR-----------------------*/
/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
#define TMS570_ESM_EPSR_EPSF BSP_FLD32(0)
/*----------------------TMS570_ESMIOFFHR----------------------*/
/* field: INTOFFH - Offset High Level Interrupt. */
#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6)
#define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
/*----------------------TMS570_ESMIOFFLR----------------------*/
/* field: INTOFFL - Offset Low Level Interrupt. */
#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6)
#define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
/*-----------------------TMS570_ESMLTCR-----------------------*/
/* field: LTC - ERROR Pin Low-Time Counter */
#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15)
#define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*----------------------TMS570_ESMLTCPR----------------------*/
/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */
#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15)
#define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_ESMEKR-----------------------*/
/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */
#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3)
#define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-----------------------TMS570_ESMSSR2-----------------------*/
/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */
#define TMS570_ESM_SSR2_ESF(val) BSP_FLD32(val,0, 31)
#define TMS570_ESM_SSR2_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_ESM_SSR2_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_ESMIEPSR4----------------------*/
/* field: IEPSET - Set Influence on ERROR Pin */
#define TMS570_ESM_IEPSR4_IEPSET(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_IEPSR4_IEPSET_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_IEPSR4_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
/*----------------------TMS570_ESMIEPCR4----------------------*/
/* field: IEPCLR - Clear Influence on ERROR Pin */
#define TMS570_ESM_IEPCR4_IEPCLR(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_IEPCR4_IEPCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_IEPCR4_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
/*----------------------TMS570_ESMIESR4----------------------*/
/* field: INTENSET - Set Interrupt Enable */
#define TMS570_ESM_IESR4_INTENSET(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_IESR4_INTENSET_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_IESR4_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
/*----------------------TMS570_ESMIECR4----------------------*/
/* field: INTENCLR - Clear Interrupt Enable */
#define TMS570_ESM_IECR4_INTENCLR(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_IECR4_INTENCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_IECR4_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
/*----------------------TMS570_ESMILSR4----------------------*/
/* field: INTLVLSET - Set Interrupt Level */
#define TMS570_ESM_ILSR4_INTLVLSET(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_ILSR4_INTLVLSET_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_ILSR4_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
/*----------------------TMS570_ESMILCR4----------------------*/
/* field: INTLVLCLR - Clear Interrupt Level */
#define TMS570_ESM_ILCR4_INTLVLCLR(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_ILCR4_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_ILCR4_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
/*-----------------------TMS570_ESMSR4-----------------------*/
/* field: ESF - Error Status Flag. Provides status information on a pending error. */
#define TMS570_ESM_SR4_ESF(val) BSP_FLD32(val,32, 63)
#define TMS570_ESM_SR4_ESF_GET(reg) BSP_FLD32GET(reg,32, 63)
#define TMS570_ESM_SR4_ESF_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
#endif /* LIBBSP_ARM_tms570_ESM */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
+687
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
+801
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
+324
View File
@@ -0,0 +1,324 @@
/* The header file is generated by make_header.py from GIO.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_GIO
#define LIBBSP_ARM_tms570_GIO
#include <bsp/utility.h>
typedef struct{
uint32_t DIR; /*GIO Data Direction Register*/
uint32_t DIN; /*GIO Data Input Register*/
uint32_t DOUT; /*GIO Data Output Register*/
uint32_t DSET; /*GIO Data Set Register*/
uint32_t DCLR; /*GIO Data Clear Register*/
uint32_t PDR; /*GIO Open Drain Register*/
uint32_t PULDIS; /*GIO Pull Disable Register*/
uint32_t PSL; /*GIO Pull Select Register*/
} tms570_gio_port_t;
typedef struct{
uint32_t GCR0; /*GIO Global Control Register*/
uint8_t reserved1 [4];
uint32_t INTDET; /*GIO Interrupt Detect Register*/
uint32_t POL; /*GIO Interrupt Polarity Register*/
uint32_t ENASET; /*GIO Interrupt Enable Set Register*/
uint32_t ENACLR; /*GIO Interrupt Enable Clear Register*/
uint32_t LVLSET; /*GIO Interrupt Priority Set Register*/
uint32_t LVLCLR; /*GIO Interrupt Priority Clear Register*/
uint32_t FLG; /*GIO Interrupt Flag Register*/
uint32_t OFF1; /*GIO Offset 1 Register*/
uint32_t OFF2; /*GIO Offset 2 Register*/
uint32_t EMU1; /*GIO Emulation 1 Register*/
uint32_t EMU2; /*GIO Emulation 2 Register*/
tms570_gio_port_t ports[8]; /*GIO ports*/
} tms570_gio_t;
/*-----------------------TMS570_GIODIR-----------------------*/
/* field: GIODIR - GIO data direction, pins [7:0] */
#define TMS570_GIO_DIR_GIODIR(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DIR_GIODIR_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DIR_GIODIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIODIN-----------------------*/
/* field: GIODIN - GIO data input, pins [7:0] */
#define TMS570_GIO_DIN_GIODIN(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DIN_GIODIN_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DIN_GIODIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIODOUT-----------------------*/
/* field: GIODOUT - IO data output, pins[7:0]. */
#define TMS570_GIO_DOUT_GIODOUT(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DOUT_GIODOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DOUT_GIODOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIODSET-----------------------*/
/* field: GIODSET - GIO data set, pins[7:0]. This bit drives the output of GIO pin high. */
#define TMS570_GIO_DSET_GIODSET(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DSET_GIODSET_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DSET_GIODSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIODCLR-----------------------*/
/* field: GIODCLR - GIO data clear, pins[7:0]. This bit drives the output of GIO pin low. */
#define TMS570_GIO_DCLR_GIODCLR(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DCLR_GIODCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DCLR_GIODCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIOPDR-----------------------*/
/* field: 7_0 - GIOPDRH GIO open drain, pins[7:0] */
#define TMS570_GIO_PDR_7_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_PDR_7_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_PDR_7_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_GIOPULDIS----------------------*/
/* field: GIOPULDIS - GIO pull disable, pins[7:0]. */
#define TMS570_GIO_PULDIS_GIOPULDIS(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_PULDIS_GIOPULDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_PULDIS_GIOPULDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIOPSL-----------------------*/
/* field: GIOPSL - GIO pull select, pins[7:0] */
#define TMS570_GIO_PSL_GIOPSL(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_PSL_GIOPSL_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_PSL_GIOPSL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIOGCR0-----------------------*/
/* field: RESET - GIO reset. */
#define TMS570_GIO_GCR0_RESET BSP_FLD32(0)
/*----------------------TMS570_GIOINTDET----------------------*/
/* field: GIOINTDET_3 - Interrupt detection select for pins GIOD[7:0] */
#define TMS570_GIO_INTDET_GIOINTDET_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_INTDET_GIOINTDET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_INTDET_GIOINTDET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOINTDET_2 - Interrupt detection select for pins GIOC[7:0] */
#define TMS570_GIO_INTDET_GIOINTDET_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_INTDET_GIOINTDET_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_INTDET_GIOINTDET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOINTDET_1 - Interrupt detection select for pins GIOB[7:0] */
#define TMS570_GIO_INTDET_GIOINTDET_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_INTDET_GIOINTDET_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_INTDET_GIOINTDET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOINTDET_0 - Interrupt detection select for pins GIOA[7:0] */
#define TMS570_GIO_INTDET_GIOINTDET_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_INTDET_GIOINTDET_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_INTDET_GIOINTDET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIOPOL-----------------------*/
/* field: GIOPOL_3 - Interrupt polarity select for pins GIOD[7:0] */
#define TMS570_GIO_POL_GIOPOL_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_POL_GIOPOL_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_POL_GIOPOL_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOPOL_2 - Interrupt polarity select for pins GIOC[7:0] */
#define TMS570_GIO_POL_GIOPOL_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_POL_GIOPOL_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_POL_GIOPOL_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOPOL_1 - Interrupt polarity select for pins GIOB[7:0] */
#define TMS570_GIO_POL_GIOPOL_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_POL_GIOPOL_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_POL_GIOPOL_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOPOL_0 - Interrupt polarity select for pins GIOA[7:0] */
#define TMS570_GIO_POL_GIOPOL_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_POL_GIOPOL_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_POL_GIOPOL_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_GIOENASET----------------------*/
/* field: GIOENASET_3 - nterrupt enable for pins GIOD[7:0] */
#define TMS570_GIO_ENASET_GIOENASET_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_ENASET_GIOENASET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_ENASET_GIOENASET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOENASET_2 - Interrupt enable for pins GIOC[7:0] */
#define TMS570_GIO_ENASET_GIOENASET_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_ENASET_GIOENASET_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_ENASET_GIOENASET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOENASET_1 - Interrupt enable for pins GIOB[7:0] */
#define TMS570_GIO_ENASET_GIOENASET_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_ENASET_GIOENASET_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_ENASET_GIOENASET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOENASET_0 - Interrupt enable for pins GIOA[7:0] */
#define TMS570_GIO_ENASET_GIOENASET_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_ENASET_GIOENASET_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_ENASET_GIOENASET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_GIOENACLR----------------------*/
/* field: GIOENACLR_3 - Interrupt enable for pins GIOD[7:0] */
#define TMS570_GIO_ENACLR_GIOENACLR_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_ENACLR_GIOENACLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_ENACLR_GIOENACLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOENACLR_2 - Interrupt enable for pins GIOC[7:0] */
#define TMS570_GIO_ENACLR_GIOENACLR_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_ENACLR_GIOENACLR_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_ENACLR_GIOENACLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOENACLR_1 - Interrupt enable for pins GIOB[7:0] */
#define TMS570_GIO_ENACLR_GIOENACLR_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_ENACLR_GIOENACLR_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_ENACLR_GIOENACLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOENACLR_0 - Interrupt enable for pins GIOA[7:0] */
#define TMS570_GIO_ENACLR_GIOENACLR_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_ENACLR_GIOENACLR_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_ENACLR_GIOENACLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_GIOLVLSET----------------------*/
/* field: GIOLVLSET_3 - GIO high priority interrupt for pins GIOD[7:0]. */
#define TMS570_GIO_LVLSET_GIOLVLSET_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_LVLSET_GIOLVLSET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_LVLSET_GIOLVLSET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOLVLSET_2 - GIO high priority interrupt for pins GIOC[7:0]. */
#define TMS570_GIO_LVLSET_GIOLVLSET_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_LVLSET_GIOLVLSET_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_LVLSET_GIOLVLSET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOLVLSET_1 - GIO high priority interrupt for pins GIOB[7:0]. */
#define TMS570_GIO_LVLSET_GIOLVLSET_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_LVLSET_GIOLVLSET_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_LVLSET_GIOLVLSET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOLVLSET_0 - GIO high priority interrupt for pins GIOA[7:0]. */
#define TMS570_GIO_LVLSET_GIOLVLSET_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_LVLSET_GIOLVLSET_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_LVLSET_GIOLVLSET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_GIOLVLCLR----------------------*/
/* field: GIOLVLCLR_3 - GIO low priority interrupt for pins GIOD[7:0] */
#define TMS570_GIO_LVLCLR_GIOLVLCLR_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOLVLCLR_2 - GIO low priority interrupt for pins GIOC[7:0] */
#define TMS570_GIO_LVLCLR_GIOLVLCLR_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOLVLCLR_1 - GIO low priority interrupt for pins GIOB[7:0] */
#define TMS570_GIO_LVLCLR_GIOLVLCLR_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOLVLCLR_0 - GIO low priority interrupt for pins GIOA[7:0] */
#define TMS570_GIO_LVLCLR_GIOLVLCLR_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIOFLG-----------------------*/
/* field: GIOFLG_3 - GIO flag for pins GIOD[7:0]. */
#define TMS570_GIO_FLG_GIOFLG_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_FLG_GIOFLG_3_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_GIO_FLG_GIOFLG_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: GIOFLG_2 - GIO flag for pins GIOC[7:0]. */
#define TMS570_GIO_FLG_GIOFLG_2(val) BSP_FLD32(val,16, 23)
#define TMS570_GIO_FLG_GIOFLG_2_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_GIO_FLG_GIOFLG_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: GIOFLG_1 - GIO flag for pins GIOB[7:0]. */
#define TMS570_GIO_FLG_GIOFLG_1(val) BSP_FLD32(val,8, 15)
#define TMS570_GIO_FLG_GIOFLG_1_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_GIO_FLG_GIOFLG_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: GIOFLG_0 - GIO flag for pins GIOA[7:0]. */
#define TMS570_GIO_FLG_GIOFLG_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_FLG_GIOFLG_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_FLG_GIOFLG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_GIOOFF1-----------------------*/
/* field: GIOOFF1 - GIO offset 1. These bits index the currently pending high-priority interrupt. */
#define TMS570_GIO_OFF1_GIOOFF1(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_OFF1_GIOOFF1_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_OFF1_GIOOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*-----------------------TMS570_GIOOFF2-----------------------*/
/* field: GIOOFF2 - GIO offset 2. These bits index the currently pending low-priority interrupt. */
#define TMS570_GIO_OFF2_GIOOFF2(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_OFF2_GIOOFF2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_OFF2_GIOOFF2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*-----------------------TMS570_GIOEMU1-----------------------*/
/* field: GIOEMU1 - GIO offset emulation 1. These bits index the currently pending high-priority interrupt. */
#define TMS570_GIO_EMU1_GIOEMU1(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_EMU1_GIOEMU1_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_EMU1_GIOEMU1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*-----------------------TMS570_GIOEMU2-----------------------*/
/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
#define TMS570_GIO_EMU2_GIOEMU2(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_EMU2_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_EMU2_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*----------------------TMS570_GIOports----------------------*/
/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
#define TMS570_GIO_ports_GIOEMU2(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_ports_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_ports_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
#endif /* LIBBSP_ARM_tms570_GIO */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
+351
View File
@@ -0,0 +1,351 @@
/* The header file is generated by make_header.py from HTU.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_HTU
#define LIBBSP_ARM_tms570_HTU
#include <bsp/utility.h>
typedef struct{
uint32_t GC; /*Global Control Register*/
uint32_t CPENA; /*Control Packet Enable Register*/
uint32_t BUSY0; /*Control Packet Busy Register 0*/
uint32_t BUSY1; /*Control Packet Busy Register 1*/
uint32_t BUSY2; /*Control Packet Busy Register 2*/
uint32_t BUSY3; /*Control Packet Busy Register 3*/
uint32_t ACPE; /*Active Control Packet and Error Register*/
uint8_t reserved1 [4];
uint32_t RLBECTRL; /*Request Lost and Bus Error Control Register*/
uint32_t BFINTS; /*Buffer Full Interrupt Enable Set Register*/
uint32_t BFINTC; /*Buffer Full Interrupt Enable Clear Register*/
uint8_t reserved2 [8];
uint32_t INTOFF0; /*Interrupt Offset Register 0*/
uint32_t INTOFF1; /*Interrupt Offset Register 1*/
uint32_t BIM; /*Buffer Initialization Mode Register*/
uint32_t RLOSTFL; /*Request Lost Flag Register*/
uint32_t BFINTFL; /*Buffer Full Interrupt Flag Register*/
uint32_t BERINTFL; /*BER Interrupt Flag Register*/
uint32_t MP1S; /*Memory Protection 1 Start Address Register*/
uint32_t MP1E; /*Memory Protection 1 End Address Register*/
uint32_t DCTRL; /*Debug Control Register*/
uint32_t WPR; /*Watch Point Register*/
uint32_t WMR; /*Watch Mask Register*/
uint32_t ID; /*Module Identification Register*/
uint32_t PCR; /*Parity Control Register*/
uint32_t PAR; /*Parity Address Register*/
uint8_t reserved3 [4];
uint32_t MPCS; /*Memory Protection Control and Status Register*/
uint32_t MP0S; /*Memory Protection 0 Start Address Register*/
uint32_t MP0E; /*Memory Protection 0 End Address Register*/
} tms570_htu_t;
/*------------------------TMS570_HTUGC------------------------*/
/* field: VBUSHOLD - Hold the VBUS bus */
#define TMS570_HTU_GC_VBUSHOLD BSP_FLD32(24)
/* field: HTUEN - Transfer Unit Enable Bit */
#define TMS570_HTU_GC_HTUEN BSP_FLD32(16)
/* field: DEBM - Debug Mode */
#define TMS570_HTU_GC_DEBM BSP_FLD32(8)
/* field: HTURES - HTU Software Reset Request */
#define TMS570_HTU_GC_HTURES BSP_FLD32(0)
/*----------------------TMS570_HTUCPENA----------------------*/
/* field: CPENA - CP Enable Bits */
#define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*----------------------TMS570_HTUBUSY0----------------------*/
/* field: BUSY0A - Busy Flag for CP A of DCP 0 */
#define TMS570_HTU_BUSY0_BUSY0A BSP_FLD32(24)
/* field: BUSY0B - Busy Flag for CP B of DCP 0 */
#define TMS570_HTU_BUSY0_BUSY0B BSP_FLD32(16)
/* field: BUSY1A - Busy Flag for CP A of DCP 1 */
#define TMS570_HTU_BUSY0_BUSY1A BSP_FLD32(8)
/* field: BUSY1B - Busy Flag for CP B of DCP 1 */
#define TMS570_HTU_BUSY0_BUSY1B BSP_FLD32(0)
/*----------------------TMS570_HTUBUSY1----------------------*/
/* field: BUSY2A - Busy Flag for CP A of DCP 2 */
#define TMS570_HTU_BUSY1_BUSY2A BSP_FLD32(24)
/* field: BUSY2B - Busy Flag for CP B of DCP 2 */
#define TMS570_HTU_BUSY1_BUSY2B BSP_FLD32(16)
/* field: BUSY3A - Busy Flag for CP A of DCP 3 */
#define TMS570_HTU_BUSY1_BUSY3A BSP_FLD32(8)
/* field: BUSY3B - Busy Flag for CP B of DCP 3 */
#define TMS570_HTU_BUSY1_BUSY3B BSP_FLD32(0)
/*----------------------TMS570_HTUBUSY2----------------------*/
/* field: BUSY4A - Busy Flag for CP A of DCP 4 */
#define TMS570_HTU_BUSY2_BUSY4A BSP_FLD32(24)
/* field: BUSY4B - Busy Flag for CP B of DCP 4 */
#define TMS570_HTU_BUSY2_BUSY4B BSP_FLD32(16)
/* field: BUSY5A - Busy Flag for CP A of DCP 5 */
#define TMS570_HTU_BUSY2_BUSY5A BSP_FLD32(8)
/* field: BUSY5B - Busy Flag for CP B of DCP 5 */
#define TMS570_HTU_BUSY2_BUSY5B BSP_FLD32(0)
/*----------------------TMS570_HTUBUSY3----------------------*/
/* field: BUSY6A - Busy Flag for CP A of DCP 6 */
#define TMS570_HTU_BUSY3_BUSY6A BSP_FLD32(24)
/* field: BUSY6B - Busy Flag for CP B of DCP 6 */
#define TMS570_HTU_BUSY3_BUSY6B BSP_FLD32(16)
/* field: BUSY7A - Busy Flag for CP A of DCP 7 */
#define TMS570_HTU_BUSY3_BUSY7A BSP_FLD32(8)
/* field: BUSY7B - Busy Flag for CP B of DCP 7 */
#define TMS570_HTU_BUSY3_BUSY7B BSP_FLD32(0)
/*-----------------------TMS570_HTUACPE-----------------------*/
/* field: ERRF - Error Flag */
#define TMS570_HTU_ACPE_ERRF BSP_FLD32(31)
/*---------------------TMS570_HTURLBECTRL---------------------*/
/* field: BERINTENA - Bus Error Interrupt Enable Bit */
#define TMS570_HTU_RLBECTRL_BERINTENA BSP_FLD32(16)
/* field: CORL - Continue On Request Lost Error */
#define TMS570_HTU_RLBECTRL_CORL BSP_FLD32(8)
/* field: RLINTENA - Request Lost Interrupt Enable Bit */
#define TMS570_HTU_RLBECTRL_RLINTENA BSP_FLD32(0)
/*----------------------TMS570_HTUBFINTS----------------------*/
/* field: BFINTENA - Bus Full Interrupt Enable Bits. */
#define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*----------------------TMS570_HTUBFINTC----------------------*/
/* field: BFINTDIS - */
#define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_HTUINTOFF0---------------------*/
/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: CPOFF0 - CP Offset. */
#define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4)
#define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*---------------------TMS570_HTUINTOFF1---------------------*/
/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: CPOFF1 - CP Offset. */
#define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4)
#define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*-----------------------TMS570_HTUBIM-----------------------*/
/* field: BIM - Buffer Initialization Mode */
#define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7)
#define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*---------------------TMS570_HTURLOSTFL---------------------*/
/* field: CPRLFL - CP Request Lost Flags */
#define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_HTUBFINTFL---------------------*/
/* field: BFINTFL - Buffer Full Interrupt Flags */
#define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_HTUBERINTFL---------------------*/
/* field: BERINTFL - Bus Error Interrupt Flags */
#define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_HTUMP1S-----------------------*/
/* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */
#define TMS570_HTU_MP1S_STARTADDRESS1(val) BSP_FLD32(val,0, 31)
#define TMS570_HTU_MP1S_STARTADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_HTU_MP1S_STARTADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_HTUMP1E-----------------------*/
/* field: ENDADDRESS1 - The end address defines at which address the region ends. */
#define TMS570_HTU_MP1E_ENDADDRESS1(val) BSP_FLD32(val,0, 31)
#define TMS570_HTU_MP1E_ENDADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_HTU_MP1E_ENDADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_HTUDCTRL----------------------*/
/* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */
#define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27)
#define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: HTUDBGS - HTU Debug Status. */
#define TMS570_HTU_DCTRL_HTUDBGS BSP_FLD32(16)
/* field: DBREN - Debug Request Enable */
#define TMS570_HTU_DCTRL_DBREN BSP_FLD32(0)
/*-----------------------TMS570_HTUWPR-----------------------*/
/* field: WP - Watch Point Register */
#define TMS570_HTU_WPR_WP(val) BSP_FLD32(val,0, 31)
#define TMS570_HTU_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_HTU_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_HTUWMR-----------------------*/
/* field: WM - Watch Mask Register */
#define TMS570_HTU_WMR_WM(val) BSP_FLD32(val,0, 31)
#define TMS570_HTU_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_HTU_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------------TMS570_HTUID------------------------*/
/* field: CLASS - Module Class */
#define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23)
#define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: TYPE - Subtype within a Class */
#define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15)
#define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: REV - Module Revision Number */
#define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7)
#define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_HTUPCR-----------------------*/
/* field: COPE - Continue on Parity Error */
#define TMS570_HTU_PCR_COPE BSP_FLD32(16)
/* field: TEST - Test. */
#define TMS570_HTU_PCR_TEST BSP_FLD32(8)
/* field: PARITY_ENA - Enable/Disable Parity Checking. */
#define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
#define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-----------------------TMS570_HTUPAR-----------------------*/
/* field: PEFT - Parity Error Fault Flag. */
#define TMS570_HTU_PAR_PEFT BSP_FLD32(16)
/* field: PAOFF - PAOFF */
#define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8)
#define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
/*-----------------------TMS570_HTUMPCS-----------------------*/
/* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */
#define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27)
#define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: MPEFT1 - MPEFT1 */
#define TMS570_HTU_MPCS_MPEFT1 BSP_FLD32(17)
/* field: MPEFT0 - Memory Protection Error Fault Flag 0. */
#define TMS570_HTU_MPCS_MPEFT0 BSP_FLD32(16)
/* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */
#define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11)
#define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/*-----------------------TMS570_HTUMP0S-----------------------*/
/* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */
#define TMS570_HTU_MP0S_ISTARTADDRESS0(val) BSP_FLD32(val,0, 31)
#define TMS570_HTU_MP0S_ISTARTADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_HTU_MP0S_ISTARTADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_HTUMP0E-----------------------*/
/* field: ENDADDRESS0 - The end address defines at which address the region ends. */
#define TMS570_HTU_MP0E_ENDADDRESS0(val) BSP_FLD32(val,0, 31)
#define TMS570_HTU_MP0E_ENDADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_HTU_MP0E_ENDADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_HTU */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
+363
View File
@@ -0,0 +1,363 @@
/* The header file is generated by make_header.py from I2C.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_I2C
#define LIBBSP_ARM_tms570_I2C
#include <bsp/utility.h>
typedef struct{
uint32_t OAR; /*I2C Own Address Manager*/
uint32_t IMR; /*I2C Interupt Mask Register*/
uint32_t STR; /*I2C Status Register*/
uint32_t CKL; /*I2C Clock Divider Low Register*/
uint32_t CKH; /*I2C Clock Control High Register*/
uint32_t CNT; /*I2C Data Count Register*/
uint32_t DRR; /*I2C Data Receive Register*/
uint32_t SAR; /*I2C Slave Address Register*/
uint32_t DXR; /*I2C Data Transmit Register*/
uint32_t MDR; /*I2C Mode Register*/
uint32_t IVR; /*I2C Interrupt Vector Register*/
uint32_t EMDR; /*I2C Extended Mode Register*/
uint32_t PSC; /*I2C Prescale Register*/
uint32_t PID11; /*I2C Peripheral ID Register 1*/
uint32_t PID12; /*I2C Peripheral ID Register 2*/
uint32_t DMACR; /*I2C DMA Control Register*/
uint8_t reserved1 [8];
uint32_t PFNC; /*I2C Pin Function Register*/
uint32_t DIR; /*I2C Pin Direction Register*/
uint32_t DIN; /*I2C Data Input Register*/
uint32_t DOUT; /*I2C Data Output Register*/
uint32_t SET; /*I2C Data Set Register*/
uint32_t CLR; /*I2C Data Clear Register*/
uint32_t PDR; /*I2C Pin Open Drain Register*/
uint32_t PDIS; /*I2C Pull Disable Register*/
uint32_t PSEL; /*I2C Pull Select Register*/
uint32_t pSRS; /*I2C Pins Slew Rate Select Register*/
} tms570_i2c_t;
/*-----------------------TMS570_I2COAR-----------------------*/
/* field: OA - Own address */
#define TMS570_I2C_OAR_OA(val) BSP_FLD32(val,0, 9)
#define TMS570_I2C_OAR_OA_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_I2C_OAR_OA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
/*-----------------------TMS570_I2CIMR-----------------------*/
/* field: AASEN - Address As Slave Interrupt Enable */
#define TMS570_I2C_IMR_AASEN BSP_FLD32(6)
/* field: SCDEN - Stop Condition Interrupt Enable */
#define TMS570_I2C_IMR_SCDEN BSP_FLD32(5)
/* field: TXRDYEN - Transmit Data Ready Interrupt Enable */
#define TMS570_I2C_IMR_TXRDYEN BSP_FLD32(4)
/* field: RXRDYEN - Receive Data Ready Interrupt Enable */
#define TMS570_I2C_IMR_RXRDYEN BSP_FLD32(3)
/* field: ARDYEN - Register Access Ready Interrupt Enable */
#define TMS570_I2C_IMR_ARDYEN BSP_FLD32(2)
/* field: NACKEN - No Acknowledgement Interrupt Enable */
#define TMS570_I2C_IMR_NACKEN BSP_FLD32(1)
/* field: ALEN - Arbitration Lost Interrupt Enable */
#define TMS570_I2C_IMR_ALEN BSP_FLD32(0)
/*-----------------------TMS570_I2CSTR-----------------------*/
/* field: SDIR - Slave direction */
#define TMS570_I2C_STR_SDIR BSP_FLD32(14)
/* field: NACKSNT - No acknowledge sent */
#define TMS570_I2C_STR_NACKSNT BSP_FLD32(13)
/* field: BB - Bus busy */
#define TMS570_I2C_STR_BB BSP_FLD32(12)
/* field: RSFULL - Receiver shift full */
#define TMS570_I2C_STR_RSFULL BSP_FLD32(11)
/* field: XSMT - XSMT */
#define TMS570_I2C_STR_XSMT BSP_FLD32(10)
/* field: AAS - Address as slave */
#define TMS570_I2C_STR_AAS BSP_FLD32(9)
/* field: AD0 - Address zero status */
#define TMS570_I2C_STR_AD0 BSP_FLD32(8)
/* field: SCD - SCD */
#define TMS570_I2C_STR_SCD BSP_FLD32(5)
/* field: TXRDY - Transmit data ready interrupt flag */
#define TMS570_I2C_STR_TXRDY BSP_FLD32(4)
/* field: RXRDY - Receive data ready interrupt flag */
#define TMS570_I2C_STR_RXRDY BSP_FLD32(3)
/* field: ARDY - Register access ready interrupt flag */
#define TMS570_I2C_STR_ARDY BSP_FLD32(2)
/* field: NACK - No acknowledgement interrupt */
#define TMS570_I2C_STR_NACK BSP_FLD32(1)
/* field: AL - Arbitration lost interrupt flag */
#define TMS570_I2C_STR_AL BSP_FLD32(0)
/*-----------------------TMS570_I2CCKL-----------------------*/
/* field: CLKL - Low time clock division factor */
#define TMS570_I2C_CKL_CLKL(val) BSP_FLD32(val,0, 15)
#define TMS570_I2C_CKL_CLKL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_I2C_CKL_CLKL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_I2CCKH-----------------------*/
/* field: CLKH - High time clock division factor */
#define TMS570_I2C_CKH_CLKH(val) BSP_FLD32(val,0, 15)
#define TMS570_I2C_CKH_CLKH_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_I2C_CKH_CLKH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_I2CCNT-----------------------*/
/* field: CNT - Data counter */
#define TMS570_I2C_CNT_CNT(val) BSP_FLD32(val,0, 15)
#define TMS570_I2C_CNT_CNT_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_I2C_CNT_CNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_I2CDRR-----------------------*/
/* field: DATARX - Receive data */
#define TMS570_I2C_DRR_DATARX(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_DRR_DATARX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_DRR_DATARX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_I2CSAR-----------------------*/
/* field: SA - 7- or 10-bit programmable slave address */
#define TMS570_I2C_SAR_SA(val) BSP_FLD32(val,0, 9)
#define TMS570_I2C_SAR_SA_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_I2C_SAR_SA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
/*-----------------------TMS570_I2CDXR-----------------------*/
/* field: DATATX - Transmit data */
#define TMS570_I2C_DXR_DATATX(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_DXR_DATATX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_DXR_DATATX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_I2CMDR-----------------------*/
/* field: NACKMOD - No-acknowledge (NACK) mode */
#define TMS570_I2C_MDR_NACKMOD BSP_FLD32(15)
/* field: FREE - Free running bit */
#define TMS570_I2C_MDR_FREE BSP_FLD32(14)
/* field: STT - Start condition */
#define TMS570_I2C_MDR_STT BSP_FLD32(13)
/* field: STP - Stop condition */
#define TMS570_I2C_MDR_STP BSP_FLD32(11)
/* field: MST - Master/slave mode bit */
#define TMS570_I2C_MDR_MST BSP_FLD32(10)
/* field: TRX - Transmit/receive bit */
#define TMS570_I2C_MDR_TRX BSP_FLD32(9)
/* field: XA - Expand address enable bit */
#define TMS570_I2C_MDR_XA BSP_FLD32(8)
/* field: RM - RM */
#define TMS570_I2C_MDR_RM BSP_FLD32(7)
/* field: DLB - Digital loop back enable bit */
#define TMS570_I2C_MDR_DLB BSP_FLD32(6)
/* field: nIRS - I2C reset enable bit */
#define TMS570_I2C_MDR_nIRS BSP_FLD32(5)
/* field: STB - Start byte mode enable bit (Master mode only) */
#define TMS570_I2C_MDR_STB BSP_FLD32(4)
/* field: FDF - Free data format enable bit */
#define TMS570_I2C_MDR_FDF BSP_FLD32(3)
/* field: BC - Bit count */
#define TMS570_I2C_MDR_BC(val) BSP_FLD32(val,0, 2)
#define TMS570_I2C_MDR_BC_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_I2C_MDR_BC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*-----------------------TMS570_I2CIVR-----------------------*/
/* field: TESTMD - Reserved for internal testing. */
#define TMS570_I2C_IVR_TESTMD(val) BSP_FLD32(val,8, 11)
#define TMS570_I2C_IVR_TESTMD_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_I2C_IVR_TESTMD_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: INTCODE - Interrupt Code Bits */
#define TMS570_I2C_IVR_INTCODE(val) BSP_FLD32(val,0, 2)
#define TMS570_I2C_IVR_INTCODE_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_I2C_IVR_INTCODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*-----------------------TMS570_I2CEMDR-----------------------*/
/* field: IGNACK - Ignore NACK mode */
#define TMS570_I2C_EMDR_IGNACK BSP_FLD32(1)
/* field: BCM - Backwards compatibility mode */
#define TMS570_I2C_EMDR_BCM BSP_FLD32(0)
/*-----------------------TMS570_I2CPSC-----------------------*/
/* field: PSC - Prescale */
#define TMS570_I2C_PSC_PSC(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_PSC_PSC_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_PSC_PSC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_I2CPID11----------------------*/
/* field: CLASS - Peripheral class */
#define TMS570_I2C_PID11_CLASS(val) BSP_FLD32(val,8, 15)
#define TMS570_I2C_PID11_CLASS_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_I2C_PID11_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: REVISION - Revision level of the I2C */
#define TMS570_I2C_PID11_REVISION(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_PID11_REVISION_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_PID11_REVISION_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_I2CPID12----------------------*/
/* field: TYPE - Peripheral type */
#define TMS570_I2C_PID12_TYPE(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_PID12_TYPE_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_PID12_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_I2CDMACR----------------------*/
/* field: TXDMAEN - Transmitter DMA enable */
#define TMS570_I2C_DMACR_TXDMAEN BSP_FLD32(1)
/* field: RXDMAEN - Receive DMA enable */
#define TMS570_I2C_DMACR_RXDMAEN BSP_FLD32(0)
/*-----------------------TMS570_I2CPFNC-----------------------*/
/* field: PINFUNC - SDA and SCL Pin Function */
#define TMS570_I2C_PFNC_PINFUNC BSP_FLD32(0)
/*-----------------------TMS570_I2CDIR-----------------------*/
/* field: SDADIR - SDA direction */
#define TMS570_I2C_DIR_SDADIR BSP_FLD32(1)
/* field: SCLDIR - SCL direction */
#define TMS570_I2C_DIR_SCLDIR BSP_FLD32(0)
/*-----------------------TMS570_I2CDIN-----------------------*/
/* field: SDAIN - Serial data in */
#define TMS570_I2C_DIN_SDAIN BSP_FLD32(1)
/* field: SCLIN - Serial clock data in */
#define TMS570_I2C_DIN_SCLIN BSP_FLD32(0)
/*-----------------------TMS570_I2CDOUT-----------------------*/
/* field: SDAOUT - SDA Data Output */
#define TMS570_I2C_DOUT_SDAOUT BSP_FLD32(1)
/* field: SCLOUT - SCL Data Output */
#define TMS570_I2C_DOUT_SCLOUT BSP_FLD32(0)
/*-----------------------TMS570_I2CSET-----------------------*/
/* field: SDASET - Serial Data Set */
#define TMS570_I2C_SET_SDASET BSP_FLD32(1)
/* field: SCLSET - Serial Clock Set */
#define TMS570_I2C_SET_SCLSET BSP_FLD32(0)
/*-----------------------TMS570_I2CCLR-----------------------*/
/* field: SDACLR - Serial Data Clear */
#define TMS570_I2C_CLR_SDACLR BSP_FLD32(1)
/* field: SCLCLR - Serial Clock Clear */
#define TMS570_I2C_CLR_SCLCLR BSP_FLD32(0)
/*-----------------------TMS570_I2CPDR-----------------------*/
/* field: SDAPDR - SDA pin open drain enable */
#define TMS570_I2C_PDR_SDAPDR BSP_FLD32(1)
/* field: SCLPDR - SCL pin open drain enable */
#define TMS570_I2C_PDR_SCLPDR BSP_FLD32(0)
/*-----------------------TMS570_I2CPDIS-----------------------*/
/* field: SDAPDIS - SDA pull disable */
#define TMS570_I2C_PDIS_SDAPDIS BSP_FLD32(1)
/* field: SCLPDIS - SCL pull disable */
#define TMS570_I2C_PDIS_SCLPDIS BSP_FLD32(0)
/*-----------------------TMS570_I2CPSEL-----------------------*/
/* field: SDAPSEL - SDA pull select */
#define TMS570_I2C_PSEL_SDAPSEL BSP_FLD32(1)
/* field: SCLPSEL - SCL pull select */
#define TMS570_I2C_PSEL_SCLPSEL BSP_FLD32(0)
/*-----------------------TMS570_I2CpSRS-----------------------*/
/* field: SDASRS - SDA Slew Rate select */
#define TMS570_I2C_pSRS_SDASRS BSP_FLD32(1)
/* field: SCLSRS - SCL Slew Rate select */
#define TMS570_I2C_pSRS_SCLSRS BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_I2C */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
+244
View File
@@ -0,0 +1,244 @@
/* The header file is generated by make_header.py from IOMM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_IOMM
#define LIBBSP_ARM_tms570_IOMM
#include <bsp/utility.h>
typedef struct{
uint32_t PINMMR0; /*Pin Multiplexing Control Register 0*/
uint32_t PINMMR1; /*Pin Multiplexing Control Register 1*/
uint32_t PINMMR2; /*Pin Multiplexing Control Register 2*/
uint32_t PINMMR3; /*Pin Multiplexing Control Register 3*/
uint32_t PINMMR4; /*Pin Multiplexing Control Register 4*/
uint32_t PINMMR5; /*Pin Multiplexing Control Register 5*/
uint32_t PINMMR6; /*Pin Multiplexing Control Register 6*/
uint32_t PINMMR7; /*Pin Multiplexing Control Register 7*/
uint32_t PINMMR8; /*Pin Multiplexing Control Register 8*/
uint32_t PINMMR9; /*Pin Multiplexing Control Register 9*/
uint32_t PINMMR10; /*Pin Multiplexing Control Register 10*/
uint32_t PINMMR11; /*Pin Multiplexing Control Register 11*/
uint32_t PINMMR12; /*Pin Multiplexing Control Register 12*/
uint32_t PINMMR13; /*Pin Multiplexing Control Register 13*/
uint32_t PINMMR14; /*Pin Multiplexing Control Register 14*/
uint32_t PINMMR15; /*Pin Multiplexing Control Register 15*/
uint32_t PINMMR16; /*Pin Multiplexing Control Register 16*/
uint32_t PINMMR17; /*Pin Multiplexing Control Register 17*/
uint32_t PINMMR18; /*Pin Multiplexing Control Register 18*/
uint32_t PINMMR19; /*Pin Multiplexing Control Register 19*/
uint32_t PINMMR20; /*Pin Multiplexing Control Register 20*/
uint32_t PINMMR21; /*Pin Multiplexing Control Register 21*/
uint32_t PINMMR22; /*Pin Multiplexing Control Register 22*/
uint32_t PINMMR23; /*Pin Multiplexing Control Register 23*/
uint32_t PINMMR24; /*Pin Multiplexing Control Register 24*/
uint32_t PINMMR25; /*Pin Multiplexing Control Register 25*/
uint32_t PINMMR26; /*Pin Multiplexing Control Register 26*/
uint32_t PINMMR27; /*Pin Multiplexing Control Register 27*/
uint32_t PINMMR28; /*Pin Multiplexing Control Register 28*/
uint32_t PINMMR29; /*Pin Multiplexing Control Register 29*/
uint32_t PINMMR30; /*Pin Multiplexing Control Register 30*/
} tms570_pinmux_t;
typedef struct{
uint32_t REVISION_REG; /*Revision Register*/
uint8_t reserved1 [28];
uint32_t ENDIAN_REG; /*Device Endianness Register*/
uint8_t reserved2 [20];
uint32_t KICK_REG0; /*Kicker Register 0*/
uint32_t KICK_REG1; /*Kicker Register 1*/
uint8_t reserved3 [160];
uint32_t ERR_RAW_STATUS_REG;/*Error Raw Status / Set Register*/
uint32_t ERR_ENABLED_STATUS_REG;/*Error Enabled Status / Clear Register*/
uint32_t ERR_ENABLE_REG; /*Error Signaling Enable Register*/
uint32_t ERR_ENABLE_CLR_REG;/*Error Signaling Enable Clear Register*/
uint8_t reserved4 [4];
uint32_t FAULT_ADDRESS_REG; /*Fault Address Register*/
uint32_t FAULT_STATUS_REG; /*Fault Status Register*/
uint32_t FAULT_CLEAR_REG; /*Fault Clear Register*/
uint8_t reserved5 [16];
tms570_pinmux_t PINMUX; /*Pin Multiplexing Control Registers*/
} tms570_iomm_t;
/*---------------------TMS570_IOMMPINMMR0---------------------*/
/* field: PINMMRx24To31 - Each of these byte-fields control the functionality on a given ball/pin. */
#define TMS570_IOMM_PINMMR0_PINMMRx24To31(val) BSP_FLD32(val,24, 31)
#define TMS570_IOMM_PINMMR0_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_IOMM_PINMMR0_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: PINMMRx16To23 - Each of these byte-fields control the functionality on a given ball/pin. */
#define TMS570_IOMM_PINMMR0_PINMMRx16To23(val) BSP_FLD32(val,16, 23)
#define TMS570_IOMM_PINMMR0_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_IOMM_PINMMR0_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: PINMMRx8To16 - Each of these byte-fields control the functionality on a given ball/pin. */
#define TMS570_IOMM_PINMMR0_PINMMRx8To16(val) BSP_FLD32(val,8, 15)
#define TMS570_IOMM_PINMMR0_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_IOMM_PINMMR0_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: PINMMRx0To7 - Each of these byte-fields control the functionality on a given ball/pin. */
#define TMS570_IOMM_PINMMR0_PINMMRx0To7(val) BSP_FLD32(val,0, 7)
#define TMS570_IOMM_PINMMR0_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_IOMM_PINMMR0_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*------------------TMS570_IOMMREVISION_REG------------------*/
/* field: REV_SCHEME - Revision Scheme */
#define TMS570_IOMM_REVISION_REG_REV_SCHEME(val) BSP_FLD32(val,30, 31)
#define TMS570_IOMM_REVISION_REG_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
#define TMS570_IOMM_REVISION_REG_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
/* field: REV_MODULE - Module Id */
#define TMS570_IOMM_REVISION_REG_REV_MODULE(val) BSP_FLD32(val,16, 27)
#define TMS570_IOMM_REVISION_REG_REV_MODULE_GET(reg) BSP_FLD32GET(reg,16, 27)
#define TMS570_IOMM_REVISION_REG_REV_MODULE_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
/* field: REV_RTL - RTL Revision */
#define TMS570_IOMM_REVISION_REG_REV_RTL(val) BSP_FLD32(val,11, 15)
#define TMS570_IOMM_REVISION_REG_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
#define TMS570_IOMM_REVISION_REG_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
/* field: REV_MAJOR - Major Revision */
#define TMS570_IOMM_REVISION_REG_REV_MAJOR(val) BSP_FLD32(val,8, 10)
#define TMS570_IOMM_REVISION_REG_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_IOMM_REVISION_REG_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: REV_CUSTOM - REV CUSTOM 0 Custom Revision */
#define TMS570_IOMM_REVISION_REG_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
/* field: REV_MINOR - Minor Revision */
#define TMS570_IOMM_REVISION_REG_REV_MINOR(val) BSP_FLD32(val,0, 5)
#define TMS570_IOMM_REVISION_REG_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_IOMM_REVISION_REG_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*-------------------TMS570_IOMMENDIAN_REG-------------------*/
/* field: ENDIAN - Device endianness */
#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_FLD32(0)
/*--------------------TMS570_IOMMKICK_REG0--------------------*/
/* field: KICK0 - Kicker 0 Register. */
#define TMS570_IOMM_KICK_REG0_KICK0(val) BSP_FLD32(val,0, 31)
#define TMS570_IOMM_KICK_REG0_KICK0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_IOMM_KICK_REG0_KICK0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_IOMMKICK_REG1--------------------*/
/* field: KICK1 - Kicker 1 Register. */
#define TMS570_IOMM_KICK_REG1_KICK1(val) BSP_FLD32(val,0, 31)
#define TMS570_IOMM_KICK_REG1_KICK1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_IOMM_KICK_REG1_KICK1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------TMS570_IOMMERR_RAW_STATUS_REG---------------*/
/* field: ADDR_ERR - Addressing Error Status and Error Signaling Enable. */
#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_FLD32(1)
/* field: PROT_ERR - register inside the IOMM is written in the CPU's user mode of operation. */
#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_FLD32(0)
/*-------------TMS570_IOMMERR_ENABLED_STATUS_REG-------------*/
/* field: ENABLED_ADDR_ERR - Addressing Error Signaling Enable Status and Status Clear */
#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_FLD32(1)
/* field: ENABLED_PROT_ERR - Protection Error Signaling Enable Status and Status Clear */
#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_FLD32(0)
/*-----------------TMS570_IOMMERR_ENABLE_REG-----------------*/
/* field: ADDR_ERR_EN - Addressing Error Signaling Enable */
#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_FLD32(1)
/* field: PROT_ERR_EN - Protection ErrorSignaling Enable */
#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_FLD32(0)
/*---------------TMS570_IOMMERR_ENABLE_CLR_REG---------------*/
/* field: ADDR_ERR_EN_CLR - Addressing Error Signaling Enable Clear */
#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_FLD32(1)
/* field: PROT_ERR_EN_CLR - Protection Error Signaling Enable Clear */
#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_FLD32(0)
/*----------------TMS570_IOMMFAULT_ADDRESS_REG----------------*/
/* field: FAULT_ADDR - Fault Address. */
#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR(val) BSP_FLD32(val,0, 31)
#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------TMS570_IOMMFAULT_STATUS_REG----------------*/
/* field: FAULT_ID - Faulting Transaction ID */
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID(val) BSP_FLD32(val,24, 27)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: FAULT_MSTID - ID of Master that initiated the faulting transaction */
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID(val) BSP_FLD32(val,16, 23)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: FAULT_PRIVID - Faulting Privilege ID */
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID(val) BSP_FLD32(val,9, 12)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_GET(reg) BSP_FLD32GET(reg,9, 12)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_SET(reg,val) BSP_FLD32SET(reg, val,9, 12)
/* field: FAULT_TYPE - Type of fault detected */
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE(val) BSP_FLD32(val,0, 5)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*-----------------TMS570_IOMMFAULT_CLEAR_REG-----------------*/
/* field: FAULT_CLEAR - Fault Clear */
#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_FLD32(0)
/*---------------------TMS570_IOMMPINMUX---------------------*/
/* field: FAULT_CLEAR - Fault Clear */
#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_IOMM */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
+594
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
+239
View File
@@ -0,0 +1,239 @@
/* The header file is generated by make_header.py from MDIO.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_MDIO
#define LIBBSP_ARM_tms570_MDIO
#include <bsp/utility.h>
typedef struct{
uint32_t REVID; /*MDIO Revision ID Register*/
uint32_t CONTROL; /*MDIO Control Register*/
uint32_t ALIVE; /*PHY Alive Status register*/
uint32_t LINK; /*PHY Link Status Register*/
uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/
uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/
uint8_t reserved1 [8];
uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/
uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/
uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/
uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/
uint8_t reserved2 [80];
uint32_t USERACCESS0; /*MDIO User Access Register 0*/
uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/
uint32_t USERACCESS1; /*MDIO User Access Register 1*/
uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/
} tms570_mdio_t;
/*----------------------TMS570_MDIOREVID----------------------*/
/* field: REV - Identifies the MDIO Module revision. */
#define TMS570_MDIO_REVID_REV(val) BSP_FLD32(val,0, 31)
#define TMS570_MDIO_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_MDIO_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_MDIOCONTROL---------------------*/
/* field: IDLE - State machine IDLE status bit. */
#define TMS570_MDIO_CONTROL_IDLE BSP_FLD32(31)
/* field: ENABLE - State machine enable control bit. */
#define TMS570_MDIO_CONTROL_ENABLE BSP_FLD32(30)
/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28)
#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: PREAMBLE - Preamble disable */
#define TMS570_MDIO_CONTROL_PREAMBLE BSP_FLD32(20)
/* field: FAULT - Fault indicator. */
#define TMS570_MDIO_CONTROL_FAULT BSP_FLD32(19)
/* field: FAULTENB - Fault detect enable. */
#define TMS570_MDIO_CONTROL_FAULTENB BSP_FLD32(18)
/* field: CLKDIV - Clock Divider bits. */
#define TMS570_MDIO_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
#define TMS570_MDIO_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_MDIO_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*----------------------TMS570_MDIOALIVE----------------------*/
/* field: ALIVE - MDIO Alive bits. */
#define TMS570_MDIO_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
#define TMS570_MDIO_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_MDIO_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_MDIOLINK----------------------*/
/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
#define TMS570_MDIO_LINK_LINK(val) BSP_FLD32(val,0, 31)
#define TMS570_MDIO_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_MDIO_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_MDIOLINKINTRAW-------------------*/
/* field: USERPHY1 - MDIO Link change event, raw value. */
#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_FLD32(1)
/* field: USERPHY0 - MDIO Link change event, raw value. */
#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_FLD32(0)
/*------------------TMS570_MDIOLINKINTMASKED------------------*/
/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
/*-------------------TMS570_MDIOUSERINTRAW-------------------*/
/* field: USERACCESS1 - MDIO User command complete event bit. */
#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - MDIO User command complete event bit. */
#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_FLD32(0)
/*------------------TMS570_MDIOUSERINTMASKED------------------*/
/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
/*-----------------TMS570_MDIOUSERINTMASKSET-----------------*/
/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
/*----------------TMS570_MDIOUSERINTMASKCLEAR----------------*/
/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
/*-------------------TMS570_MDIOUSERACCESS0-------------------*/
/* field: GO - Go bit. */
#define TMS570_MDIO_USERACCESS0_GO BSP_FLD32(31)
/* field: WRITE - Write enable bit. */
#define TMS570_MDIO_USERACCESS0_WRITE BSP_FLD32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
#define TMS570_MDIO_USERACCESS0_ACK BSP_FLD32(29)
/* field: REGADR - Register address bits. */
#define TMS570_MDIO_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
#define TMS570_MDIO_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
#define TMS570_MDIO_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
#define TMS570_MDIO_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20)
#define TMS570_MDIO_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
#define TMS570_MDIO_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
/* field: DATA - User data bits. */
#define TMS570_MDIO_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15)
#define TMS570_MDIO_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_MDIO_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_MDIOUSERPHYSEL0-------------------*/
/* field: LINKSEL - Link status determination select bit. */
#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_FLD32(7)
/* field: LINKINTENB - Link change interrupt enable. */
#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_MDIO_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
/*-------------------TMS570_MDIOUSERACCESS1-------------------*/
/* field: GO - Go bit. */
#define TMS570_MDIO_USERACCESS1_GO BSP_FLD32(31)
/* field: WRITE - Write enable bit. */
#define TMS570_MDIO_USERACCESS1_WRITE BSP_FLD32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
#define TMS570_MDIO_USERACCESS1_ACK BSP_FLD32(29)
/* field: REGADR - Register address bits. */
#define TMS570_MDIO_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
#define TMS570_MDIO_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
#define TMS570_MDIO_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
#define TMS570_MDIO_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20)
#define TMS570_MDIO_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
#define TMS570_MDIO_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
/* field: DATA - User data bits. */
#define TMS570_MDIO_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15)
#define TMS570_MDIO_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_MDIO_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_MDIOUSERPHYSEL1-------------------*/
/* field: LINKSEL - Link status determination select bit. */
#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_FLD32(7)
/* field: LINKINTENB - Link change interrupt enable. */
#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_MDIO_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
#endif /* LIBBSP_ARM_tms570_MDIO */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
+377
View File
@@ -0,0 +1,377 @@
/* The header file is generated by make_header.py from N2HET.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_NHET
#define LIBBSP_ARM_tms570_NHET
#include <bsp/utility.h>
typedef struct{
uint32_t GCR; /*Global Configuration Register*/
uint32_t PFR; /*Prescale Factor Register*/
uint32_t ADDR; /*NHET Current Address Register*/
uint32_t OFF1; /*Offset Index Priority Level 1 Register*/
uint32_t OFF2; /*Offset Index Priority Level 2 Register*/
uint32_t INTENAS; /*Interrupt Enable Set Register*/
uint32_t INTENAC; /*Interrupt Enable Clear Register*/
uint32_t EXC1; /*Exception Control Register 1*/
uint32_t EXC2; /*Exception Control Register 2*/
uint32_t PRY; /*Interrupt Priority Register*/
uint32_t FLG; /*Interrupt Flag Register*/
uint32_t AND; /*AND Share Control Register*/
uint8_t reserved1 [4];
uint32_t HRSH; /*HR Share Control Register*/
uint32_t XOR; /*HR XOR-Share Control Register*/
uint32_t REQENS; /*Request Enable Set Register*/
uint32_t REQENC; /*Request Enable Clear Register*/
uint32_t REQDS; /*Request Destination Select Register*/
uint8_t reserved2 [4];
uint32_t DIR; /*NHET Direction Register*/
uint32_t DIN; /*NHET Data Input Register*/
uint32_t DOUT; /*NHET Data Output Register*/
uint32_t DSET; /*NHET Data Set Register*/
uint32_t DCLR; /*NHET Data Clear Register*/
uint32_t PDR; /*NHET Open Drain Register*/
uint32_t PULDIS; /*NHET Pull Disable Register*/
uint32_t PSL; /*NHET Pull Select Register*/
uint8_t reserved3 [8];
uint32_t PCR; /*Parity Control Register*/
uint32_t PAR; /*Parity Address Register*/
uint32_t PPR; /*Parity Pin Register*/
uint32_t SFPRLD; /*Suppression Filter Preload Register*/
uint32_t SFENA; /*Suppression Filter Enable Register*/
uint8_t reserved4 [4];
uint32_t LBPSEL; /*Loop Back Pair Select Register*/
uint32_t LBPDIR; /*Loop Back Pair Direction Register*/
uint32_t PINDIS; /*NHET Pin Disable Register*/
} tms570_nhet_t;
/*-----------------------TMS570_NHETGCR-----------------------*/
/* field: HET_PIN_ENA - Enables the output buffers of the pin structures depending on the value of nDIS and DIR. */
#define TMS570_NHET_GCR_HET_PIN_ENA BSP_FLD32(24)
/* field: MP - Master Priority */
#define TMS570_NHET_GCR_MP(val) BSP_FLD32(val,21, 22)
#define TMS570_NHET_GCR_MP_GET(reg) BSP_FLD32GET(reg,21, 22)
#define TMS570_NHET_GCR_MP_SET(reg,val) BSP_FLD32SET(reg, val,21, 22)
/* field: PPF - Protect Program Fields */
#define TMS570_NHET_GCR_PPF BSP_FLD32(18)
/* field: IS - Ignore Suspend */
#define TMS570_NHET_GCR_IS BSP_FLD32(17)
/* field: CMS - Clk_master/slave */
#define TMS570_NHET_GCR_CMS BSP_FLD32(16)
/*-----------------------TMS570_NHETPFR-----------------------*/
/* field: LRPFC - oop Resolution Pre-scale Factor Code */
#define TMS570_NHET_PFR_LRPFC(val) BSP_FLD32(val,8, 10)
#define TMS570_NHET_PFR_LRPFC_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_NHET_PFR_LRPFC_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: HRPFC - High Resolution Pre-scale Factor Code */
#define TMS570_NHET_PFR_HRPFC(val) BSP_FLD32(val,0, 5)
#define TMS570_NHET_PFR_HRPFC_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_NHET_PFR_HRPFC_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*----------------------TMS570_NHETADDR----------------------*/
/* field: HETADDR - N2HET Current Address */
#define TMS570_NHET_ADDR_HETADDR(val) BSP_FLD32(val,0, 8)
#define TMS570_NHET_ADDR_HETADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_NHET_ADDR_HETADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
/*----------------------TMS570_NHETOFF1----------------------*/
/* field: OFFSET1 - HETOFF1[5:0] indexes the currently pending high-priority interrupt. */
#define TMS570_NHET_OFF1_OFFSET1(val) BSP_FLD32(val,0, 5)
#define TMS570_NHET_OFF1_OFFSET1_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_NHET_OFF1_OFFSET1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*----------------------TMS570_NHETOFF2----------------------*/
/* field: OFFSET2 - HETOFF2[5:0] indexes the currently pending low-priority interrupt. */
#define TMS570_NHET_OFF2_OFFSET2(val) BSP_FLD32(val,0, 5)
#define TMS570_NHET_OFF2_OFFSET2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_NHET_OFF2_OFFSET2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*---------------------TMS570_NHETINTENAS---------------------*/
/* field: HETINTENAS - Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode. */
#define TMS570_NHET_INTENAS_HETINTENAS(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_INTENAS_HETINTENAS_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_INTENAS_HETINTENAS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_NHETINTENAC---------------------*/
/* field: HETINTENAC - Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode. */
#define TMS570_NHET_INTENAC_HETINTENAC(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_INTENAC_HETINTENAC_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_INTENAC_HETINTENAC_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_NHETEXC1----------------------*/
/* field: APCNT_OVRFL_ENA - APCNT Overflow Enable */
#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_FLD32(24)
/* field: APCNT_UNRFL_ENA - APCNT Underflow Enable */
#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_FLD32(16)
/* field: PRGM_OVRFL_ENA - Program Overflow Enable */
#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_FLD32(8)
/* field: APCNT_OVRFL_PRY - APCNT Overflow Exception Interrupt Priority */
#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_FLD32(2)
/* field: APCNT_UNRFL_PRY - APCNT Underflow Exception Interrupt Priority */
#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_FLD32(1)
/* field: PRGM_OVRFL_PRY - ProgramOverflow Exception Interrupt Priority */
#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_FLD32(0)
/*----------------------TMS570_NHETEXC2----------------------*/
/* field: DEBUG_STATUS_FLAG - Debug Status Flag. */
#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_FLD32(8)
/* field: APCNT_OVRFL_FLAG - APCNT Overflow Flag */
#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_FLD32(2)
/* field: APCNT_UNDFL_FLAG - APCNT Underflow Flag */
#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_FLD32(1)
/* field: PRGM_OVERFL_FLAG - Program Overflow Flag */
#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_FLD32(0)
/*-----------------------TMS570_NHETPRY-----------------------*/
/* field: HETPRY - HET Interrupt Priority Level bits */
#define TMS570_NHET_PRY_HETPRY(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_PRY_HETPRY_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_PRY_HETPRY_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_NHETFLG-----------------------*/
/* field: HETFLAG - Interrupt Flag Register Bits */
#define TMS570_NHET_FLG_HETFLAG(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_FLG_HETFLAG_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_FLG_HETFLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_NHETAND-----------------------*/
/* field: AND_SHARE - AND Share Enable */
#define TMS570_NHET_AND_AND_SHARE(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_AND_AND_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_AND_AND_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*----------------------TMS570_NHETHRSH----------------------*/
/* field: HR_SHARE - HR Share Bits */
#define TMS570_NHET_HRSH_HR_SHARE(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_HRSH_HR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_HRSH_HR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-----------------------TMS570_NHETXOR-----------------------*/
/* field: XOR_SHARE - XOR Share Enable */
#define TMS570_NHET_XOR_XOR_SHARE(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_XOR_XOR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_XOR_XOR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_NHETREQENS---------------------*/
/* field: REQ_ENA_n - Request Enable Bits */
#define TMS570_NHET_REQENS_REQ_ENA_n(val) BSP_FLD32(val,0, 7)
#define TMS570_NHET_REQENS_REQ_ENA_n_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_NHET_REQENS_REQ_ENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*---------------------TMS570_NHETREQENC---------------------*/
/* field: REQ_DIS_n - Request Disable Bits */
#define TMS570_NHET_REQENC_REQ_DIS_n(val) BSP_FLD32(val,0, 7)
#define TMS570_NHET_REQENC_REQ_DIS_n_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_NHET_REQENC_REQ_DIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_NHETREQDS----------------------*/
/* field: TDBS_n - HTU, DMA or Both Select Bits */
#define TMS570_NHET_REQDS_TDBS_n(val) BSP_FLD32(val,16, 23)
#define TMS570_NHET_REQDS_TDBS_n_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_NHET_REQDS_TDBS_n_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: TDS_n - HTU or DMA Select Bits */
#define TMS570_NHET_REQDS_TDS_n(val) BSP_FLD32(val,0, 7)
#define TMS570_NHET_REQDS_TDS_n_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_NHET_REQDS_TDS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_NHETDIR-----------------------*/
/* field: HETDIR_n - Data direction of NHET pins */
#define TMS570_NHET_DIR_HETDIR_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_DIR_HETDIR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_DIR_HETDIR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_NHETDIN-----------------------*/
/* field: HETDIN_n - Data input. This bit displays the logic state of the pin. */
#define TMS570_NHET_DIN_HETDIN_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_DIN_HETDIN_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_DIN_HETDIN_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_NHETDOUT----------------------*/
/* field: HETDOUT_n - Data out write. Writes to this bit will only take effect when the pin is configured as an output. */
#define TMS570_NHET_DOUT_HETDOUT_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_DOUT_HETDOUT_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_DOUT_HETDOUT_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_NHETDSET----------------------*/
/* field: HETDSET_n - This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write */
#define TMS570_NHET_DSET_HETDSET_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_DSET_HETDSET_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_DSET_HETDSET_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_NHETDCLR----------------------*/
/* field: HETDCLR_n - This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modifywrite */
#define TMS570_NHET_DCLR_HETDCLR_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_DCLR_HETDCLR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_DCLR_HETDCLR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_NHETPDR-----------------------*/
/* field: HETPDR_n - Open drain control for HET[n] pins */
#define TMS570_NHET_PDR_HETPDR_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_PDR_HETPDR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_PDR_HETPDR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_NHETPULDIS---------------------*/
/* field: HETPULDIS_n - Pull disable for N2HET pins */
#define TMS570_NHET_PULDIS_HETPULDIS_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_PULDIS_HETPULDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_PULDIS_HETPULDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_NHETPSL-----------------------*/
/* field: HETPSL_n - Pull select for NHET pins */
#define TMS570_NHET_PSL_HETPSL_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_PSL_HETPSL_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_PSL_HETPSL_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_NHETPCR-----------------------*/
/* field: TEST - Test Bit. */
#define TMS570_NHET_PCR_TEST BSP_FLD32(8)
/* field: PARITY_ENA - Enable/disable parity checking. */
#define TMS570_NHET_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
#define TMS570_NHET_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_NHET_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-----------------------TMS570_NHETPAR-----------------------*/
/* field: PAOFF - Parity Error Address Offset. */
#define TMS570_NHET_PAR_PAOFF(val) BSP_FLD32(val,2, 12)
#define TMS570_NHET_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,2, 12)
#define TMS570_NHET_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,2, 12)
/*-----------------------TMS570_NHETPPR-----------------------*/
/* field: HETPPR_n - NHET Parity Pin Select Bits - Allows HET[n] pins to be configured to drive to a known state when */
#define TMS570_NHET_PPR_HETPPR_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_PPR_HETPPR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_PPR_HETPPR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_NHETSFPRLD---------------------*/
/* field: CCDIV - Counter Clock Divider */
#define TMS570_NHET_SFPRLD_CCDIV(val) BSP_FLD32(val,16, 17)
#define TMS570_NHET_SFPRLD_CCDIV_GET(reg) BSP_FLD32GET(reg,16, 17)
#define TMS570_NHET_SFPRLD_CCDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
/* field: CPRLD - Counter Preload Value */
#define TMS570_NHET_SFPRLD_CPRLD(val) BSP_FLD32(val,0, 9)
#define TMS570_NHET_SFPRLD_CPRLD_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_NHET_SFPRLD_CPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
/*----------------------TMS570_NHETSFENA----------------------*/
/* field: HETSFENA_n - Suppression Filter Enable Bits */
#define TMS570_NHET_SFENA_HETSFENA_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_SFENA_HETSFENA_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_SFENA_HETSFENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_NHETLBPSEL---------------------*/
/* field: LBPTYPE - Loop Back Pair Type Select Bits */
#define TMS570_NHET_LBPSEL_LBPTYPE(val) BSP_FLD32(val,16, 31)
#define TMS570_NHET_LBPSEL_LBPTYPE_GET(reg) BSP_FLD32GET(reg,16, 31)
#define TMS570_NHET_LBPSEL_LBPTYPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
/* field: LBPSEL - Loop Back Pair Select Bits */
#define TMS570_NHET_LBPSEL_LBPSEL(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_LBPSEL_LBPSEL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_LBPSEL_LBPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_NHETLBPDIR---------------------*/
/* field: LBPTSTENA - Loopback Test Enable Key */
#define TMS570_NHET_LBPDIR_LBPTSTENA(val) BSP_FLD32(val,16, 19)
#define TMS570_NHET_LBPDIR_LBPTSTENA_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_NHET_LBPDIR_LBPTSTENA_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: LBPDIR - Loop Back Pair Direction Bits */
#define TMS570_NHET_LBPDIR_LBPDIR(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_LBPDIR_LBPDIR_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_LBPDIR_LBPDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_NHETPINDIS---------------------*/
/* field: HETPINDIS_n - N2HET Pin Disable Bits */
#define TMS570_NHET_PINDIS_HETPINDIS_n(val) BSP_FLD32(val,0, 31)
#define TMS570_NHET_PINDIS_HETPINDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_NHET_PINDIS_HETPINDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_NHET */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
+213
View File
@@ -0,0 +1,213 @@
/* The header file is generated by make_header.py from PBIST.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_PBIST
#define LIBBSP_ARM_tms570_PBIST
#include <bsp/utility.h>
typedef struct{
uint32_t DNW[88]; /*Reserved DO NOT WRITE*/
uint32_t RAMT; /*RAM Configuration Register*/
uint32_t DLR; /*Datalogger Register*/
uint8_t reserved1 [24];
uint32_t PACT; /*PBIST Activate/ROM Clock Enable Register*/
uint32_t PBISTID; /*PBIST ID Register*/
uint32_t OVER; /*Override Register*/
uint8_t reserved2 [4];
uint32_t FSRF0; /*Fail Status Fail Register 0*/
uint8_t reserved3 [4];
uint32_t FSRC0; /*Fail Status Count Register 0*/
uint32_t FSRC1; /*Fail Status Count Register 1*/
uint32_t FSRA0; /*Fail Status Address 0 Register*/
uint32_t FSRA1; /*Fail Status Address 1 Register*/
uint32_t FSRDL0; /*Fail Status Data Register 0*/
uint8_t reserved4 [4];
uint32_t FSRDL1; /*Fail Status Data Register 1*/
uint8_t reserved5 [12];
uint32_t ROM; /*ROM Mask Register*/
uint32_t ALGO; /*ROM Algorithm Mask Register*/
uint32_t RINFOL; /*RAM Info Mask Lower Register*/
uint32_t RINFOUL; /*RAM Info Mask Lower Register*/
} tms570_pbist_t;
/*----------------------TMS570_PBISTDNW----------------------*/
/* field: Reserved - Do not write */
#define TMS570_PBIST_DNW_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_PBIST_DNW_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PBIST_DNW_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_PBISTRAMT----------------------*/
/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
#define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */
#define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23)
#define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: DWR - Data Width Register */
#define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15)
#define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: SMS - Sense Margin Select Register */
#define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7)
#define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7)
#define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
/* field: PLS - Pipeline Latency Select */
#define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5)
#define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5)
#define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5)
/* field: RLS - RAM Latency Select */
#define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1)
#define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*----------------------TMS570_PBISTDLR----------------------*/
/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
#define TMS570_PBIST_DLR_DLR4 BSP_FLD32(4)
/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
#define TMS570_PBIST_DLR_DLR2 BSP_FLD32(2)
/*----------------------TMS570_PBISTPACT----------------------*/
/* field: PACT1 - PBIST Activate */
#define TMS570_PBIST_PACT_PACT1 BSP_FLD32(1)
/* field: PACT0 - ROM Clock Enable Register */
#define TMS570_PBIST_PACT_PACT0 BSP_FLD32(0)
/*--------------------TMS570_PBISTPBISTID--------------------*/
/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_PBISTOVER----------------------*/
/* field: OVER0 - RINFO Override Bit */
#define TMS570_PBIST_OVER_OVER0 BSP_FLD32(0)
/*---------------------TMS570_PBISTFSRF0---------------------*/
/* field: FSRF0 - Fail Status 0. */
#define TMS570_PBIST_FSRF0_FSRF0 BSP_FLD32(0)
/*---------------------TMS570_PBISTFSRC0---------------------*/
/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*---------------------TMS570_PBISTFSRC1---------------------*/
/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*---------------------TMS570_PBISTFSRA0---------------------*/
/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_PBISTFSRA1---------------------*/
/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_PBISTFSRDL0---------------------*/
/* field: FSRDL1 - Failure data on port 1 */
#define TMS570_PBIST_FSRDL0_FSRDL1(val) BSP_FLD32(val,0, 31)
#define TMS570_PBIST_FSRDL0_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PBIST_FSRDL0_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_PBISTFSRDL1---------------------*/
/* field: FSRDL1 - Failure data on port 1 */
#define TMS570_PBIST_FSRDL1_FSRDL1(val) BSP_FLD32(val,0, 31)
#define TMS570_PBIST_FSRDL1_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PBIST_FSRDL1_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_PBISTROM----------------------*/
/* field: ROM - ROM Mask */
#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*----------------------TMS570_PBISTALGO----------------------*/
/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
#define TMS570_PBIST_ALGO_ROM_ALG_MASK(val) BSP_FLD32(val,0, 31)
#define TMS570_PBIST_ALGO_ROM_ALG_MASK_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PBIST_ALGO_ROM_ALG_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_PBISTRINFOL---------------------*/
/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW(val) BSP_FLD32(val,0, 31)
#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_PBISTRINFOUL--------------------*/
/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP(val) BSP_FLD32(val,0, 31)
#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_PBIST */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
+150
View File
@@ -0,0 +1,150 @@
/* The header file is generated by make_header.py from PCR.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_PCR
#define LIBBSP_ARM_tms570_PCR
#include <bsp/utility.h>
typedef struct{
uint32_t PMPROTSET0; /*Peripheral Memory Protection Set Register 0*/
uint32_t PMPROTSET1; /*Peripheral Memory Protection Set Register 1*/
uint8_t reserved1 [8];
uint32_t PMPROTCLR0; /*Peripheral Memory Protection Clear Register 0*/
uint32_t PMPROTCLR1; /*Peripheral Memory Protection Clear Register 1*/
uint8_t reserved2 [8];
uint32_t PPROTSET0; /*Peripheral Protection Set Register 0*/
uint32_t PPROTSET1; /*Peripheral Protection Set Register 1*/
uint32_t PPROTSET2; /*Peripheral Protection Set Register 2*/
uint32_t PPROTSET3; /*Peripheral Protection Set Register 3*/
uint8_t reserved3 [16];
uint32_t PPROTCLR0; /*Peripheral Protection Clear Register 0*/
uint32_t PPROTCLR1; /*Peripheral Protection Clear Register 1*/
uint32_t PPROTCLR2; /*Peripheral Protection Clear Register 2*/
uint32_t PPROTCLR3; /*Peripheral Protection Clear Register 3*/
uint8_t reserved4 [16];
uint32_t PCSPWRDWNSET0; /*Peripheral Memory Power-Down Set Register 0*/
uint32_t PCSPWRDWNSET1; /*Peripheral Memory Power-Down Set Register 1*/
uint8_t reserved5 [8];
uint32_t PCSPWRDWNCLR0; /*Peripheral Memory Power-Down Clear Register 0*/
uint32_t PCSPWRDWNCLR1; /*Peripheral Memory Power-Down Clear Register 1*/
uint8_t reserved6 [8];
uint32_t PSPWRDWNSET0; /*Peripheral Power-Down Set Register 0*/
uint32_t PSPWRDWNSET1; /*Peripheral Power-Down Set Register 1*/
uint32_t PSPWRDWNSET2; /*Peripheral Power-Down Set Register 2*/
uint32_t PSPWRDWNSET3; /*Peripheral Power-Down Set Register 3*/
uint8_t reserved7 [16];
uint32_t PSPWRDWNCLR0; /*Peripheral Power-Down Clear Register 0*/
uint32_t PSPWRDWNCLR1; /*Peripheral Power-Down Clear Register 1*/
uint32_t PSPWRDWNCLR2; /*Peripheral Power-Down Clear Register 2*/
uint32_t PSPWRDWNCLR3; /*Peripheral Power-Down Clear Register 3*/
} tms570_pcr_t;
/*--------------------TMS570_PCRPMPROTSET0--------------------*/
/* field: PCSPROTSET - Peripheral memory frame protection set. */
#define TMS570_PCR_PMPROTSET0_PCSPROTSET(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PMPROTSET0_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PMPROTSET0_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_PCRPMPROTSET1--------------------*/
/* field: PCSPROTSET - Peripheral memory frame protection set. */
#define TMS570_PCR_PMPROTSET1_PCSPROTSET(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PMPROTSET1_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PMPROTSET1_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_PCRPMPROTCLR0--------------------*/
/* field: PCSPROTCLR - Peripheral memory frame protection clear. */
#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_PCRPMPROTCLR1--------------------*/
/* field: PCSPROTCLR - Peripheral memory frame protection clear. */
#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_PCRPPROTSET0--------------------*/
/* field: PROTSET - Peripheral select quadrant protection set. */
#define TMS570_PCR_PPROTSET0_PROTSET(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PPROTSET0_PROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PPROTSET0_PROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_PCRPPROTCLR0--------------------*/
/* field: PROTCLR - Peripheral select quadrant protection clear. */
#define TMS570_PCR_PPROTCLR0_PROTCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PPROTCLR0_PROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PPROTCLR0_PROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_PCRPCSPWRDWNSET0------------------*/
/* field: PWRDNSET - Peripheral memory clock power-down set. */
#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_PCRPCSPWRDWNCLR0------------------*/
/* field: PWRDNCLR - Peripheral memory clock power-down clear. */
#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_PCRPSPWRDWNSET0-------------------*/
/* field: PWRDWNSET - Peripheral select quadrant clock power-down set. */
#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_PCRPSPWRDWNCLR0-------------------*/
/* field: PWRDWNCLR - Peripheral select quadrant clock power-down clear. */
#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR(val) BSP_FLD32(val,0, 31)
#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_PCR */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
+304
View File
@@ -0,0 +1,304 @@
/* The header file is generated by make_header.py from PLL.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_PLL
#define LIBBSP_ARM_tms570_PLL
#include <bsp/utility.h>
typedef struct{
uint32_t PLLCTL3; /*PLL Control 3 Register*/
uint8_t reserved1 [108];
uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/
uint8_t reserved2 [7600];
uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/
uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/
uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/
uint32_t CSDIS; /*Clock Source Disable Register*/
uint32_t CSDISSET; /*Clock Source Disable Set Register*/
uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/
uint8_t reserved3 [24];
uint32_t CSVSTAT; /*Clock Source Valid Status Register*/
uint8_t reserved4 [24];
uint32_t PLLCTL1; /*PLL Control 1 Register*/
uint32_t PLLCTL2; /*PLL Control 2 Register*/
uint8_t reserved5 [16];
uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/
uint32_t CLKTEST; /*Clock Test Register*/
uint8_t reserved6 [16];
uint32_t GPREG1; /*General Purpose Register*/
uint8_t reserved7 [72];
uint32_t GLBSTAT; /*Global Status Register*/
} tms570_pll_t;
/*---------------------TMS570_PLLPLLCTL3---------------------*/
/* field: ODPLL2 - Internal PLL Output Divider */
#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
/* field: PLLDIV2 - PLL2 Output Clock Divider */
#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: REFCLKDIV2 - Reference Clock Divider */
#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
/* field: PLLMUL2 - PLL2 Multiplication Factor */
#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_PLLCLKSLIP---------------------*/
/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*---------------------TMS570_PLLSSWPLL1---------------------*/
/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: COUNTER_READ_READY - Counter read ready. */
#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_FLD32(6)
/* field: COUNTER_RESET - Counter reset. */
#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_FLD32(5)
/* field: COUNTER_EN - Counter enable. */
#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_FLD32(4)
/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3)
#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_FLD32(0)
/*---------------------TMS570_PLLSSWPLL2---------------------*/
/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_PLLSSWPLL3---------------------*/
/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_PLLCSDIS----------------------*/
/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */
#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_PLLCSDISSET---------------------*/
/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */
#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_PLLCSDISCLR---------------------*/
/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */
#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_PLLCSVSTAT---------------------*/
/* field: CLKSR_7_3V - Clock source[7-0] valid. */
#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
/* field: CLKSR_1_0V - Clock source[1-0] valid. */
#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1)
#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_PLLPLLCTL1---------------------*/
/* field: ROS - Reset on PLL Slip */
#define TMS570_PLL_PLLCTL1_ROS BSP_FLD32(31)
/* field: MASK_SLIP - Mask detection of PLL slip */
#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: PLLDIV - PLL Output Clock Divider */
#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: ROF - Reset on Oscillator Fail */
#define TMS570_PLL_PLLCTL1_ROF BSP_FLD32(23)
/* field: REFCLKDIV - Reference Clock Divider */
#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
/* field: PLLMUL - PLL Multiplication Factor */
#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_PLLPLLCTL2---------------------*/
/* field: FMENA - Frequency Modulation Enable. */
#define TMS570_PLL_PLLCTL2_FMENA BSP_FLD32(31)
/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
/* field: ODPLL - Internal PLL Output Divider. */
#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
/* field: SPR_AMOUNT - Spreading Amount. */
#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
/*--------------------TMS570_PLLLPOMONCTL--------------------*/
/* field: BIAS_ENABLE - Bias enable. */
#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
/* field: HFTRIM - High frequency oscillator trim value. */
#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
/*---------------------TMS570_PLLCLKTEST---------------------*/
/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
/* field: RANGEDETCTRL - Range detection control. */
#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/*----------------------TMS570_PLLGPREG1----------------------*/
/* field: EMIF_FUNC - Enable EMIF functions to be output. */
#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_FLD32(31)
/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_PLLGLBSTAT---------------------*/
/* field: FBSLIP - PLL over cycle slip detection. */
#define TMS570_PLL_GLBSTAT_FBSLIP BSP_FLD32(9)
/* field: RFSLIP - PLL under cycle slip detection. */
#define TMS570_PLL_GLBSTAT_RFSLIP BSP_FLD32(8)
/* field: OSCFAIL - Oscillator fail flag bit. */
#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_PLL */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
+258
View File
@@ -0,0 +1,258 @@
/* The header file is generated by make_header.py from PMM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_PMM
#define LIBBSP_ARM_tms570_PMM
#include <bsp/utility.h>
typedef struct{
uint32_t LOGICPDPWRCTRL0; /*Logic Power Domain Control Register 0*/
uint8_t reserved1 [12];
uint32_t MEMPDPWRCTRL0; /*Memory Power Domain Control Register 0*/
uint8_t reserved2 [12];
uint32_t PDCLKDISREG; /*Power Domain Clock Disable Register*/
uint32_t PDCLKDISSETREG; /*Power Domain Clock Disable Set Register*/
uint32_t PDCLKDISCLRREG; /*Power Domain Clock Disable Clear Register*/
uint8_t reserved3 [20];
uint32_t LOGICPDPWRSTAT[4]; /*Logic Power Domain PD2 Power Status Registers*/
uint8_t reserved4 [48];
uint32_t MEMPDPWRSTAT[3]; /*Memory Power Domain RAM_PD1 Power Status Registers*/
uint8_t reserved5 [20];
uint32_t GLOBALCTRL1; /*Global Control Register 1*/
uint8_t reserved6 [4];
uint32_t GLOBALSTAT; /*Global Status Register*/
uint32_t PRCKEYREG; /*PSCON Diagnostic Compare Key Register*/
uint32_t LPDDCSTAT1; /*LogicPD PSCON Diagnostic Compare Status Register 1*/
uint32_t LPDDCSTAT2; /*LogicPD PSCON Diagnostic Compare Status Register 2*/
uint32_t MPDDCSTAT1; /*Memory PD PSCON Diagnostic Compare Status Register 1*/
uint32_t MPDDCSTAT2; /*Memory PD PSCON Diagnostic Compare Status Register 2*/
uint32_t ISODIAGSTAT; /*Isolation Diagnostic Status Register*/
} tms570_pmm_t;
/*-----------------TMS570_PMMLOGICPDPWRCTRL0-----------------*/
/* field: LOGICPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0(val) BSP_FLD32(val,24, 27)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: LOGICPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1(val) BSP_FLD32(val,16, 19)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: LOGICPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2(val) BSP_FLD32(val,8, 11)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: LOGICPDON3 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*------------------TMS570_PMMMEMPDPWRCTRL0------------------*/
/* field: MEMPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0(val) BSP_FLD32(val,24, 27)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: MEMPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1(val) BSP_FLD32(val,16, 19)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: MEMPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2(val) BSP_FLD32(val,8, 11)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/*-------------------TMS570_PMMPDCLKDISREG-------------------*/
/* field: PDCLK_DIS_3 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. */
#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_FLD32(3)
/* field: PDCLK_DIS_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_FLD32(2)
/* field: PDCLK_DIS_1 - ead in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_FLD32(1)
/* field: PDCLK_DIS_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_FLD32(0)
/*------------------TMS570_PMMPDCLKDISSETREG------------------*/
/* field: PDCLK_DISSET_3 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. */
#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_FLD32(3)
/* field: PDCLK_DISSET_2 - Privileged Mode only. */
#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_FLD32(2)
/* field: PDCLK_DISSET_1 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. */
#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_FLD32(1)
/* field: PDCLK_DISSET_0 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. */
#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_FLD32(0)
/*------------------TMS570_PMMPDCLKDISCLRREG------------------*/
/* field: PDCLK_DISCLR_3 - PDCLK_DISCLR[3] */
#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_FLD32(3)
/* field: PDCLK_DISCLR_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_FLD32(2)
/* field: PDCLK_DISCLR_1 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_FLD32(1)
/* field: PDCLK_DISCLR_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_FLD32(0)
/*------------------TMS570_PMMLOGICPDPWRSTAT------------------*/
/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain PD2. */
#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
/* field: MEM_IN_TRANS0 - Memory in transition status for power domain PD2. */
#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
/* field: DOMAIN_ON0 - Current state of power domain PD2. */
#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
/* field: LOGICPDPWR_STAT0 - Logic power domain PD2 power state. */
#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*-------------------TMS570_PMMMEMPDPWRSTAT-------------------*/
/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain RAM_PD1. */
#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
/* field: MEM_IN_TRANS0 - Memory in transition status for power domain RAM_PD1. */
#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
/* field: DOMAIN_ON0 - Current state of power domain RAM_PD1. */
#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
/* field: MEMPDPWR_STAT0 - Memory power domain RAM_PD1 power state. */
#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*-------------------TMS570_PMMGLOBALCTRL1-------------------*/
/* field: PMCTRL_PWRDN - PMC/PSCON Power Down */
#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_FLD32(8)
/* field: AUTO_CLK_WAKE_ENA - Automatic Clock Enable on Wake Up */
#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_FLD32(0)
/*--------------------TMS570_PMMGLOBALSTAT--------------------*/
/* field: PMCTRL_IDLE - State of PMC and all PSCONs. */
#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_FLD32(0)
/*--------------------TMS570_PMMPRCKEYREG--------------------*/
/* field: MKEY - Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units. */
#define TMS570_PMM_PRCKEYREG_MKEY(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_PRCKEYREG_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PMM_PRCKEYREG_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*--------------------TMS570_PMMLPDDCSTAT1--------------------*/
/* field: LCMPE - Logic Power Domain Compare Error */
#define TMS570_PMM_LPDDCSTAT1_LCMPE(val) BSP_FLD32(val,16, 19)
#define TMS570_PMM_LPDDCSTAT1_LCMPE_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_PMM_LPDDCSTAT1_LCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: LSTC - Logic Power Domain Self-test Complete */
#define TMS570_PMM_LPDDCSTAT1_LSTC(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_LPDDCSTAT1_LSTC_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PMM_LPDDCSTAT1_LSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*--------------------TMS570_PMMLPDDCSTAT2--------------------*/
/* field: LSTET - Logic Power Domain Self-test Error Type */
#define TMS570_PMM_LPDDCSTAT2_LSTET(val) BSP_FLD32(val,16, 19)
#define TMS570_PMM_LPDDCSTAT2_LSTET_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_PMM_LPDDCSTAT2_LSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: LSTE - Logic Power Domain Self-test Error */
#define TMS570_PMM_LPDDCSTAT2_LSTE(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_LPDDCSTAT2_LSTE_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PMM_LPDDCSTAT2_LSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*--------------------TMS570_PMMMPDDCSTAT1--------------------*/
/* field: MCMPE - Memory Power Domain Compare Error */
#define TMS570_PMM_MPDDCSTAT1_MCMPE(val) BSP_FLD32(val,16, 18)
#define TMS570_PMM_MPDDCSTAT1_MCMPE_GET(reg) BSP_FLD32GET(reg,16, 18)
#define TMS570_PMM_MPDDCSTAT1_MCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
/* field: MSTC - Memory Power Domain Self-test Complete */
#define TMS570_PMM_MPDDCSTAT1_MSTC(val) BSP_FLD32(val,0, 2)
#define TMS570_PMM_MPDDCSTAT1_MSTC_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_PMM_MPDDCSTAT1_MSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*--------------------TMS570_PMMMPDDCSTAT2--------------------*/
/* field: MSTET - Memory Power Domain Self-test Error Type */
#define TMS570_PMM_MPDDCSTAT2_MSTET(val) BSP_FLD32(val,16, 18)
#define TMS570_PMM_MPDDCSTAT2_MSTET_GET(reg) BSP_FLD32GET(reg,16, 18)
#define TMS570_PMM_MPDDCSTAT2_MSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
/* field: MSTE - Memory Power Domain Self-test Error */
#define TMS570_PMM_MPDDCSTAT2_MSTE(val) BSP_FLD32(val,0, 2)
#define TMS570_PMM_MPDDCSTAT2_MSTE_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_PMM_MPDDCSTAT2_MSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*-------------------TMS570_PMMISODIAGSTAT-------------------*/
/* field: ISO_DIAG - Isolation Diagnostic */
#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
#endif /* LIBBSP_ARM_tms570_PMM */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
+336
View File
@@ -0,0 +1,336 @@
/* The header file is generated by make_header.py from POM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_POM
#define LIBBSP_ARM_tms570_POM
#include <bsp/utility.h>
typedef struct{
uint32_t PROGSTART; /*POM Program Region Start Address Register*/
uint32_t OVLSTART; /*POM Overlay Region Start Address Register*/
uint32_t REGSIZE; /*POM Region Size Register */
uint32_t Reser; /*Reserved*/
} tms570_pom_region_t;
typedef struct{
uint32_t GLBCTRL; /*POM Global Control Register*/
uint32_t REV; /*POM Revision ID*/
uint32_t CLKCTRL; /*POM Clock Gate Control Register*/
uint32_t FLG; /*POM Status Register*/
uint8_t reserved1 [496];
tms570_pom_region_t REG[32];/*Program Regions*/
uint8_t reserved2 [2816];
uint32_t ITCTRL; /*POM Integration Control Register*/
uint8_t reserved3 [156];
uint32_t CLAIMSET; /*POM Claim Set Register*/
uint32_t CLAIMCLR; /*POM Claim Clear Register*/
uint8_t reserved4 [8];
uint32_t LOCKACCESS; /*POM Lock Access Register*/
uint32_t LOCKSTATUS; /*POM Lock Status Register*/
uint32_t AUTHSTATUS; /*POM Authentication Status Register*/
uint8_t reserved5 [12];
uint32_t DEVID; /*POM Device ID Register*/
uint32_t DEVTYPE; /*POM Device Type Register*/
uint32_t PERIPHERALID4; /*POM Peripheral ID 4 Register*/
uint32_t PERIPHERALID5; /*POM Peripheral ID 5 Register*/
uint32_t PERIPHERALID6; /*POM Peripheral ID 6 Register*/
uint32_t PERIPHERALID7; /*POM Peripheral ID 7 Register*/
uint32_t PERIPHERALID0; /*POM Peripheral ID 0 Register*/
uint32_t PERIPHERALID1; /*POM Peripheral ID 1 Register*/
uint32_t PERIPHERALID2; /*POM Peripheral ID 2 Register*/
uint32_t PERIPHERALID3; /*POM Peripheral ID 3 Register*/
uint32_t COMPONENTID0; /*POM Component ID 0 Register*/
uint32_t COMPONENTID1; /*POM Component ID 1 Register*/
uint32_t COMPONENTID2; /*POM Component ID 2 Register*/
uint32_t COMPONENTID3; /*POM Component ID 3 Register*/
} tms570_pom_t;
/*--------------------TMS570_POMPROGSTART--------------------*/
/* field: STARTADDRESS - Defines the start address of the program memory region. */
#define TMS570_POM_PROGSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
#define TMS570_POM_PROGSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
#define TMS570_POM_PROGSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
/*---------------------TMS570_POMOVLSTART---------------------*/
/* field: STARTADDRESS - Defines the start address of the overlay memory region. */
#define TMS570_POM_OVLSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
#define TMS570_POM_OVLSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
#define TMS570_POM_OVLSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
/*---------------------TMS570_POMREGSIZE---------------------*/
/* field: SIZE - Region size */
#define TMS570_POM_REGSIZE_SIZE(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_REGSIZE_SIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_REGSIZE_SIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*---------------------TMS570_POMGLBCTRL---------------------*/
/* field: OTADDR - Overlay target Address. */
#define TMS570_POM_GLBCTRL_OTADDR(val) BSP_FLD32(val,23, 31)
#define TMS570_POM_GLBCTRL_OTADDR_GET(reg) BSP_FLD32GET(reg,23, 31)
#define TMS570_POM_GLBCTRL_OTADDR_SET(reg,val) BSP_FLD32SET(reg, val,23, 31)
/* field: ETO - Enable Timeout. Refer to Section 18.2.2 for more details on the timeout error. */
#define TMS570_POM_GLBCTRL_ETO(val) BSP_FLD32(val,8, 11)
#define TMS570_POM_GLBCTRL_ETO_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_POM_GLBCTRL_ETO_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: ON_OFF - Turn functionality of POM on or off. */
#define TMS570_POM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-----------------------TMS570_POMREV-----------------------*/
/* field: SCHEME - Used to distinguish between different ID schemes. */
#define TMS570_POM_REV_SCHEME(val) BSP_FLD32(val,30, 31)
#define TMS570_POM_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
#define TMS570_POM_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
/* field: FUNC - Indicates the SW compatible module family */
#define TMS570_POM_REV_FUNC(val) BSP_FLD32(val,16, 27)
#define TMS570_POM_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27)
#define TMS570_POM_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
/* field: RTL - RTL version number */
#define TMS570_POM_REV_RTL(val) BSP_FLD32(val,11, 15)
#define TMS570_POM_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
#define TMS570_POM_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
/* field: MAJOR - Major revision number */
#define TMS570_POM_REV_MAJOR(val) BSP_FLD32(val,8, 10)
#define TMS570_POM_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_POM_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: CUSTOM - Indicates a device specific implementation */
#define TMS570_POM_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
#define TMS570_POM_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
#define TMS570_POM_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
/* field: 5_0 - MINOR 8h Minor revision number */
#define TMS570_POM_REV_5_0(val) BSP_FLD32(val,0, 5)
#define TMS570_POM_REV_5_0_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_POM_REV_5_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
/*---------------------TMS570_POMCLKCTRL---------------------*/
/* field: CLK_GATE_OFF - Do not modify this bit. Leave it in its reset state. */
#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_FLD32(0)
/*-----------------------TMS570_POMFLG-----------------------*/
/* field: TO - Timeout. */
#define TMS570_POM_FLG_TO BSP_FLD32(0)
/*----------------------TMS570_POMITCTRL----------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_ITCTRL_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_ITCTRL_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_ITCTRL_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_POMCLAIMSET---------------------*/
/* field: SET1 - The module is claimed */
#define TMS570_POM_CLAIMSET_SET1 BSP_FLD32(1)
/* field: SET0 - The module is claimed */
#define TMS570_POM_CLAIMSET_SET0 BSP_FLD32(0)
/*---------------------TMS570_POMCLAIMCLR---------------------*/
/* field: CLR1 - The module is claimed */
#define TMS570_POM_CLAIMCLR_CLR1 BSP_FLD32(1)
/* field: CLR0 - The module is claimed */
#define TMS570_POM_CLAIMCLR_CLR0 BSP_FLD32(0)
/*--------------------TMS570_POMLOCKACCESS--------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_LOCKACCESS_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_LOCKACCESS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_LOCKACCESS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_POMLOCKSTATUS--------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_LOCKSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_LOCKSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_LOCKSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_POMAUTHSTATUS--------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_AUTHSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_AUTHSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_AUTHSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_POMDEVID----------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_DEVID_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_DEVID_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_DEVID_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_POMDEVTYPE---------------------*/
/* field: Sub_Type - Other */
#define TMS570_POM_DEVTYPE_Sub_Type(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_DEVTYPE_Sub_Type_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_POM_DEVTYPE_Sub_Type_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: Major_Type - Debug Control */
#define TMS570_POM_DEVTYPE_Major_Type(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_DEVTYPE_Major_Type_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_DEVTYPE_Major_Type_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*------------------TMS570_POMPERIPHERALID4------------------*/
/* field: 4KB_Count - Only 4KB implemented */
#define TMS570_POM_PERIPHERALID4_4KB_Count(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_PERIPHERALID4_4KB_Count_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_POM_PERIPHERALID4_4KB_Count_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: JEP_Continuation - JEP106 Code */
#define TMS570_POM_PERIPHERALID4_JEP_Continuation(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_PERIPHERALID4_JEP_Continuation_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_PERIPHERALID4_JEP_Continuation_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*------------------TMS570_POMPERIPHERALID5------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_PERIPHERALID5_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_PERIPHERALID5_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_PERIPHERALID5_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_POMPERIPHERALID6------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_PERIPHERALID6_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_PERIPHERALID6_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_PERIPHERALID6_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_POMPERIPHERALID7------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_PERIPHERALID7_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_PERIPHERALID7_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_PERIPHERALID7_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_POMPERIPHERALID0------------------*/
/* field: Part_Number - Reads 0, since POMREV defines the module */
#define TMS570_POM_PERIPHERALID0_Part_Number(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_PERIPHERALID0_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_PERIPHERALID0_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*------------------TMS570_POMPERIPHERALID1------------------*/
/* field: JEP106_Identity - Part of TI JEDEC number */
#define TMS570_POM_PERIPHERALID1_JEP106_Identity(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_PERIPHERALID1_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_POM_PERIPHERALID1_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: Part_Number - Reads 0, since POMREV defines the module */
#define TMS570_POM_PERIPHERALID1_Part_Number(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_PERIPHERALID1_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_PERIPHERALID1_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*------------------TMS570_POMPERIPHERALID2------------------*/
/* field: Revision - Reads 0, since POMREV defines the module */
#define TMS570_POM_PERIPHERALID2_Revision(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_PERIPHERALID2_Revision_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_POM_PERIPHERALID2_Revision_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: JEDEC - Indicates JEDEC assigned value */
#define TMS570_POM_PERIPHERALID2_JEDEC BSP_FLD32(3)
/* field: JEP106_Identity - JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code */
#define TMS570_POM_PERIPHERALID2_JEP106_Identity(val) BSP_FLD32(val,0, 2)
#define TMS570_POM_PERIPHERALID2_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_POM_PERIPHERALID2_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*------------------TMS570_POMPERIPHERALID3------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_POM_PERIPHERALID3_Reserved(val) BSP_FLD32(val,0, 31)
#define TMS570_POM_PERIPHERALID3_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_POM_PERIPHERALID3_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_POMCOMPONENTID0-------------------*/
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID0_Preamble(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_COMPONENTID0_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_COMPONENTID0_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-------------------TMS570_POMCOMPONENTID1-------------------*/
/* field: Component_Class - CoreSight Component */
#define TMS570_POM_COMPONENTID1_Component_Class(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_COMPONENTID1_Component_Class_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_POM_COMPONENTID1_Component_Class_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID1_Preamble(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_COMPONENTID1_Preamble_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_COMPONENTID1_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-------------------TMS570_POMCOMPONENTID2-------------------*/
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID2_Preamble(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_COMPONENTID2_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_COMPONENTID2_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-------------------TMS570_POMCOMPONENTID3-------------------*/
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID3_Preamble(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_COMPONENTID3_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_COMPONENTID3_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
#endif /* LIBBSP_ARM_tms570_POM */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
+407
View File
@@ -0,0 +1,407 @@
/* The header file is generated by make_header.py from RTI.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_RTI
#define LIBBSP_ARM_tms570_RTI
#include <bsp/utility.h>
typedef struct{
uint32_t COMPx; /*RTI Compare x Register*/
uint32_t UDCPx; /*RTI Update Compare x Register*/
} tms570_rti_compare_t;
typedef struct{
uint32_t FRCx; /*RTI Free Running Counter x Register*/
uint32_t UCx; /*RTI Up Counter x Register*/
uint32_t CPUCx; /*RTI Compare Up Counter x Register*/
uint8_t reserved1 [4];
uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/
uint32_t CAUCx; /*RTI Capture Up Counter x Register*/
uint32_t rsvd[2]; /*Reserved*/
} tms570_rti_counter_t;
typedef struct{
uint32_t GCTRL; /*RTI Global Control Register*/
uint32_t TBCTRL; /*RTI Timebase Control Register*/
uint32_t CAPCTRL; /*RTI Capture Control Register*/
uint32_t COMPCTRL; /*RTI Compare Control Register*/
tms570_rti_counter_t CNT[2];/*Counters*/
tms570_rti_compare_t CMP[4];/*Compares*/
uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/
uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/
uint8_t reserved2 [8];
uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/
uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/
uint32_t INTFLAG; /*RTI Interrupt Flag Register*/
uint8_t reserved3 [4];
uint32_t DWDCTRL; /*Digital Watchdog Control Register*/
uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/
uint32_t WDSTATUS; /*Watchdog Status Register*/
uint32_t WDKEY; /*RTI Watchdog Key Register*/
uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/
uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/
uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/
uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/
uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/
uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/
uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/
uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/
} tms570_rti_t;
/*----------------------TMS570_RTICOMPx----------------------*/
/* field: COMPx - Compare x. */
#define TMS570_RTI_COMPx_COMPx(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_COMPx_COMPx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_COMPx_COMPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_RTIUDCPx----------------------*/
/* field: UDCPx - Update compare x. */
#define TMS570_RTI_UDCPx_UDCPx(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_UDCPx_UDCPx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_UDCPx_UDCPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_RTIFRCx-----------------------*/
/* field: FRC0 - FRC0 */
#define TMS570_RTI_FRCx_FRC0(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_FRCx_FRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_FRCx_FRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_RTIUCx-----------------------*/
/* field: UC0 - Up counter 0. */
#define TMS570_RTI_UCx_UC0(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_UCx_UC0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_UCx_UC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_RTICPUCx----------------------*/
/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
#define TMS570_RTI_CPUCx_CPUC0(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_CPUCx_CPUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_CPUCx_CPUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_RTICAFRCx----------------------*/
/* field: CAFRC0 - Capture free running counter 0. */
#define TMS570_RTI_CAFRCx_CAFRC0(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_CAFRCx_CAFRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_CAFRCx_CAFRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_RTICAUCx----------------------*/
/* field: CAUC0 - Capture up counter 0. */
#define TMS570_RTI_CAUCx_CAUC0(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_CAUCx_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_CAUCx_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_RTIrsvd-----------------------*/
/* field: CAUC0 - Capture up counter 0. */
#define TMS570_RTI_rsvd_CAUC0(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_rsvd_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_rsvd_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_RTIGCTRL----------------------*/
/* field: NTUSEL - Select NTU signal. */
#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: COS - Continue on suspend. */
#define TMS570_RTI_GCTRL_COS BSP_FLD32(15)
/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
#define TMS570_RTI_GCTRL_CNT1EN BSP_FLD32(1)
/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
#define TMS570_RTI_GCTRL_CNT0EN BSP_FLD32(0)
/*----------------------TMS570_RTITBCTRL----------------------*/
/* field: INC - Increment free running counter 0. */
#define TMS570_RTI_TBCTRL_INC BSP_FLD32(1)
/* field: TBEXT - Timebase external. */
#define TMS570_RTI_TBCTRL_TBEXT BSP_FLD32(0)
/*---------------------TMS570_RTICAPCTRL---------------------*/
/* field: CAPCNTR1 - Capture counter 1. */
#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_FLD32(1)
/* field: CAPCNTR0 - Capture counter 0. */
#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_FLD32(0)
/*---------------------TMS570_RTICOMPCTRL---------------------*/
/* field: COMPSEL3 - Compare select 3. */
#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_FLD32(12)
/* field: COMPSEL2 - Compare select 2. */
#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_FLD32(8)
/* field: COMPSEL1 - Compare select 1. */
#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_FLD32(4)
/* field: COMPSEL0 - Compare select 0. */
#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_FLD32(0)
/*---------------------TMS570_RTITBLCOMP---------------------*/
/* field: TBLCOMP - Timebase low compare value. */
#define TMS570_RTI_TBLCOMP_TBLCOMP(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_TBLCOMP_TBLCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_TBLCOMP_TBLCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_RTITBHCOMP---------------------*/
/* field: TBHCOMP - Timebase high compare value. */
#define TMS570_RTI_TBHCOMP_TBHCOMP(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_TBHCOMP_TBHCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_TBHCOMP_TBHCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_RTISETINTENA--------------------*/
/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_FLD32(18)
/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_FLD32(17)
/* field: SETTBINT - Set timebase interrupt. */
#define TMS570_RTI_SETINTENA_SETTBINT BSP_FLD32(16)
/* field: SETDMA3 - Set compare DMA request 3. */
#define TMS570_RTI_SETINTENA_SETDMA3 BSP_FLD32(11)
/* field: SETDMA2 - Set compare DMA request 2. */
#define TMS570_RTI_SETINTENA_SETDMA2 BSP_FLD32(10)
/* field: SETDMA1 - Set compare DMA request 1. */
#define TMS570_RTI_SETINTENA_SETDMA1 BSP_FLD32(9)
/* field: SETDMA0 - Set compare DMA request 0. */
#define TMS570_RTI_SETINTENA_SETDMA0 BSP_FLD32(8)
/* field: SETINT3 - Set compare interrupt 3. */
#define TMS570_RTI_SETINTENA_SETINT3 BSP_FLD32(3)
/* field: SETINT2 - Set compare interrupt 2. */
#define TMS570_RTI_SETINTENA_SETINT2 BSP_FLD32(2)
/* field: SETINT1 - Set compare interrupt 1. */
#define TMS570_RTI_SETINTENA_SETINT1 BSP_FLD32(1)
/* field: SETINT0 - Set compare interrupt 0. */
#define TMS570_RTI_SETINTENA_SETINT0 BSP_FLD32(0)
/*-------------------TMS570_RTICLEARINTENA-------------------*/
/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_FLD32(18)
/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_FLD32(17)
/* field: CLEARTBINT - Clear timebase interrupt. */
#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_FLD32(16)
/* field: CLEARDMA3 - Clear compare DMA request 3. */
#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_FLD32(11)
/* field: CLEARDMA2 - Clear compare DMA request 2. */
#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_FLD32(10)
/* field: CLEARDMA1 - Clear compare DMA request 1. */
#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_FLD32(9)
/* field: CLEARDMA0 - Clear compare DMA request 0. */
#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_FLD32(8)
/* field: CLEARINT3 - Clear compare interrupt 3. */
#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_FLD32(3)
/* field: CLEARINT2 - Clear compare interrupt 2. */
#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_FLD32(2)
/* field: CLEARINT1 - Clear compare interrupt 1. */
#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_FLD32(1)
/* field: CLEARINT0 - Clear compare interrupt 0. */
#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_FLD32(0)
/*---------------------TMS570_RTIINTFLAG---------------------*/
/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
#define TMS570_RTI_INTFLAG_OVL1INT BSP_FLD32(18)
/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
#define TMS570_RTI_INTFLAG_OVL0INT BSP_FLD32(17)
/* field: TBINT - Timebase interrupt flag. */
#define TMS570_RTI_INTFLAG_TBINT BSP_FLD32(16)
/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
#define TMS570_RTI_INTFLAG_INT3 BSP_FLD32(3)
/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
#define TMS570_RTI_INTFLAG_INT2 BSP_FLD32(2)
/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
#define TMS570_RTI_INTFLAG_INT1 BSP_FLD32(1)
/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
#define TMS570_RTI_INTFLAG_INT0 BSP_FLD32(0)
/*---------------------TMS570_RTIDWDCTRL---------------------*/
/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
#define TMS570_RTI_DWDCTRL_DWDCTRL(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_DWDCTRL_DWDCTRL_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_DWDCTRL_DWDCTRL_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_RTIDWDPRLD---------------------*/
/* field: DWDPRLD - Digital Watchdog Preload Value. */
#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_RTIWDSTATUS---------------------*/
/* field: DWWD_ST - Windowed Watchdog Status */
#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_FLD32(5)
/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_FLD32(4)
/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_FLD32(3)
/* field: KEY_ST - Watchdog key status. */
#define TMS570_RTI_WDSTATUS_KEY_ST BSP_FLD32(2)
/* field: DWD_ST - DWD status. */
#define TMS570_RTI_WDSTATUS_DWD_ST BSP_FLD32(1)
/*----------------------TMS570_RTIWDKEY----------------------*/
/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_RTIDWDCNTR---------------------*/
/* field: DWDCNTR - DWD down counter. */
#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
/*--------------------TMS570_RTIWWDRXNCTRL--------------------*/
/* field: WWDRXN - The DWWD reaction */
#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-------------------TMS570_RTIWWDSIZECTRL-------------------*/
/* field: WWDSIZE - The DWWD window size */
#define TMS570_RTI_WWDSIZECTRL_WWDSIZE(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-------------------TMS570_RTIINTCLRENABLE-------------------*/
/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*---------------------TMS570_RTICOMP0CLR---------------------*/
/* field: CMP0CLR - Compare 0 clear. */
#define TMS570_RTI_COMP0CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_COMP0CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_COMP0CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_RTICOMP1CLR---------------------*/
/* field: CMP0CLR - Compare 1 clear. */
#define TMS570_RTI_COMP1CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_COMP1CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_COMP1CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_RTICOMP2CLR---------------------*/
/* field: CMP2CLR - Compare 2 clear. */
#define TMS570_RTI_COMP2CLR_CMP2CLR(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_COMP2CLR_CMP2CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_COMP2CLR_CMP2CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_RTICOMP3CLR---------------------*/
/* field: CMP3CLR - Compare 3 clear. */
#define TMS570_RTI_COMP3CLR_CMP3CLR(val) BSP_FLD32(val,0, 31)
#define TMS570_RTI_COMP3CLR_CMP3CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTI_COMP3CLR_CMP3CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_RTI */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
+230
View File
@@ -0,0 +1,230 @@
/* The header file is generated by make_header.py from RTP.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_RTP
#define LIBBSP_ARM_tms570_RTP
#include <bsp/utility.h>
typedef struct{
uint32_t GLBCTRL; /*RTP Global Control Register*/
uint32_t TRENA; /*RTP Trace Enable Register*/
uint32_t GSR; /*RTP Global Status Register*/
uint32_t RAM1REG1; /*RTP RAM 1 Trace Region 1 Register*/
uint32_t RAM1REG2; /*RTP RAM 1 Trace Region 2 Register*/
uint32_t RAM2REG1; /*RTP RAM 2 Trace Region 1 Register*/
uint32_t RAM2REG2; /*RTP RAM 2 Trace Region 2 Register*/
uint8_t reserved1 [8];
uint32_t PERREG1; /*RTP Peripheral Trace Region 1 Register*/
uint32_t PERREG2; /*RTP Peripheral Trace Region 2 Register*/
uint32_t DDMW; /*RTP Direct Data Mode Write Register*/
uint8_t reserved2 [4];
uint32_t PC0; /*RTP Pin Control 0 Register*/
uint32_t PC1; /*RTP Pin Control 1 Register*/
uint32_t PC2; /*RTP Pin Control 2 Register*/
uint32_t PC3; /*RTP Pin Control 3 Register*/
uint32_t PC4; /*RTP Pin Control 4 Register*/
uint32_t PC5; /*RTP Pin Control 5 Register*/
uint32_t PC6; /*RTP Pin Control 6 Register*/
uint32_t PC7; /*RTP Pin Control 7 Register*/
uint32_t PC8; /*RTP Pin Control 8 Register*/
} tms570_rtp_t;
/*---------------------TMS570_RTPGLBCTRL---------------------*/
/* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */
#define TMS570_RTP_GLBCTRL_TEST BSP_FLD32(24)
/* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */
#define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18)
#define TMS570_RTP_GLBCTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg,16, 18)
#define TMS570_RTP_GLBCTRL_PRESCALER_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
/* field: DDM_WIDTH - Direct data mode word size width. */
#define TMS570_RTP_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,12, 13)
#define TMS570_RTP_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,12, 13)
#define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
/* field: DDM_RW - */
#define TMS570_RTP_GLBCTRL_DDM_RW BSP_FLD32(11)
/* field: TM_DDM - Trace Mode or Direct Data Mode */
#define TMS570_RTP_GLBCTRL_TM_DDM BSP_FLD32(10)
/* field: PW - Port width. This bit field configures the RTP to the desired port width. */
#define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9)
#define TMS570_RTP_GLBCTRL_PW_GET(reg) BSP_FLD32GET(reg,8, 9)
#define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
/* field: RESET - This bit resets the state machine and the registers to their reset value. */
#define TMS570_RTP_GLBCTRL_RESET BSP_FLD32(7)
/* field: CONTCLK - Continuous RTPCLK enable. */
#define TMS570_RTP_GLBCTRL_CONTCLK BSP_FLD32(6)
/* field: HOVF - Halt on overflow. */
#define TMS570_RTP_GLBCTRL_HOVF BSP_FLD32(5)
/* field: INV_RGN - Trace inside or outside of defined trace regions. */
#define TMS570_RTP_GLBCTRL_INV_RGN BSP_FLD32(4)
/* field: ON_OFF - ON/Off switch. */
#define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
#define TMS570_RTP_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*----------------------TMS570_RTPTRENA----------------------*/
/* field: ENA4 - Enable tracing for peripherals. */
#define TMS570_RTP_TRENA_ENA4 BSP_FLD32(24)
/* field: ENA2 - Enable tracing for RAM block 2. */
#define TMS570_RTP_TRENA_ENA2 BSP_FLD32(8)
/* field: ENA1 - */
#define TMS570_RTP_TRENA_ENA1 BSP_FLD32(0)
/*-----------------------TMS570_RTPGSR-----------------------*/
/* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */
#define TMS570_RTP_GSR_EMPTYSER BSP_FLD32(12)
/* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */
#define TMS570_RTP_GSR_EMPTYPER BSP_FLD32(11)
/* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */
#define TMS570_RTP_GSR_EMPTY2 BSP_FLD32(9)
/* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */
#define TMS570_RTP_GSR_EMPTY1 BSP_FLD32(8)
/* field: OVFPER - Overflow peripheral FIFO. */
#define TMS570_RTP_GSR_OVFPER BSP_FLD32(3)
/* field: OVF2 - Overflow RAM block 2 FIFO. */
#define TMS570_RTP_GSR_OVF2 BSP_FLD32(1)
/* field: OVF1 - Overflow RAM block 1 FIFO. */
#define TMS570_RTP_GSR_OVF1 BSP_FLD32(0)
/*---------------------TMS570_RTPRAM1REG1---------------------*/
/* field: CPU_DMA - CPU and/or other master access. */
#define TMS570_RTP_RAM1REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
#define TMS570_RTP_RAM1REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
#define TMS570_RTP_RAM1REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: RW - Read/Write. */
#define TMS570_RTP_RAM1REG1_RW BSP_FLD32(28)
/* field: BLOCKSIZE - These bits define the length of the trace region. */
#define TMS570_RTP_RAM1REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
#define TMS570_RTP_RAM1REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_RTP_RAM1REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
#define TMS570_RTP_RAM1REG1_STARTADDR(val) BSP_FLD32(val,0, 17)
#define TMS570_RTP_RAM1REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
#define TMS570_RTP_RAM1REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
/*---------------------TMS570_RTPRAM2REG1---------------------*/
/* field: CPU_DMA - CPU and/or other master access. */
#define TMS570_RTP_RAM2REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
#define TMS570_RTP_RAM2REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
#define TMS570_RTP_RAM2REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: RW - Read/Write. */
#define TMS570_RTP_RAM2REG1_RW BSP_FLD32(28)
/* field: BLOCKSIZE - These bits define the length of the trace region. */
#define TMS570_RTP_RAM2REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
#define TMS570_RTP_RAM2REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_RTP_RAM2REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
#define TMS570_RTP_RAM2REG1_STARTADDR(val) BSP_FLD32(val,0, 23)
#define TMS570_RTP_RAM2REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_RTP_RAM2REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*---------------------TMS570_RTPPERREG1---------------------*/
/* field: CPU_DMA - CPU and/or other master access. */
#define TMS570_RTP_PERREG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
#define TMS570_RTP_PERREG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
#define TMS570_RTP_PERREG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: RW - Read/Write. */
#define TMS570_RTP_PERREG1_RW BSP_FLD32(28)
/* field: BLOCKSIZE - These bits define the length of the trace region. */
#define TMS570_RTP_PERREG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
#define TMS570_RTP_PERREG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_RTP_PERREG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
#define TMS570_RTP_PERREG1_STARTADDR(val) BSP_FLD32(val,0, 23)
#define TMS570_RTP_PERREG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_RTP_PERREG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*-----------------------TMS570_RTPDDMW-----------------------*/
/* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */
#define TMS570_RTP_DDMW_DATA(val) BSP_FLD32(val,0, 31)
#define TMS570_RTP_DDMW_DATA_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_RTP_DDMW_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*-----------------------TMS570_RTPPC0-----------------------*/
/* field: ENAFUNC - Functional mode of RTPENA pin. */
#define TMS570_RTP_PC0_ENAFUNC BSP_FLD32(18)
/* field: CLKFUNC - Functional mode of RTPCLK pin. */
#define TMS570_RTP_PC0_CLKFUNC BSP_FLD32(17)
/* field: SYNCFUNC - Functional mode of RTPSYNC pin. */
#define TMS570_RTP_PC0_SYNCFUNC BSP_FLD32(16)
/* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */
#define TMS570_RTP_PC0_DATAFUNC(val) BSP_FLD32(val,0, 15)
#define TMS570_RTP_PC0_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_RTP_PC0_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
#endif /* LIBBSP_ARM_tms570_RTP */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
+450
View File
@@ -0,0 +1,450 @@
/* The header file is generated by make_header.py from SCI.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_SCI
#define LIBBSP_ARM_tms570_SCI
#include <bsp/utility.h>
typedef struct{
uint32_t GCR0; /*SCI Global Control Register 0*/
uint32_t GCR1; /*SCI Global Control Register 1*/
uint32_t GCR2; /*SCI Global Control Register 2*/
uint32_t SETINT; /*SCI Set Interrupt Register*/
uint32_t CLEARINT; /*SCI Clear Interrupt Register*/
uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/
uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/
uint32_t FLR; /*SCI Flags Register*/
uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/
uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/
uint32_t FORMAT; /*SCI Format Control Register*/
uint32_t BRS; /*Baud Rate Selection Register*/
uint32_t ED; /*Receiver Emulation Data Buffer*/
uint32_t RD; /*Receiver Data Buffer*/
uint32_t TD; /*Transmit Data Buffer*/
uint32_t PIO0; /*SCI Pin I/O Control Register 0*/
uint32_t PIO1; /*SCI Pin I/O Control Register 1*/
uint32_t PIO2; /*SCI Pin I/O Control Register 2*/
uint32_t PIO3; /*SCI Pin I/O Control Register 3*/
uint32_t PIO4; /*SCI Pin I/O Control Register 4*/
uint32_t PIO5; /*SCI Pin I/O Control Register 5*/
uint32_t PIO6; /*SCI Pin I/O Control Register 6*/
uint32_t PIO7; /*SCI Pin I/O Control Register 7*/
uint32_t PIO8; /*SCI Pin I/O Control Register 8*/
uint8_t reserved1 [48];
uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/
} tms570_sci_t;
/*-----------------------TMS570_SCIGCR0-----------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
/* field: RESET - This bit resets the SCI module. */
#define TMS570_SCI_GCR0_RESET BSP_FLD32(0)
/*-----------------------TMS570_SCIGCR1-----------------------*/
/* field: TXENA - Transmit enable. */
#define TMS570_SCI_GCR1_TXENA BSP_FLD32(25)
/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
#define TMS570_SCI_GCR1_RXENA BSP_FLD32(24)
/* field: CONT - Continue on suspend. */
#define TMS570_SCI_GCR1_CONT BSP_FLD32(17)
/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
#define TMS570_SCI_GCR1_LOOP_BACK BSP_FLD32(16)
/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
#define TMS570_SCI_GCR1_POWERDOWN BSP_FLD32(9)
/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
#define TMS570_SCI_GCR1_SLEEP BSP_FLD32(8)
/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
#define TMS570_SCI_GCR1_SWnRST BSP_FLD32(7)
/* field: CLOCK - CLOCK */
#define TMS570_SCI_GCR1_CLOCK BSP_FLD32(5)
/* field: STOP - SCI number of stop bits per frame. */
#define TMS570_SCI_GCR1_STOP BSP_FLD32(4)
/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
#define TMS570_SCI_GCR1_PARITY BSP_FLD32(3)
/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
#define TMS570_SCI_GCR1_PARITY_ENA BSP_FLD32(2)
/* field: TIMING_MODE - SCI timing mode bit. */
#define TMS570_SCI_GCR1_TIMING_MODE BSP_FLD32(1)
/* field: COMM_MODE - SCI communication mode bit. */
#define TMS570_SCI_GCR1_COMM_MODE BSP_FLD32(0)
/*-----------------------TMS570_SCIGCR2-----------------------*/
/* field: CC - Compare checksum. LIN mode only. */
#define TMS570_SCI_GCR2_CC BSP_FLD32(17)
/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
#define TMS570_SCI_GCR2_SC BSP_FLD32(16)
/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
#define TMS570_SCI_GCR2_GEN_WU BSP_FLD32(8)
/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
#define TMS570_SCI_GCR2_POWERDOWN BSP_FLD32(0)
/*----------------------TMS570_SCISETINT----------------------*/
/* field: SET_FE_INT - */
#define TMS570_SCI_SETINT_SET_FE_INT BSP_FLD32(26)
/* field: SET_OE_INT - SET OE INT */
#define TMS570_SCI_SETINT_SET_OE_INT BSP_FLD32(25)
/* field: SET_PE_INT - Set parity interrupt. */
#define TMS570_SCI_SETINT_SET_PE_INT BSP_FLD32(24)
/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
/* field: SET_RX_DMA - SET RX DMA */
#define TMS570_SCI_SETINT_SET_RX_DMA BSP_FLD32(17)
/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
#define TMS570_SCI_SETINT_SET_TX_DMA BSP_FLD32(16)
/* field: SET_RX_INT - SET RX INT */
#define TMS570_SCI_SETINT_SET_RX_INT BSP_FLD32(9)
/* field: SET_TX_INT - Set transmitter interrupt. */
#define TMS570_SCI_SETINT_SET_TX_INT BSP_FLD32(8)
/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_FLD32(0)
/*---------------------TMS570_SCICLEARINT---------------------*/
/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_FLD32(26)
/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_FLD32(25)
/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_FLD32(24)
/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
/* field: CLR_TX_DMA - CLR TX DMA */
#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_FLD32(9)
/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_FLD32(8)
/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
/*--------------------TMS570_SCISETINTLVL--------------------*/
/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
/*-------------------TMS570_SCICLEARINTLVL-------------------*/
/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
/* field: CLR_PE_INT_LVL - */
#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
#define TMS570_SCI_CLEARINTLVL_8 BSP_FLD32(8)
/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
/*-----------------------TMS570_SCIFLR-----------------------*/
/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
#define TMS570_SCI_FLR_FE BSP_FLD32(26)
/* field: OE - Overrun error flag. */
#define TMS570_SCI_FLR_OE BSP_FLD32(25)
/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
#define TMS570_SCI_FLR_PE BSP_FLD32(24)
/* field: RXWAKE - Receiver wakeup detect flag. */
#define TMS570_SCI_FLR_RXWAKE BSP_FLD32(12)
/* field: TX_EMPTY - Transmitter empty flag. */
#define TMS570_SCI_FLR_TX_EMPTY BSP_FLD32(11)
/* field: TXWAKE - Transmitter wakeup method select. */
#define TMS570_SCI_FLR_TXWAKE BSP_FLD32(10)
/* field: RXRDY - Receiver ready flag. */
#define TMS570_SCI_FLR_RXRDY BSP_FLD32(9)
/* field: TXRDY - Transmitter buffer register ready flag. */
#define TMS570_SCI_FLR_TXRDY BSP_FLD32(8)
/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
#define TMS570_SCI_FLR_BUSY BSP_FLD32(3)
/* field: IDLE - SCI receiver in idle state. */
#define TMS570_SCI_FLR_IDLE BSP_FLD32(2)
/* field: WAKEUP - Wakeup flag. */
#define TMS570_SCI_FLR_WAKEUP BSP_FLD32(1)
/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
#define TMS570_SCI_FLR_BRKDT BSP_FLD32(0)
/*---------------------TMS570_SCIINTVECT0---------------------*/
/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*---------------------TMS570_SCIINTVECT1---------------------*/
/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*----------------------TMS570_SCIFORMAT----------------------*/
/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
/*-----------------------TMS570_SCIBRS-----------------------*/
/* field: BAUD - SCI 24-bit baud selection. */
#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23)
#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
/*------------------------TMS570_SCIED------------------------*/
/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7)
#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*------------------------TMS570_SCIRD------------------------*/
/* field: RD - Receiver data. */
#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7)
#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*------------------------TMS570_SCITD------------------------*/
/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7)
#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*-----------------------TMS570_SCIPIO0-----------------------*/
/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
#define TMS570_SCI_PIO0_TX_FUNC BSP_FLD32(2)
/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
#define TMS570_SCI_PIO0_RX_FUNC BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO1-----------------------*/
/* field: TX_DIR - Transmit pin direction. */
#define TMS570_SCI_PIO1_TX_DIR BSP_FLD32(2)
/* field: RX_DIR - Receive pin direction. */
#define TMS570_SCI_PIO1_RX_DIR BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO2-----------------------*/
/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
#define TMS570_SCI_PIO2_TX_IN BSP_FLD32(2)
/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
#define TMS570_SCI_PIO2_RX_IN BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO3-----------------------*/
/* field: TX_OUT - Transmit pin out. */
#define TMS570_SCI_PIO3_TX_OUT BSP_FLD32(2)
/* field: RX_OUT - Receive pin out. */
#define TMS570_SCI_PIO3_RX_OUT BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO4-----------------------*/
/* field: TX_SET - Transmit pin set. */
#define TMS570_SCI_PIO4_TX_SET BSP_FLD32(2)
/* field: RX_SET - Receive pin set. */
#define TMS570_SCI_PIO4_RX_SET BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO5-----------------------*/
/* field: TX_CLR - Transmit pin clear. */
#define TMS570_SCI_PIO5_TX_CLR BSP_FLD32(2)
/* field: RX_CLR - Receive pin clear. */
#define TMS570_SCI_PIO5_RX_CLR BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO6-----------------------*/
/* field: TX_PDR - Transmit pin open drain enable. */
#define TMS570_SCI_PIO6_TX_PDR BSP_FLD32(2)
/* field: RX_PDR - Receive pin open drain enable. */
#define TMS570_SCI_PIO6_RX_PDR BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO7-----------------------*/
/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
#define TMS570_SCI_PIO7_TX_PD BSP_FLD32(2)
/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
#define TMS570_SCI_PIO7_RX_PD BSP_FLD32(1)
/*-----------------------TMS570_SCIPIO8-----------------------*/
/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
#define TMS570_SCI_PIO8_TX_PSL BSP_FLD32(2)
/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
#define TMS570_SCI_PIO8_RX_PSL BSP_FLD32(1)
/*--------------------TMS570_SCIIODFTCTRL--------------------*/
/* field: FEN - Frame error enable. This bit is used to create a frame error. */
#define TMS570_SCI_IODFTCTRL_FEN BSP_FLD32(26)
/* field: PEN - Parity error enable. This bit is used to create a parity error. */
#define TMS570_SCI_IODFTCTRL_PEN BSP_FLD32(25)
/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
/* field: PIN_SAMPLE_MASK - Pin sample mask. */
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20)
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20)
/* field: TX_SHIFT - Transmit shift. */
#define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18)
#define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18)
#define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */
#define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11)
#define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
#define TMS570_SCI_IODFTCTRL_LPBENA BSP_FLD32(1)
/* field: RXPENA - Module analog loopback through receive pin enable. */
#define TMS570_SCI_IODFTCTRL_RXPENA BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_SCI */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
+918
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
+188
View File
@@ -0,0 +1,188 @@
/* The header file is generated by make_header.py from STC.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_STC
#define LIBBSP_ARM_tms570_STC
#include <bsp/utility.h>
typedef struct{
uint32_t STCGCR0; /*STC Global Control Register 0*/
uint32_t STCGCR1; /*STCGlobal Control Register 1*/
uint32_t STCTPR; /*Self-Test Run Timeout Counter Preload Register*/
uint32_t STC_CADDR; /*STC Current ROM Address Register*/
uint32_t STCCICR; /*STC Current Interval Count Register*/
uint32_t STCGSTAT; /*Self-Test Global Status Register*/
uint32_t STCFSTAT; /*Self-Test Fail Status Register*/
uint32_t CPU1_CURMISR3; /*CPU1 Current MISR Register 3*/
uint32_t CPU1_CURMISR2; /*CPU1 Current MISR Register 2*/
uint32_t CPU1_CURMISR1; /*CPU1 Current MISR Register 1*/
uint32_t CPU1_CURMISR0; /*CPU1 Current MISR Register 0*/
uint32_t CPU2_CURMISR3; /*CPU2 Current MISR Register 3*/
uint32_t CPU2_CURMISR2; /*CPU2 Current MISR Register 2*/
uint32_t CPU2_CURMISR1; /*CPU2 Current MISR Register 1*/
uint32_t CPU2_CURMISR0; /*CPU2 Current MISR Register 0*/
uint32_t STCSCSCR; /*Signature Compare Self-Check Register*/
} tms570_stc_t;
/*---------------------TMS570_STCSTCGCR0---------------------*/
/* field: INTCOUNT - Number of intervals of self-test run */
#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
/* field: RS_CNT - Restart or Continue */
#define TMS570_STC_STCGCR0_RS_CNT BSP_FLD32(0)
/*---------------------TMS570_STCSTCGCR1---------------------*/
/* field: STC_ENA - Self-test run enable key */
#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*----------------------TMS570_STCSTCTPR----------------------*/
/* field: RTOD - Self-test timeout count preload */
#define TMS570_STC_STCTPR_RTOD(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_STCTPR_RTOD_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_STCTPR_RTOD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_STCSTC_CADDR--------------------*/
/* field: ADDR - Current ROM Address */
#define TMS570_STC_STC_CADDR_ADDR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_STC_CADDR_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_STC_CADDR_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_STCSTCCICR---------------------*/
/* field: N - Interval Number */
#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*---------------------TMS570_STCSTCGSTAT---------------------*/
/* field: TEST_FAIL - Test Fail */
#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_FLD32(1)
/* field: TEST_DONE - Test Done */
#define TMS570_STC_STCGSTAT_TEST_DONE BSP_FLD32(0)
/*---------------------TMS570_STCSTCFSTAT---------------------*/
/* field: TO_ERR - Timeout Error */
#define TMS570_STC_STCFSTAT_TO_ERR BSP_FLD32(2)
/* field: CPU2_FAIL - CPU2 failure info */
#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_FLD32(1)
/* field: CPU1_FAIL - CPU1 failure info */
#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_FLD32(0)
/*------------------TMS570_STCCPU1_CURMISR3------------------*/
/* field: MISR - MISR data from CPU1 */
#define TMS570_STC_CPU1_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU1_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU1_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU1_CURMISR2------------------*/
/* field: MISR - MISR data from CPU1 */
#define TMS570_STC_CPU1_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU1_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU1_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU1_CURMISR1------------------*/
/* field: MISR - MISR data from CPU1 */
#define TMS570_STC_CPU1_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU1_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU1_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU1_CURMISR0------------------*/
/* field: MISR - MISR data from CPU1 */
#define TMS570_STC_CPU1_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU1_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU1_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU2_CURMISR3------------------*/
/* field: MISR - MISR data from CPU2 */
#define TMS570_STC_CPU2_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU2_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU2_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU2_CURMISR2------------------*/
/* field: MISR - MISR data from CPU2 */
#define TMS570_STC_CPU2_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU2_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU2_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU2_CURMISR1------------------*/
/* field: MISR - MISR data from CPU2 */
#define TMS570_STC_CPU2_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU2_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU2_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*------------------TMS570_STCCPU2_CURMISR0------------------*/
/* field: MISR - MISR data from CPU2 */
#define TMS570_STC_CPU2_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
#define TMS570_STC_CPU2_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_STC_CPU2_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_STCSTCSCSCR---------------------*/
/* field: FAULT_INS - Enable / Disable fault insertion. */
#define TMS570_STC_STCSCSCR_FAULT_INS BSP_FLD32(4)
/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
#endif /* LIBBSP_ARM_tms570_STC */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
+704
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
+173
View File
@@ -0,0 +1,173 @@
/* The header file is generated by make_header.py from SYS2.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_SYS2
#define LIBBSP_ARM_tms570_SYS2
#include <bsp/utility.h>
typedef struct{
uint32_t PLLCTL3; /*PLL Control Register 3*/
uint8_t reserved1 [4];
uint32_t STCCLKDIV; /*CPU Logic BIST Clock Divider*/
uint8_t reserved2 [24];
uint32_t ECPCNTL; /*ECP Control Register*/
uint8_t reserved3 [20];
uint32_t CLK2CNTRL; /*Clock 2 Control Register*/
uint32_t VCLKACON1; /*Peripheral Asynchronous Clock Configuration 1 Register*/
uint8_t reserved4 [44];
uint32_t CLKSLIP; /*Clock Slip Register*/
uint8_t reserved5 [120];
uint32_t EFC_CTLREG; /*EFUSE Controller Control Register*/
uint32_t DIEDL_REG0; /*Die Identification Register*/
uint32_t DIEDH_REG1; /*Die Identification Register*/
uint32_t DIEDL_REG2; /*Die Identification Register*/
uint32_t DIEDH_REG3; /*Die Identification Register*/
} tms570_sys2_t;
/*---------------------TMS570_SYS2PLLCTL3---------------------*/
/* field: ODPLL2 - Internal PLL Output Divider */
#define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
#define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
#define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
/* field: PLLDIV2 - PLL2 Output Clock Divider */
#define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
#define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
#define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: REFCLKDIV2 - REFCLKDIV2 */
#define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
/* field: PLLMUL2 - PLL2 Multiplication Factor */
#define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
#define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*--------------------TMS570_SYS2STCCLKDIV--------------------*/
/* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */
#define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26)
#define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26)
#define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
/*---------------------TMS570_SYS2ECPCNTL---------------------*/
/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_FLD32(24)
/* field: ECPCOS - ECP continue on suspend. */
#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_FLD32(23)
/* field: ECPINSEL - Select ECP input clock source. */
#define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
#define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
#define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
/* field: ECPDIV - ECP divider value. */
#define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
#define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*--------------------TMS570_SYS2CLK2CNTRL--------------------*/
/* field: VCLK3R - VBUS clock3 ratio. */
#define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*--------------------TMS570_SYS2VCLKACON1--------------------*/
/* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */
#define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26)
#define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26)
#define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
/* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */
#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_FLD32(20)
/* field: VCLKA4S - Peripheral asynchronous clock4 source. */
#define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19)
#define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */
#define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10)
#define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10)
#define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */
#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_FLD32(4)
/* field: VCLKA3S - Peripheral asynchronous clock3 source. */
#define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*---------------------TMS570_SYS2CLKSLIP---------------------*/
/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-------------------TMS570_SYS2EFC_CTLREG-------------------*/
/* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */
#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-------------------TMS570_SYS2DIEDL_REG0-------------------*/
/* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */
#define TMS570_SYS2_DIEDL_REG0_DIE(val) BSP_FLD32(val,0, 31)
#define TMS570_SYS2_DIEDL_REG0_DIE_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_SYS2_DIEDL_REG0_DIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
#endif /* LIBBSP_ARM_tms570_SYS2 */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
+84
View File
@@ -0,0 +1,84 @@
/* The header file is generated by make_header.py from TCR.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_TCR
#define LIBBSP_ARM_tms570_TCR
#include <bsp/utility.h>
typedef struct{
uint32_t TCR[128]; /*Transfer Configuration RAM*/
uint32_t TCR_Parity[128]; /*TCR Parity Test Mode*/
} tms570_tcr_t;
/*-----------------------TMS570_TCRTCR-----------------------*/
/* field: STXR - Set Transmit Request. */
#define TMS570_TCR_TCR_STXR BSP_FLD32(18)
/* field: THTSM - Transfer Header to System Memory. */
#define TMS570_TCR_TCR_THTSM BSP_FLD32(17)
/* field: TPTSM - Transfer Payload to System Memory. */
#define TMS570_TCR_TCR_TPTSM BSP_FLD32(16)
/* field: THTCC - Transfer Header to Communication Controller. */
#define TMS570_TCR_TCR_THTCC BSP_FLD32(15)
/* field: TPTCC - Transfer Payload to Communication Controller. */
#define TMS570_TCR_TCR_TPTCC BSP_FLD32(14)
/* field: TSO - Transfer Start Offset. */
#define TMS570_TCR_TCR_TSO(val) BSP_FLD32(val,0, 13)
#define TMS570_TCR_TCR_TSO_GET(reg) BSP_FLD32GET(reg,0, 13)
#define TMS570_TCR_TCR_TSO_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
/*--------------------TMS570_TCRTCR_Parity--------------------*/
/* field: PAB2 - Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). */
#define TMS570_TCR_TCR_Parity_PAB2 BSP_FLD32(16)
/* field: PAB1 - Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8). */
#define TMS570_TCR_TCR_Parity_PAB1 BSP_FLD32(8)
/* field: PAB0 - Parity Bit for Byte 0. */
#define TMS570_TCR_TCR_Parity_PAB0 BSP_FLD32(0)
#endif /* LIBBSP_ARM_tms570_TCR */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
+170
View File
@@ -0,0 +1,170 @@
/* The header file is generated by make_header.py from TCRAM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_TCRAM
#define LIBBSP_ARM_tms570_TCRAM
#include <bsp/utility.h>
typedef struct{
uint32_t RAMCTRL; /*TCRAM Module Control Register*/
uint32_t RAMTHRESHOLD; /*TCRAM Module Single-Bit Error Correction Threshold Register*/
uint32_t RAMOCCUR; /*TCRAM Module Single-Bit Error Occurrences Control Register*/
uint32_t RAMINTCTRL; /*TCRAM Module Interrupt Control Register*/
uint32_t RAMERRSTATUS; /*TCRAM Module Error Status Register*/
uint32_t RAMSERRADDR; /*TCRAM Module Single-Bit Error Address Register*/
uint8_t reserved1 [4];
uint32_t RAMUERRADDR; /*TCRAM Module Uncorrectable Error Address Register*/
uint8_t reserved2 [16];
uint32_t RAMTEST; /*TCRAM Module Test Mode Control Register*/
uint8_t reserved3 [4];
uint32_t RAMADDRDECVECT; /*TCRAM Module Test Mode Vector Register*/
uint32_t RAMPERADDR; /*TCRAM Module Parity Error Address Register*/
} tms570_tcram_t;
/*--------------------TMS570_TCRAMRAMCTRL--------------------*/
/* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */
#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_FLD32(30)
/* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27)
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19)
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: ECC_WR_EN - ECC Memory Write Enable. */
#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_FLD32(8)
/* field: ECC_DETECT_EN - ECC Detect Enable. */
#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3)
#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*------------------TMS570_TCRAMRAMTHRESHOLD------------------*/
/* field: THRESHOLD - Single-bit Error Threshold Count. */
#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15)
#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*--------------------TMS570_TCRAMRAMOCCUR--------------------*/
/* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */
#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15)
#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_TCRAMRAMINTCTRL-------------------*/
/* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */
#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_FLD32(0)
/*------------------TMS570_TCRAMRAMERRSTATUS------------------*/
/* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */
#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_FLD32(9)
/* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */
#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_FLD32(8)
/* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */
#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_FLD32(5)
/* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */
#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_FLD32(4)
/* field: ADDR_DEC_FAIL - Address decode failed. */
#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_FLD32(2)
/* field: SERR - Single Error Status. */
#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_FLD32(0)
/*------------------TMS570_TCRAMRAMSERRADDR------------------*/
/* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */
#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17)
#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17)
#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17)
/*------------------TMS570_TCRAMRAMUERRADDR------------------*/
/* field: UNCORRECTABLE - address parity error. */
#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22)
#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22)
#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
/*--------------------TMS570_TCRAMRAMTEST--------------------*/
/* field: TRIGGER - Test Trigger. */
#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_FLD32(8)
/* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */
#define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7)
#define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7)
#define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
/* field: TEST_ENABLE - Test Enable. */
#define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3)
#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*-----------------TMS570_TCRAMRAMADDRDECVECT-----------------*/
/* field: ECC_SELECT - ECC Select. */
#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_FLD32(26)
/* field: RAM_CHIP_SELECT - RAM Chip Select. */
#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15)
#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
/*-------------------TMS570_TCRAMRAMPERADDR-------------------*/
/* field: ADDRESS_PARITY - Parity Error Address. */
#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22)
#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22)
#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
#endif /* LIBBSP_ARM_tms570_TCRAM */
c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
+217
View File
@@ -0,0 +1,217 @@
/* The header file is generated by make_header.py from VIM.json */
/* Current script's version can be found at: */
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
/*
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
*
* Czech Technical University in Prague
* Zikova 1903/4
* 166 36 Praha 6
* Czech Republic
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are those
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
#ifndef LIBBSP_ARM_tms570_VIM
#define LIBBSP_ARM_tms570_VIM
#include <bsp/utility.h>
typedef struct{
uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/
uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/
uint32_t ADDERR; /*Address Parity Error Register*/
uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/
uint8_t reserved1 [4];
uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/
uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/
uint8_t reserved2 [8];
uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/
uint8_t reserved3 [4];
uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/
uint8_t reserved4 [4];
uint32_t REQENASET[3]; /*Interrupt Enable Set Register */
uint8_t reserved5 [4];
uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */
uint8_t reserved6 [4];
uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/
uint8_t reserved7 [4];
uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/
uint8_t reserved8 [4];
uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/
uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/
uint32_t CAPEVT; /*Capture Event Register*/
uint8_t reserved9 [4];
uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/
} tms570_vim_t;
/*----------------------TMS570_VIMPARFLG----------------------*/
/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
#define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0)
/*----------------------TMS570_VIMPARCTL----------------------*/
/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
#define TMS570_VIM_PARCTL_TEST BSP_FLD32(8)
/* field: PARENA - VIM parity enable. */
#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
/*----------------------TMS570_VIMADDERR----------------------*/
/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31)
/* field: ADDERR - Address parity error register. */
#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8)
#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8)
#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8)
/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */
#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1)
#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
/*---------------------TMS570_VIMFBPARERR---------------------*/
/* field: FBPARERR - Fall back address parity error. */
#define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*---------------------TMS570_VIMIRQINDEX---------------------*/
/* field: IRQINDEX - IRQ index vector. */
#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*---------------------TMS570_VIMFIQINDEX---------------------*/
/* field: FIQINDEX - FIQ index offset vector. */
#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
/*----------------------TMS570_VIMFIRQPR----------------------*/
/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
#define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_VIMINTREQ----------------------*/
/* field: INTREQx - Pending interrupt bits. 96 bit register. */
#define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMREQENASET--------------------*/
/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
#define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMREQENACLR--------------------*/
/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
#define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMWAKEENASET--------------------*/
/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
#define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMWAKEENACLR--------------------*/
/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
#define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMIRQVECREG--------------------*/
/* field: IRQVECREG - IRQ interrupt vector register. */
#define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*--------------------TMS570_VIMFIQVECREG--------------------*/
/* field: FIQVECREG - FIQ interrupt vector register. */
#define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31)
#define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
#define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
/*----------------------TMS570_VIMCAPEVT----------------------*/
/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */
#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6)
#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
/*---------------------TMS570_VIMCHANCTRL---------------------*/
/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22)
#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22)
#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14)
#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14)
#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6)
#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
#endif /* LIBBSP_ARM_tms570_VIM */