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2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>

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* cpu_asm.S: Fixed exception return address, modified FP context
	switch so FPU is properly enabled and also doesn't screw up the
	exception FP handling.
	* idtcpu.h: Added C0_TAR, the MIPS target address register used for
	returning from exceptions.
	* iregdef.h: Added R_TAR to the stack frame so the target address
	can be saved on a per-exception basis.  The new entry is past the
	end of the frame gdb cares about, so doesn't affect gdb or cpu.h
	stuff.
	* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
	to obtain FPU defines without systax errors generated by the C
	defintions.
	* cpu.c: Improved interrupt level saves & restores.
This commit is contained in:
Joel Sherrill
2002-03-01 16:21:12 +00:00
parent f9d1afc056
commit bd1ecb00d9
14 changed files with 588 additions and 266 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/exec/score/cpu/mips/ChangeLog
+16
View File
@@ -1,3 +1,19 @@
2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed exception return address, modified FP context
switch so FPU is properly enabled and also doesn't screw up the
exception FP handling.
* idtcpu.h: Added C0_TAR, the MIPS target address register used for
returning from exceptions.
* iregdef.h: Added R_TAR to the stack frame so the target address
can be saved on a per-exception basis. The new entry is past the
end of the frame gdb cares about, so doesn't affect gdb or cpu.h
stuff.
* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
to obtain FPU defines without systax errors generated by the C
defintions.
* cpu.c: Improved interrupt level saves & restores.
2002-02-08 Joel Sherrill <joel@OARcorp.com>
* iregdef.h, rtems/score/cpu.h: Reordered register in the
c/src/exec/score/cpu/mips/cpu.c
+23 -8
View File
@@ -1,6 +1,12 @@
/*
* Mips CPU Dependent Source
*
* 2002: Greg Menke (gregory.menke@gsfc.nasa.gov)
* Overhauled interrupt level and interrupt enable/disable code
* to more exactly support MIPS. Our mods were for MIPS1 processors
* MIPS3 ports are affected, though apps written to the old behavior
* should still work OK.
*
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
* Joel Sherrill <joel@OARcorp.com>.
*
@@ -74,24 +80,28 @@ void _CPU_Initialize(
*
* This routine returns the current interrupt level.
*/
unsigned32 _CPU_ISR_Get_level( void )
{
unsigned int sr;
mips_get_sr(sr);
//printf("current sr=%08X, ",sr);
#if __mips == 3
/* EXL bit and shift down hardware ints into bits 1 thru 6 */
return ((sr & SR_EXL) >> 1) + ((sr & 0xfc00) >> 9);
sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9);
#elif __mips == 1
/* IEC bit and shift down hardware ints into bits 1 thru 6 */
return (sr & SR_IEC) + ((sr & 0xfc00) >> 9);
sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
#else
#error "CPU ISR level: unknown MIPS level for SR handling"
#endif
//printf("intlevel=%02X\n",sr);
return sr;
}
@@ -108,16 +118,17 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
** off since, so we'll just leave them alone.
*/
new_level &= 0xff;
mips_get_sr(sr);
#if __mips == 3
mips_set_sr(sr & ~SR_IE); /* first disable ie bit (recommended) */
mips_set_sr( (sr & ~SR_IE) ); /* first disable ie bit (recommended) */
srbits = sr & ~(0xfc00 | SR_EXL | SR_IE);
sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \
(((new_level<<9) & 0xfc000) | \
(((new_level<<9) & 0xfc00) | \
(new_level & 1)?(SR_EXL | SR_IE):0));
/*
if ( (new_level & SR_EXL) == (sr & SR_EXL) )
@@ -134,16 +145,20 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
*/
#elif __mips == 1
mips_set_sr( (sr & ~SR_IEC) );
mips_set_sr( (sr & ~SR_IEC) );
srbits = sr & ~(0xfc00 | SR_IEC);
sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc000) | (new_level & 1)));
//printf("current sr=%08X, newlevel=%02X, srbits=%08X, ",sr,new_level,srbits);
sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
(new_level & SR_IEC)));
//printf("new sr=%08X\n",sr);
#else
#error "CPU ISR level: unknown MIPS level for SR handling"
#endif
mips_set_sr( sr );
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
c/src/exec/score/cpu/mips/cpu_asm.S
+200 -95
View File
File diff suppressed because it is too large Load Diff
c/src/exec/score/cpu/mips/idtcpu.h
+5
View File
@@ -362,6 +362,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_BT 0x40000000 /* Branch Taken */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
@@ -393,6 +394,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_WIRED $6 /* number of wired tlb entries */
#endif
#if __mips == 1
#define C0_TAR $6
#endif
#define C0_BADVADDR $8 /* bad virtual address */
#if __mips == 3
c/src/exec/score/cpu/mips/iregdef.h
+21 -18
View File
@@ -225,39 +225,42 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define R_FCSR 70
#define R_FEIR 71
#define R_TLBHI 72
#if __mips == 1
#define R_TLBLO 73
#endif
#if __mips == 3
#define R_TLBLO0 74
#define R_TLBLO0 73
#endif
#define R_INX 74
#define R_RAND 75
#define R_CTXT 76
#define R_EXCTYPE 77
#define R_MODE 78
#define R_PRID 79
#define R_TAR 80
#if __mips == 1
#define NREGS 80
#define NREGS 81
#endif
#if __mips == 3
#define R_TLBLO1 80
#define R_PAGEMASK 81
#define R_WIRED 82
#define R_COUNT 83
#define R_COMPARE 84
#define R_CONFIG 85
#define R_LLADDR 86
#define R_WATCHLO 87
#define R_WATCHHI 88
#define R_ECC 89
#define R_CACHEERR 90
#define R_TAGLO 91
#define R_TAGHI 92
#define R_ERRPC 93
#define R_XCTXT 94 /* Ketan added from SIM64bit */
#define R_TLBLO1 81
#define R_PAGEMASK 82
#define R_WIRED 83
#define R_COUNT 84
#define R_COMPARE 85
#define R_CONFIG 86
#define R_LLADDR 87
#define R_WATCHLO 88
#define R_WATCHHI 89
#define R_ECC 90
#define R_CACHEERR 91
#define R_TAGLO 92
#define R_TAGHI 93
#define R_ERRPC 94
#define R_XCTXT 95 /* Ketan added from SIM64bit */
#define NREGS 95
#define NREGS 96
#endif
/*
c/src/exec/score/cpu/mips/rtems/score/cpu.h
+16 -3
View File
@@ -314,7 +314,7 @@ extern "C" {
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_MODES_INTERRUPT_MASK 0x000000ff
/*
* Processor defined structures
@@ -360,6 +360,8 @@ extern "C" {
* a debugger such as gdb. But that is another problem.
*/
#ifndef ASSEMBLY_ONLY
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
#if __mips == 1
#define __MIPS_REGISTER_TYPE unsigned32
@@ -595,6 +597,7 @@ typedef struct {
unsigned32 clicks_per_microsecond;
} rtems_cpu_table;
/*
* Macros to access required entires in the CPU Table are in
* the file rtems/system.h.
@@ -647,6 +650,8 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* NOTE: Not needed on this port.
*/
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
@@ -686,6 +691,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32))
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
@@ -845,9 +851,11 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
#if __mips == 3
#define _INTON (SR_EXL | SR_IE)
#define _EXTRABITS 0
#endif
#if __mips == 1
#define _INTON SR_IEC
#define _INTON SR_IEC
#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */
#endif
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
@@ -862,7 +870,7 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
0x300 | \
((_intlvl & 1)?_INTON:0)) ) | \
SR_CU0 | ((_is_fp)?SR_CU1:0); \
SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
}
@@ -1178,6 +1186,11 @@ static inline unsigned int CPU_swap_u32(
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
#endif
#ifdef __cplusplus
}
#endif
cpukit/score/cpu/mips/ChangeLog
+16
View File
@@ -1,3 +1,19 @@
2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed exception return address, modified FP context
switch so FPU is properly enabled and also doesn't screw up the
exception FP handling.
* idtcpu.h: Added C0_TAR, the MIPS target address register used for
returning from exceptions.
* iregdef.h: Added R_TAR to the stack frame so the target address
can be saved on a per-exception basis. The new entry is past the
end of the frame gdb cares about, so doesn't affect gdb or cpu.h
stuff.
* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
to obtain FPU defines without systax errors generated by the C
defintions.
* cpu.c: Improved interrupt level saves & restores.
2002-02-08 Joel Sherrill <joel@OARcorp.com>
* iregdef.h, rtems/score/cpu.h: Reordered register in the
cpukit/score/cpu/mips/cpu.c
+23 -8
View File
@@ -1,6 +1,12 @@
/*
* Mips CPU Dependent Source
*
* 2002: Greg Menke (gregory.menke@gsfc.nasa.gov)
* Overhauled interrupt level and interrupt enable/disable code
* to more exactly support MIPS. Our mods were for MIPS1 processors
* MIPS3 ports are affected, though apps written to the old behavior
* should still work OK.
*
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
* Joel Sherrill <joel@OARcorp.com>.
*
@@ -74,24 +80,28 @@ void _CPU_Initialize(
*
* This routine returns the current interrupt level.
*/
unsigned32 _CPU_ISR_Get_level( void )
{
unsigned int sr;
mips_get_sr(sr);
//printf("current sr=%08X, ",sr);
#if __mips == 3
/* EXL bit and shift down hardware ints into bits 1 thru 6 */
return ((sr & SR_EXL) >> 1) + ((sr & 0xfc00) >> 9);
sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9);
#elif __mips == 1
/* IEC bit and shift down hardware ints into bits 1 thru 6 */
return (sr & SR_IEC) + ((sr & 0xfc00) >> 9);
sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
#else
#error "CPU ISR level: unknown MIPS level for SR handling"
#endif
//printf("intlevel=%02X\n",sr);
return sr;
}
@@ -108,16 +118,17 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
** off since, so we'll just leave them alone.
*/
new_level &= 0xff;
mips_get_sr(sr);
#if __mips == 3
mips_set_sr(sr & ~SR_IE); /* first disable ie bit (recommended) */
mips_set_sr( (sr & ~SR_IE) ); /* first disable ie bit (recommended) */
srbits = sr & ~(0xfc00 | SR_EXL | SR_IE);
sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \
(((new_level<<9) & 0xfc000) | \
(((new_level<<9) & 0xfc00) | \
(new_level & 1)?(SR_EXL | SR_IE):0));
/*
if ( (new_level & SR_EXL) == (sr & SR_EXL) )
@@ -134,16 +145,20 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
*/
#elif __mips == 1
mips_set_sr( (sr & ~SR_IEC) );
mips_set_sr( (sr & ~SR_IEC) );
srbits = sr & ~(0xfc00 | SR_IEC);
sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc000) | (new_level & 1)));
//printf("current sr=%08X, newlevel=%02X, srbits=%08X, ",sr,new_level,srbits);
sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
(new_level & SR_IEC)));
//printf("new sr=%08X\n",sr);
#else
#error "CPU ISR level: unknown MIPS level for SR handling"
#endif
mips_set_sr( sr );
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
cpukit/score/cpu/mips/cpu_asm.S
+200 -95
View File
File diff suppressed because it is too large Load Diff
cpukit/score/cpu/mips/idtcpu.h
+5
View File
@@ -362,6 +362,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_BT 0x40000000 /* Branch Taken */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
@@ -393,6 +394,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_WIRED $6 /* number of wired tlb entries */
#endif
#if __mips == 1
#define C0_TAR $6
#endif
#define C0_BADVADDR $8 /* bad virtual address */
#if __mips == 3
cpukit/score/cpu/mips/iregdef.h
+21 -18
View File
@@ -225,39 +225,42 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define R_FCSR 70
#define R_FEIR 71
#define R_TLBHI 72
#if __mips == 1
#define R_TLBLO 73
#endif
#if __mips == 3
#define R_TLBLO0 74
#define R_TLBLO0 73
#endif
#define R_INX 74
#define R_RAND 75
#define R_CTXT 76
#define R_EXCTYPE 77
#define R_MODE 78
#define R_PRID 79
#define R_TAR 80
#if __mips == 1
#define NREGS 80
#define NREGS 81
#endif
#if __mips == 3
#define R_TLBLO1 80
#define R_PAGEMASK 81
#define R_WIRED 82
#define R_COUNT 83
#define R_COMPARE 84
#define R_CONFIG 85
#define R_LLADDR 86
#define R_WATCHLO 87
#define R_WATCHHI 88
#define R_ECC 89
#define R_CACHEERR 90
#define R_TAGLO 91
#define R_TAGHI 92
#define R_ERRPC 93
#define R_XCTXT 94 /* Ketan added from SIM64bit */
#define R_TLBLO1 81
#define R_PAGEMASK 82
#define R_WIRED 83
#define R_COUNT 84
#define R_COMPARE 85
#define R_CONFIG 86
#define R_LLADDR 87
#define R_WATCHLO 88
#define R_WATCHHI 89
#define R_ECC 90
#define R_CACHEERR 91
#define R_TAGLO 92
#define R_TAGHI 93
#define R_ERRPC 94
#define R_XCTXT 95 /* Ketan added from SIM64bit */
#define NREGS 95
#define NREGS 96
#endif
/*
cpukit/score/cpu/mips/rtems/mips/idtcpu.h
+5
View File
@@ -362,6 +362,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_BT 0x40000000 /* Branch Taken */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
@@ -393,6 +394,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_WIRED $6 /* number of wired tlb entries */
#endif
#if __mips == 1
#define C0_TAR $6
#endif
#define C0_BADVADDR $8 /* bad virtual address */
#if __mips == 3
cpukit/score/cpu/mips/rtems/mips/iregdef.h
+21 -18
View File
@@ -225,39 +225,42 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define R_FCSR 70
#define R_FEIR 71
#define R_TLBHI 72
#if __mips == 1
#define R_TLBLO 73
#endif
#if __mips == 3
#define R_TLBLO0 74
#define R_TLBLO0 73
#endif
#define R_INX 74
#define R_RAND 75
#define R_CTXT 76
#define R_EXCTYPE 77
#define R_MODE 78
#define R_PRID 79
#define R_TAR 80
#if __mips == 1
#define NREGS 80
#define NREGS 81
#endif
#if __mips == 3
#define R_TLBLO1 80
#define R_PAGEMASK 81
#define R_WIRED 82
#define R_COUNT 83
#define R_COMPARE 84
#define R_CONFIG 85
#define R_LLADDR 86
#define R_WATCHLO 87
#define R_WATCHHI 88
#define R_ECC 89
#define R_CACHEERR 90
#define R_TAGLO 91
#define R_TAGHI 92
#define R_ERRPC 93
#define R_XCTXT 94 /* Ketan added from SIM64bit */
#define R_TLBLO1 81
#define R_PAGEMASK 82
#define R_WIRED 83
#define R_COUNT 84
#define R_COMPARE 85
#define R_CONFIG 86
#define R_LLADDR 87
#define R_WATCHLO 88
#define R_WATCHHI 89
#define R_ECC 90
#define R_CACHEERR 91
#define R_TAGLO 92
#define R_TAGHI 93
#define R_ERRPC 94
#define R_XCTXT 95 /* Ketan added from SIM64bit */
#define NREGS 95
#define NREGS 96
#endif
/*
cpukit/score/cpu/mips/rtems/score/cpu.h
+16 -3
View File
@@ -314,7 +314,7 @@ extern "C" {
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_MODES_INTERRUPT_MASK 0x000000ff
/*
* Processor defined structures
@@ -360,6 +360,8 @@ extern "C" {
* a debugger such as gdb. But that is another problem.
*/
#ifndef ASSEMBLY_ONLY
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
#if __mips == 1
#define __MIPS_REGISTER_TYPE unsigned32
@@ -595,6 +597,7 @@ typedef struct {
unsigned32 clicks_per_microsecond;
} rtems_cpu_table;
/*
* Macros to access required entires in the CPU Table are in
* the file rtems/system.h.
@@ -647,6 +650,8 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* NOTE: Not needed on this port.
*/
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
@@ -686,6 +691,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32))
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
@@ -845,9 +851,11 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
#if __mips == 3
#define _INTON (SR_EXL | SR_IE)
#define _EXTRABITS 0
#endif
#if __mips == 1
#define _INTON SR_IEC
#define _INTON SR_IEC
#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */
#endif
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
@@ -862,7 +870,7 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
0x300 | \
((_intlvl & 1)?_INTON:0)) ) | \
SR_CU0 | ((_is_fp)?SR_CU1:0); \
SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
}
@@ -1178,6 +1186,11 @@ static inline unsigned int CPU_swap_u32(
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
#endif
#ifdef __cplusplus
}
#endif