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bsp/xilinx-zynq: Add devcfg and slcr drivers
The devfg driver loads the PL with a bitfile image. The driver can also support scrubbing. These drivers are from Patrick Gauvin <pggauvin at gmail.com> and a thread on the devel list: https://lists.rtems.org/pipermail/devel/2017-May/017705.html
This commit is contained in:
Chris Johns
Amar Takhar
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,101 @@
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/*
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* SLCR Support Implementation
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*
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* At this point, only a few operations related to programming the FPGA are
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* supported.
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*
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* Copyright (c) 2017
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Pittsburgh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of CHREC.
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*
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* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
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*/
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#include <stdint.h>
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#include <rtems.h>
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#include <dev/slcr/zynq-slcr.h>
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#include <dev/slcr/zynq-slcr-regs.h>
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static uint32_t rst_mask = 0xf;
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static rtems_interrupt_lock zynq_slcr_lock =
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RTEMS_INTERRUPT_LOCK_INITIALIZER( "zynq_slcr" );
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static inline void slcr_unlock( void )
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{
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zynq_slcr_write32( ZYNQ_SLCR_UNLOCK_OFF, ZYNQ_SLCR_UNLOCK_KEY );
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}
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static inline void slcr_lock( void )
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{
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zynq_slcr_write32( ZYNQ_SLCR_LOCK_OFF, ZYNQ_SLCR_LOCK_KEY );
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}
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void zynq_slcr_fpga_clk_rst_mask_set(
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uint32_t mask
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)
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{
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rtems_interrupt_lock_context lcontext;
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rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
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rst_mask = 0xf & mask;
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rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
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}
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void zynq_slcr_fpga_clk_rst(
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uint32_t val
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)
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{
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uint32_t rst_ctrl;
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rtems_interrupt_lock_context lcontext;
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rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
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slcr_unlock();
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rst_ctrl = ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET(
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zynq_slcr_read32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF )
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);
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/* Only modify resets that are set in the mask */
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zynq_slcr_write32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF,
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ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST(
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( ~rst_mask & rst_ctrl ) | ( rst_mask & val )
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)
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);
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slcr_lock();
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rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
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}
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void zynq_slcr_level_shifter_enable(
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uint32_t val
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)
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{
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rtems_interrupt_lock_context lcontext;
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rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
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slcr_unlock();
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zynq_slcr_write32( ZYNQ_SLCR_LVL_SHFTR_EN_OFF, val );
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slcr_lock();
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rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
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}
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@@ -0,0 +1,197 @@
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/**
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* @file
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* @ingroup zynq_devcfg
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* @brief Device configuration interface register definitions.
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*/
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/*
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* Copyright (c) 2016
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Florida. All rights reserved.
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* Copyright (c) 2017
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Pittsburgh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
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* The views and conclusions contained in the software and documentation
|
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* are those of the authors and should not be interpreted as representing
|
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* official policies, either expressed or implied, of CHREC.
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*
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* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
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*/
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/**
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* @defgroup zynq_devcfg_regs Device Configuration Interface Register Definitions
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* @ingroup zynq_devcfg
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* @brief Device Configuration Interface Register Definitions
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*/
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#ifndef LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
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#define LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
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#include <stdint.h>
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#include <bsp/utility.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* Zynq-7000 series devcfg address */
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#define ZYNQ_DEVCFG_BASE_ADDR 0xF8007000UL
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/* For use with the PCAP DMA */
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#define ZYNQ_DEVCFG_BITSTREAM_ADDR 0xFFFFFFFFUL
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/* PCAP DMA transfers must be 64-byte aligned */
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#define ZYNQ_DEVCFG_PCAP_DMA_ALIGN 64
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#define ZYNQ_DEVCFG_INTERRUPT_VECTOR 40
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typedef struct {
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uint32_t ctrl;
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#define ZYNQ_DEVCFG_CTRL_FORCE_RST( val ) BSP_FLD32( val, 31, 31 )
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#define ZYNQ_DEVCFG_CTRL_FORCE_RST_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET( reg ) BSP_FLD32GET( reg, 30, 30 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B( val ) BSP_FLD32( val, 30, 30 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET( reg ) BSP_FLD32GET( reg, 29, 29 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K( val ) BSP_FLD32( val, 29, 29 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR( val ) BSP_FLD32( val, 27, 27 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR_GET( reg ) BSP_FLD32GET( reg, 27, 27 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR_ICAP ( 0 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR_PCAP ( 1 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_MODE( val ) BSP_FLD32( val, 26, 26 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET( reg ) BSP_FLD32GET( reg, 26, 26 )
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#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN( val ) BSP_FLD32( val, 25, 25 )
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#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET( reg ) \
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BSP_FLD32GET( reg, 25, 25 )
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#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN( val ) BSP_FLD32( val, 24, 24 )
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#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET( reg ) BSP_FLD32GET( reg, 24, 24 )
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#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS( val ) BSP_FLD32( val, 23, 23 )
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#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET( reg ) BSP_FLD32GET( reg, 23, 23 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE( val ) BSP_FLD32( val, 12, 12 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_BBRAM ( 0 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_EFUSE ( 1 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN( val ) BSP_FLD32( val, 9, 11 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET( reg ) BSP_FLD32GET( reg, 9, 11 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_ENABLE ( 0x3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_DISABLE ( 0x0 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_LOCKDOWN ( 0x1 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN( val ) BSP_FLD32( val, 8, 8 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET( reg ) BSP_FLD32GET( reg, 7, 7 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN( val ) BSP_FLD32( val, 6, 6 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET( reg ) BSP_FLD32GET( reg, 6, 6 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN( val ) BSP_FLD32( val, 5, 5 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET( reg ) BSP_FLD32GET( reg, 5, 5 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN( val ) BSP_FLD32( val, 4, 4 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN( val ) BSP_FLD32( val, 3, 3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET( reg ) BSP_FLD32GET( reg, 3, 3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN( val ) BSP_FLD32( val, 0, 2 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET( reg ) BSP_FLD32GET( reg, 0, 2 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_ENABLE ( 0x3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_BYPASS ( 0x0 )
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#define ZYNQ_DEVCFG_CTRL_RESERVED_BITS ( 0x6000 )
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uint32_t lock;
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uint32_t cfg;
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/* int_sts and int_mask directly overlap, so they share the ZYNQ_DEVCFG_INT_*
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* macros */
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uint32_t int_sts;
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uint32_t int_mask;
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#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT BSP_BIT32( 27 )
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#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET( reg ) \
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BSP_FLD32GET( reg, 27, 27 )
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#define ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET( reg ) BSP_FLD32GET( reg, 22, 22 )
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#define ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET( reg ) BSP_FLD32GET( reg, 21, 21 )
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#define ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET( reg ) BSP_FLD32GET( reg, 20, 20 )
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#define ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET( reg ) \
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BSP_FLD32GET( reg, 18, 18 )
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#define ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 15, 15 )
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#define ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET( reg ) BSP_FLD32GET( reg, 14, 14 )
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#define ZYNQ_DEVCFG_INT_DMA_DONE_INT BSP_BIT32( 13 )
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#define ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 13, 13 )
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#define ZYNQ_DEVCFG_INT_D_P_DONE_INT BSP_BIT32( 12 )
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#define ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
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#define ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 11, 11 )
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#define ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 6, 6 )
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#define ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 5, 5 )
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#define ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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#define ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET( reg ) \
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BSP_FLD32GET( reg, 3, 3 )
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#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT BSP_BIT32( 2 )
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#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 2, 2 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT BSP_BIT32( 1 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET( reg ) \
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BSP_FLD32GET( reg, 1, 1 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT BSP_BIT32( 0 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET( reg ) \
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BSP_FLD32GET( reg, 0, 0 )
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#define ZYNQ_DEVCFG_INT_ALL ( 0xf8f7f87f )
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uint32_t status;
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#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F( val ) BSP_FLD32( val, 31, 31 )
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#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
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#define ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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uint32_t dma_src_addr;
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#define ZYNQ_DEVCFG_DMA_SRC_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
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uint32_t dma_dst_addr;
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#define ZYNQ_DEVCFG_DMA_DST_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
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uint32_t dma_src_len;
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#define ZYNQ_DEVCFG_DMA_SRC_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
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uint32_t dma_dest_len; /* (sic) */
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#define ZYNQ_DEVCFG_DMA_DEST_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
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uint32_t reserved0;
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uint32_t multiboot_addr;
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uint32_t reserved1;
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uint32_t unlock;
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uint32_t reserved2[18];
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uint32_t mctrl;
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET( reg ) BSP_FLD32GET( reg, 28, 31 )
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_1_0 0x0
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_2_0 0x1
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_0 0x2
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_1 0x3
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#define ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
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#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK( val ) BSP_FLD32( val, 4, 4 )
|
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#define ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS ( 0x800000 )
|
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#define ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ( 0x3 )
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#define ZYNQ_DEVCFG_MCTRL_SET( reg, val ) ( ( ( reg ) & \
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~ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ) | \
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ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS | ( val ) )
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uint32_t reserved3[32];
|
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uint32_t xadcif_cfg;
|
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uint32_t xadcif_int_sts;
|
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uint32_t xadcif_int_mask;
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uint32_t xadcif_msts;
|
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uint32_t xadcif_cmdfifo;
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uint32_t xadcif_rdfifo;
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uint32_t xadcif_mctrl;
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} zynq_devcfg_regs;
|
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#ifdef __cplusplus
|
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}
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#endif /* __cplusplus */
|
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#endif /* LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H */
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@@ -0,0 +1,155 @@
|
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/**
|
||||
* @file
|
||||
* @ingroup zynq_devcfg
|
||||
* @brief Device configuration support.
|
||||
*
|
||||
* Provides support for the Zynq7000 series device configuration interface
|
||||
* controller. PCAP command sequences are written using the write interface,
|
||||
* and PCAP responses are retrieved with the read interface. The driver can be
|
||||
* used for reconfiguration of the FPGA, and also reading FPGA configuration
|
||||
* data for error checking.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2016
|
||||
* NSF Center for High-Performance Reconfigurable Computing (CHREC),
|
||||
* University of Florida. All rights reserved.
|
||||
* Copyright (c) 2017
|
||||
* NSF Center for High-Performance Reconfigurable Computing (CHREC),
|
||||
* University of Pittsburgh. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* The views and conclusions contained in the software and documentation
|
||||
* are those of the authors and should not be interpreted as representing
|
||||
* official policies, either expressed or implied, of CHREC.
|
||||
*
|
||||
* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup zynq_devcfg Device Configuration Interface Support
|
||||
* @ingroup arm_zynq
|
||||
* @brief Device Configuration Interface Support
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_H
|
||||
#define LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_H
|
||||
|
||||
#include <rtems/libio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define ZYNQ_DEVCFG_NAME "/dev/fgpa"
|
||||
/*
|
||||
* Add to CONFIGURE_APPLICATION_PREREQUISITE_DRIVERS
|
||||
*/
|
||||
#define ZYNQ_DEVCFG_DRIVER_TABLE_ENTRY \
|
||||
{ zynq_devcfg_init, zynq_devcfg_open, zynq_devcfg_close, zynq_devcfg_read, \
|
||||
zynq_devcfg_write, zynq_devcfg_control }
|
||||
|
||||
/* Configuration command words. */
|
||||
#define ZYNQ_DEVCFG_CFG_DUMMY ( 0xffffffff )
|
||||
#define ZYNQ_DEVCFG_CFG_BUS_WIDTH_SYNC ( 0x000000bb )
|
||||
#define ZYNQ_DEVCFG_CFG_BUS_WIDTH_DETECT ( 0x11220044 )
|
||||
#define ZYNQ_DEVCFG_CFG_SYNC ( 0xaa995566 )
|
||||
|
||||
/** @brief Zynq configuration frame length in bytes */
|
||||
#define ZYNQ_DEVCFG_CONFIG_FRAME_LEN ( 101 * 4 )
|
||||
|
||||
#define ZYNQ_DEVCFG_IOCTL_VERSION_MAX_LEN 16
|
||||
|
||||
enum zynq_devcfg_ioctl {
|
||||
/** @brief Argument: Buffer for character string of at least
|
||||
* ZYNQ_DEVCFG_IOCTL_VERSION_MAX_LEN bytes.
|
||||
*/
|
||||
ZYNQ_DEVCFG_IOCTL_VERSION,
|
||||
/** @brief Argument: None. */
|
||||
ZYNQ_DEVCFG_IOCTL_FPGA_PROGRAM_PRE,
|
||||
/** @brief Argument: None. */
|
||||
ZYNQ_DEVCFG_IOCTL_FPGA_PROGRAM_POST,
|
||||
/** @brief Argument: None. */
|
||||
ZYNQ_DEVCFG_IOCTL_FPGA_PROGRAM_WAIT_DONE,
|
||||
/** @brief Argument: bool. */
|
||||
ZYNQ_DEVCFG_IOCTL_SET_SECURE,
|
||||
/** @brief Argument: bool. */
|
||||
ZYNQ_DEVCFG_IOCTL_SET_WRITE_MODE_RESTRICTED
|
||||
};
|
||||
|
||||
rtems_device_driver zynq_devcfg_init(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *args
|
||||
);
|
||||
|
||||
rtems_device_driver zynq_devcfg_open(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *args
|
||||
);
|
||||
|
||||
rtems_device_driver zynq_devcfg_close(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *args
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Read from the PCAP controller.
|
||||
*
|
||||
* Readback reads cannot be split into multiple DMA reads, this may cause the
|
||||
* PCAP DMA to exhibit unexpected behavior. Therefore, the read length must
|
||||
* match the preceding command sequence's expected data output length.
|
||||
*/
|
||||
rtems_device_driver zynq_devcfg_read(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *args
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Write to the PCAP controller.
|
||||
*
|
||||
* Data format: dword aligned bistream data or PCAP commands. Bitstream data is
|
||||
* expected to be formatted as Vivado 2016.4 outputs BIN-format bitstreams by
|
||||
* default (not bit-swapped) BUT with the byte order within each dword changed
|
||||
* to little endian. See UG470 for information on data ordering.
|
||||
*/
|
||||
rtems_device_driver zynq_devcfg_write(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *args
|
||||
);
|
||||
|
||||
rtems_device_driver zynq_devcfg_control(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *args
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_H */
|
||||
@@ -0,0 +1,111 @@
|
||||
/**
|
||||
* @file
|
||||
* @ingroup zynq_slcr
|
||||
* @brief SLCR register definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2017
|
||||
* NSF Center for High-Performance Reconfigurable Computing (CHREC),
|
||||
* University of Pittsburgh. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* The views and conclusions contained in the software and documentation
|
||||
* are those of the authors and should not be interpreted as representing
|
||||
* official policies, either expressed or implied, of CHREC.
|
||||
*
|
||||
* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup zynq_slcr_regs SLCR Register Definitions
|
||||
* @ingroup zynq_slcr
|
||||
* @brief SLCR Register Definitions
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H
|
||||
#define LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H
|
||||
|
||||
#include <bsp/utility.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define ZYNQ_SLCR_BASE_ADDR ( 0xF8000000 )
|
||||
|
||||
#define ZYNQ_SLCR_LOCK_OFF ( 0x4 )
|
||||
#define ZYNQ_SLCR_UNLOCK_OFF ( 0x8 )
|
||||
#define ZYNQ_SLCR_FPGA_RST_CTRL_OFF ( 0x240 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_OFF ( 0x530 )
|
||||
#define ZYNQ_SLCR_LVL_SHFTR_EN_OFF ( 0x900 )
|
||||
|
||||
#define ZYNQ_SLCR_LOCK_KEY ( 0x767b )
|
||||
#define ZYNQ_SLCR_UNLOCK_KEY ( 0xdf0d )
|
||||
|
||||
/** \brief Get FPGA0_OUT_RST (bit 0) through FPGA3_OUT_RST fields (bit 3). */
|
||||
#define ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET( reg ) \
|
||||
BSP_FLD32GET( reg, 0, 3 )
|
||||
#define ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST( val ) BSP_FLD32( val, 0, 3 )
|
||||
|
||||
/* NOTE: QEMU gives a value of 0 for the pss_idcode. */
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_GET( reg ) BSP_FLD32GET( reg, 12, 16 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z007s ( 0x03 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z012s ( 0x1c )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z014s ( 0x08 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z010 ( 0x02 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z015 ( 0x1b )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z020 ( 0x07 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z030 ( 0x0c )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z035 ( 0x12 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z045 ( 0x11 )
|
||||
#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z100 ( 0x16 )
|
||||
|
||||
#define ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE ( 0 )
|
||||
#define ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL ( 0xA )
|
||||
#define ZYNQ_SLCR_LVL_SHFTR_EN_ALL ( 0xF )
|
||||
|
||||
static inline void zynq_slcr_write32(
|
||||
const uint32_t reg_off,
|
||||
const uint32_t val
|
||||
)
|
||||
{
|
||||
volatile uint32_t *slcr_reg;
|
||||
slcr_reg = (volatile uint32_t *)( ZYNQ_SLCR_BASE_ADDR + reg_off );
|
||||
*slcr_reg = val;
|
||||
}
|
||||
|
||||
static inline uint32_t zynq_slcr_read32(
|
||||
const uint32_t reg_off
|
||||
)
|
||||
{
|
||||
volatile uint32_t *slcr_reg;
|
||||
slcr_reg = (volatile uint32_t *)( ZYNQ_SLCR_BASE_ADDR + reg_off);
|
||||
return *slcr_reg;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H */
|
||||
@@ -0,0 +1,91 @@
|
||||
/**
|
||||
* @file
|
||||
* @ingroup zynq_slcr
|
||||
* @brief SLCR support.
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* Copyright (c) 2017
|
||||
* NSF Center for High-Performance Reconfigurable Computing (CHREC),
|
||||
* University of Pittsburgh. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* The views and conclusions contained in the software and documentation
|
||||
* are those of the authors and should not be interpreted as representing
|
||||
* official policies, either expressed or implied, of CHREC.
|
||||
*
|
||||
* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup zynq_slcr SLCR Support
|
||||
* @ingroup arm_zynq
|
||||
* @brief SLCR Support
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
|
||||
#define LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @brief Set the mask that allows the FPGA resets to be modified.
|
||||
*
|
||||
* Bit 0 corresponds to FPGA0_OUT_RST, and bit 3 to FPGA3_OUT_RST. Setting a
|
||||
* bit in the mask to 1 allows calls to zynq_slcr_fpga_clk_rst to modify that
|
||||
* reset. The default mask is 0xf.
|
||||
*/
|
||||
void zynq_slcr_fpga_clk_rst_mask_set(
|
||||
uint32_t mask
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Control the FPGA reset values.
|
||||
*
|
||||
* @param val Bits 0 through 3 correspond to FPGA RST 0 through 3. A bit value
|
||||
* of 1 asserts the reset.
|
||||
*/
|
||||
void zynq_slcr_fpga_clk_rst(
|
||||
uint32_t val
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Control the level shifters between the PS and PL.
|
||||
*
|
||||
* @param val Acceptable values are ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE,
|
||||
* ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL, and ZYNQ_SLCR_LVL_SHFTR_EN_ALL.
|
||||
*/
|
||||
void zynq_slcr_level_shifter_enable(
|
||||
uint32_t val
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_H */
|
||||
@@ -19,6 +19,12 @@ install:
|
||||
source:
|
||||
- bsps/include/dev/i2c/cadence-i2c-regs.h
|
||||
- bsps/include/dev/i2c/cadence-i2c.h
|
||||
- destination: ${BSP_INCLUDEDIR}/dev/devcfg
|
||||
source:
|
||||
- bsps/arm/xilinx-zynq/include/dev/devcfg/zynq-devcfg.h
|
||||
- destination: ${BSP_INCLUDEDIR}/dev/slcr
|
||||
source:
|
||||
- bsps/arm/xilinx-zynq/include/dev/slcr/zynq-slcr.h
|
||||
links: []
|
||||
source:
|
||||
- bsps/arm/shared/cache/cache-l2c-310.c
|
||||
@@ -40,4 +46,6 @@ source:
|
||||
- bsps/shared/start/gettargethash-default.c
|
||||
- bsps/shared/start/sbrk.c
|
||||
- bsps/shared/start/stackalloc.c
|
||||
- bsps/arm/xilinx-zynq/dev/devcfg/zynq-devcfg.c
|
||||
- bsps/arm/xilinx-zynq/dev/slcr/zynq-slcr.c
|
||||
type: build
|
||||
|
||||
Reference in New Issue
Block a user