This is a large patch from Eric Valette <valette@crf.canon.fr> that was

described in the message following this paragraph. This patch also includes a mcp750 BSP. From valette@crf.canon.fr Mon Jun 14 10:03:08 1999 Date: Tue, 18 May 1999 01:30:14 +0200 (CEST) From: VALETTE Eric <valette@crf.canon.fr> To: joel@oarcorp.com Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr Subject: Questions/Suggestion regarding RTEMS PowerPC code (long) Dear knowledgeable RTEMS powerpc users, As some of you may know, I'm currently finalizing a port of RTEMS on a MCP750 Motorola board. I have done most of it but have some questions to ask before submitting the port. In order to understand some of the changes I have made or would like to make, maybe it is worth describing the MCP750 Motorola board. the MCP750 is a COMPACT PCI powerpc board with : 1) a MPC750 233 MHz processor, 2) a raven bus bridge/PCI controller that implement an OPENPIC compliant interrupt controller, 3) a VIA 82C586 PCI/ISA bridge that offers a PC compliant IO for keyboard, serial line, IDE, and the well known PC 8259 cascaded PIC interrupt architecture model, 4) a DEC 21140 Ethernet controller, 5) the PPCBUG Motorola firmware in flash, 6) A DEC PCI bridge, This architecture is common to most Motorola 60x/7xx board except that : 1) on VME board, the DEC PCI bridge is replaced by a VME chipset, 2) the VIA 82C586 PCI/ISA bridge is replaced by another bridge that is almost fully compatible with the via bridge... So the port should be a rather close basis for many 60x/7xx motorola board... On this board, I already have ported Linux 2.2.3 and use it both as a development and target board. Now the questions/suggestions I have : 1) EXCEPTION CODE ------------------- As far as I know exceptions on PPC are handled like interrupts. I dislike this very much as : a) Except for the decrementer exception (and maybe some other on mpc8xx), exceptions are not recoverable and the handler just need to print the full context and go to the firmware or debugger... b) The interrupt switch is only necessary for the decrementer and external interrupt (at least on 6xx,7xx). c) The full context for exception is never saved and thus cannot be used by debugger... I do understand the most important for interrupts low level code is to save the minimal context enabling to call C code for performance reasons. On non recoverable exception on the other hand, the most important is to save the maximum information concerning proc status in order to analyze the reason of the fault. At least we will need this in order to implement the port of RGDB on PPC ==> I wrote an API for connecting raw exceptions (and thus raw interrupts) for mpc750. It should be valid for most powerpc processors... I hope to find a way to make this coexist with actual code layout. The code is actually located in lib/libcpu/powerpc/mpc750 and is thus optional (provided I write my own version of exec/score/cpu/powerpc/cpu.c ...) See remark about files/directory layout organization in 4) 2) Current Implementation of ISR low level code ----------------------------------------------- I do not understand why the MSR EE flags is cleared again in exec/score/cpu/powerpc/irq_stubs.S #if (PPC_USE_SPRG) mfmsr r5 mfspr r6, sprg2 #else lwz r6,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r6,r6,r5 mfmsr r5 #endif Reading the doc, when a decrementer interrupt or an external interrupt is active, the MSR EE flag is already cleared. BTW if exception/interrupt could occur, it would trash SRR0 and SRR1. In fact the code may be useful to set MSR[RI] that re-enables exception processing. BTW I will need to set other value in MSR to handle interrupts : a) I want the MSR[IR] and MSR[DR] to be set for performance reasons and also because I need DBAT support to have access to PCI memory space as the interrupt controller is in the PCI space. Reading the code, I see others have the same kind of request : /* SCE 980217 * * We need address translation ON when we call our ISR routine mtmsr r5 */ This is just another prof that even the lowest level IRQ code is fundamentally board dependent and not simply processor dependent especially when the processor use external interrupt controller because it has a single interrupt request line... Note that if you look at the PPC code high level interrupt handling code, as the "set_vector" routine that really connects the interrupt is in the BSP/startup/genpvec.c, the fact that IRQ handling is BSP specific is DE-FACTO acknowledged. I know I have already expressed this and understand that this would require some heavy change in the code but believe me you will reach a point where you will not be able to find a compatible while optimum implementation for low level interrupt handling code...) In my case this is already true... So please consider removing low level IRQ handling from exec/score/cpu/* and only let there exception handling code... Exceptions are usually only processor dependent and do not depend on external hardware mechanism to be masked or acknowledged or re-enabled (there are probably exception but ...) I have already done this for pc386 bsp but need to make it again. This time I will even propose an API. 3) R2/R13 manipulation for EABI implementation ---------------------------------------------- I do not understand the handling of r2 and r13 in the EABI case. The specification for r2 says pointer to sdata2, sbss2 section => constant. However I do not see -ffixed-r2 passed to any compilation system in make/custom/* (for info linux does this on PPC). So either this is a default compiler option when choosing powerpc-rtems and thus we do not need to do anything with this register as all the code is compiled with this compiler and linked together OR this register may be used by rtems code and then we do not need any special initialization or handling. The specification for r13 says pointer to the small data area. r13 argumentation is the same except that as far as I know the usage of the small data area requires specific compiler support so that access to variables is compiled via loading the LSB in a register and then using r13 to get full address... It is like a small memory model and it was present in IBM C compilers. => I propose to suppress any specific code for r2 and r13 in the EABI case. 4) Code layout organization (yes again :-)) ------------------------------------------- I think there are a number of design flaws in the way the code is for ppc organized and I will try to point them out. I have been beaten by this again on this new port, and was beaten last year while modifying code for pc386. a) exec/score/cpu/* vs lib/libcpu/cpu/*. I think that too many things are put in exec/score/cpu that have nothing to do with RTEMS internals but are rather related to CPU feature. This include at least : a) registers access routine (e.g GET_MSR_Value), b) interrupt masking/unmasking routines, c) cache_mngt_routine, d) mmu_mngt_routine, e) Routines to connect the raw_exception, raw_interrupt handler, b) lib/libcpu/cpu/powerpc/* With a processor family as exuberant as the powerpc family, and their well known subtle differences (604 vs 750) or unfortunately majors (8xx vs 60x) the directory structure is fine (except maybe the names that are not homogeneous) powerpc ppc421 mpc821 ... I only needed to add mpc750. But the fact that libcpu.a was not produced was a pain and the fact that this organization may duplicates code is also problematic. So, except if the support of automake provides a better solution I would like to propose something like this : powerpc mpc421 mpc821 ... mpc750 shared wrapup with the following rules : a) "shared" would act as a source container for sources that may be shared among processors. Needed files would be compiled inside the processor specific directory using the vpath Makefile mechanism. "shared" may also contain compilation code for routine that are really shared and not worth to inline... (did not found many things so far as registers access routine ARE WORTH INLINING)... In the case something is compiled there, it should create libcpushared.a b) layout under processor specific directory is free provided that 1)the result of the compilation process exports : libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu 2) each processor specific directory creates a library called libcpuspecific.a Note that this organization enables to have a file that is nearly the same than in shared but that must differ because of processor differences... c) "wrapup" should create libcpu.a using libcpushared.a libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu The only thing I have no ideal solution is the way to put shared definitions in "shared" and only processor specific definition in "proc". To give a concrete example, most MSR bit definition are shared among PPC processors and only some differs. if we create a single msr.h in shared it will have ifdef. If in msr.h we include libcpu/msr_c.h we will need to have it in each prowerpc specific directory (even empty). Opinions are welcomed ... Note that a similar mechanism exist in libbsp/i386 that also contains a shared directory that is used by several bsp like pc386 and i386ex and a similar wrapup mechanism... NB: I have done this for mpc750 and other processors could just use similar Makefiles... c) The exec/score/cpu/powerpc directory layout. I think the directory layout should be the same than the libcpu/powerpc. As it is not, there are a lot of ifdefs inside the code... And of course low level interrupt handling code should be removed... Besides that I do not understand why 1) things are compiled in the wrap directory, 2) some includes are moved to rtems/score, I think the "preinstall" mechanism enables to put everything in the current directory (or better in a per processor directory), 5) Interrupt handling API ------------------------- Again :-). But I think that using all the features the PIC offers is a MUST for RT system. I already explained in the prologue of this (long and probably boring) mail that the MCP750 boards offers an OPENPIC compliant architecture and that the VIA 82586 PCI/ISA bridge offers a PC compatible IO and PIC mapping. Here is a logical view of the RAVEN/VIA 82586 interrupt mapping : --------- 0 ------ | OPEN | <-----|8259| | PIC | | | 2 ------ |(RAVEN)| | | <-----|8259| | | | | | | 11 | | | | | | <---- | | | | | | | | | | | | --------- ------ | | ^ ------ | VIA PCI/ISA bridge | x -------- PCI interrupts OPENPIC offers interrupt priorities among PCI interrupts and interrupt selective masking. The 8259 offers the same kind of feature. With actual powerpc interrupt code : 1) there is no way to specify priorities among interrupts handler. This is REALLY a bad thing. For me it is as importnat as having priorities for threads... 2) for my implementation, each ISR should contain the code that acknowledge the RAVEN and 8259 cascade, modify interrupt mask on both chips, and reenable interrupt at processor level, ..., restore then on interrupt return,.... This code is actually similar to code located in some genpvec.c powerpc files, 3) I must update _ISR_Nesting_level because irq.inl use it... 4) the libchip code connects the ISR via set_vector but the libchip handler code does not contain any code to manipulate external interrupt controller hardware in order to acknoledge the interrupt or re-enable them (except for the target hardware of course) So this code is broken unless set_vector adds an additionnal prologue/epilogue before calling/returning from in order to acknoledge/mask the raven and the 8259 PICS... => Anyway already EACH BSP MUST REWRITE PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT SET_VECTOR. I would rather offer an API similar to the one provided in libbsp/i386/shared/irq/irq.h so that : 1) Once the driver supplied methods is called the only things the ISR has to do is to worry about the external hardware that triggered the interrupt. Everything on openpic/VIA/processor would have been done by the low levels (same things as set-vector) 2) The caller will need to supply the on/off/isOn routine that are fundamental to correctly implements debuggers/performance monitoring is a portable way 3) A globally configurable interrupt priorities mechanism... I have nothing against providing a compatible set_vector just to make libchip happy but as I have already explained in other mails (months ago), I really think that the ISR connection should be handled by the BSP and that no code containing irq connection should exist the rtems generic layers... Thus I really dislike libchip on this aspect because in a long term it will force to adopt the less reach API for interrupt handling that exists (set_vector). Additional note : I think the _ISR_Is_in_progress() inline routine should be : 1) Put in a processor specific section, 2) Should not rely on a global variable, As : a) on symmetric MP, there is one interrupt level per CPU, b) On processor that have an ISP (e,g 68040), this variable is useless (MSR bit testing could be used) c) On PPC, instead of using the address of the variable via __CPU_IRQ_info.Nest_level a dedicated SPR could be used. NOTE: most of this is also true for _Thread_Dispatch_disable_level END NOTE -------- Please do not take what I said in the mail as a criticism for anyone who submitted ppc code. Any code present helped me a lot understanding PPC behavior. I just wanted by this mail to : 1) try to better understand the actual code, 2) propose concrete ways of enhancing current code by providing an alternative implementation for MCP750. I will make my best effort to try to brake nothing but this is actually hard due to the file layout organisation. 3) make understandable some changes I will probably make if joel let me do them :-) Any comments/objections are welcomed as usual. -- __ / ` Eric Valette /-- __ o _. Canon CRF (___, / (_(_(__ Rue de la touche lambert 35517 Cesson-Sevigne Cedex FRANCE Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30 E-mail: valette@crf.canon.fr
2026-10-26 14:38:12 +08:00 · 1999-06-14 16:51:13 +00:00
1 parent 255b2931b6
commit ba46ffa616
@@ -1,4 +1,7 @@
 #
+# $Id$
+#
+#	
 #  $Id$
 #

@@ -18,8 +21,13 @@ VPATH = @srcdir@
 include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
 include $(RTEMS_ROOT)/make/directory.cfg

-SUB_DIRS = rtems wrap
+SHARED_LIB=shared
+
+ifeq ($(RTEMS_CPU_MODEL),mpc750)
+CPUDIR=mpc750
+else
+CPUDIR=other_cpu
+endif
+
+SUB_DIRS=$(CPUDIR) $(SHARED_LIB)

-Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
-	cd $(top_builddir) \
-	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
@@ -0,0 +1,83 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/exec/score/cpu/powerpc/wrap
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+RELS=../$(ARCH)/rtems-cpu.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES = cpu
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+ROOT_H_PIECES =
+ROOT_H_FILES=$(ROOT_H_PIECES:%=$(srcdir)/%)
+RTEMS_SCORE_H_PIECES=cpu.h
+RTEMS_SCORE_H_FILES=$(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
+H_PIECES=$(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
+H_FILES=$(H_PIECES%=$(srcdir)/%)
+I_PIECES= c_isr
+I_FILES=$(I_PIECES:%=$(srcdir)/%.inl)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES = cpu_asm 
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) $(I_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += 
+CFLAGS   += $(CFLAGS_OS_V)
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+../$(ARCH)/rtems-cpu.rel: $(OBJS)
+	test -d ../$(ARCH) || mkdir ../$(ARCH)
+	$(make-rel)
+
+all:    ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL_CHANGE)
+install:  all
+
+preinstall: ${ARCH}
+	$(INSTALL_CHANGE) -m 444 ${RTEMS_SCORE_H_FILES} ${I_FILES} $(PROJECT_INCLUDE)/rtems/score
+	$(INSTALL_CHANGE) -m 444 ${ROOT_H_FILES} $(PROJECT_INCLUDE)
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
@@ -0,0 +1,9 @@
+RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
+{
+	register unsigned int isr_nesting_level;
+	/*
+         * Move from special purpose register 0 (mfspr SPRG0, r3)
+	 */
+	asm volatile ("mfspr	%0, 272" : "=r" (isr_nesting_level));
+	return isr_nesting_level;
+}
@@ -0,0 +1,118 @@
+/*
+ *  PowerPC CPU Dependent Source
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be found in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/context.h>
+#include <rtems/score/thread.h>
+#include <rtems/score/interr.h>
+
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ */
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+  _CPU_Table = *cpu_table;
+}
+
+/*PAGE
+ *
+ *  _CPU_Context_Initialize
+ */
+
+#define CPU_MINIMUM_STACK_FRAME_SIZE 8
+
+void _CPU_Context_Initialize(
+  Context_Control  *the_context,
+  unsigned32       *stack_base,
+  unsigned32        size,
+  unsigned32        new_level,
+  void             *entry_point,
+  boolean           is_fp
+)
+{
+  unsigned32 msr_value;
+  unsigned32 sp;
+
+  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
+  *((unsigned32 *)sp) = 0;
+  the_context->gpr1 = sp;
+   
+  _CPU_MSR_GET( msr_value );
+
+  if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
+    msr_value |= MSR_EE;
+  }
+  else {
+    msr_value &= ~MSR_EE;
+  }
+
+  the_context->msr = msr_value;
+
+  /*
+   *  The FP bit of the MSR should only be enabled if this is a floating
+   *  point task.  Unfortunately, the vfprintf_r routine in newlib 
+   *  ends up pushing a floating point register regardless of whether or
+   *  not a floating point number is being printed.  Serious restructuring
+   *  of vfprintf.c will be required to avoid this behavior.  At this
+   *  time (7 July 1997), this restructuring is not being done.
+   */
+
+  /*if ( is_fp ) */
+    the_context->msr |= PPC_MSR_FP;
+
+  the_context->pc = (unsigned32)entry_point;
+}
+
+
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+}
+
+
+
+
@@ -0,0 +1,83 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/exec/score/cpu/powerpc/wrap
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+RELS=../$(ARCH)/rtems-cpu.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES = cpu ppccache
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+ROOT_H_PIECES =
+ROOT_H_FILES=$(ROOT_H_PIECES:%=$(srcdir)/%)
+RTEMS_SCORE_H_PIECES=cpu.h
+RTEMS_SCORE_H_FILES=$(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
+H_PIECES=$(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
+H_FILES=$(H_PIECES%=$(srcdir)/%)
+I_PIECES= c_isr
+I_FILES=$(I_PIECES:%=$(srcdir)/%.inl)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES = cpu_asm rtems # irq_stub
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) $(I_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += 
+CFLAGS   += $(CFLAGS_OS_V)
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+../$(ARCH)/rtems-cpu.rel: $(OBJS)
+	test -d ../$(ARCH) || mkdir ../$(ARCH)
+	$(make-rel)
+
+all:    ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL_CHANGE)
+install:  all
+
+preinstall: ${ARCH}
+	$(INSTALL_CHANGE) -m 444 ${RTEMS_SCORE_H_FILES} ${I_FILES} $(PROJECT_INCLUDE)/rtems/score
+	$(INSTALL_CHANGE) -m 444 ${ROOT_H_FILES} $(PROJECT_INCLUDE)
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
@@ -0,0 +1,4 @@
+RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
+{
+	return (_ISR_Nest_level != 0);
+}
@@ -41,6 +41,7 @@ extern "C" {
 #include <rtems/score/ppc.h>               /* pick up machine definitions */
 #ifndef ASM
 struct CPU_Interrupt_frame;
+typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );

 #include <rtems/score/ppctypes.h>
 #endif
@@ -0,0 +1,73 @@
+/*  ppctypes.h
+ *
+ *  This include file contains type definitions pertaining to the PowerPC
+ *  processor family.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_TYPES_h
+#define __PPC_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned32     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void ppc_isr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */
@@ -0,0 +1,73 @@
+/*  ppctypes.h
+ *
+ *  This include file contains type definitions pertaining to the PowerPC
+ *  processor family.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_TYPES_h
+#define __PPC_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned32     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void ppc_isr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */
@@ -0,0 +1,77 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/exec/score/cpu/powerpc/shared
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+RELS=
+
+# C source names, if any, go here -- minus the .c
+C_PIECES =
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+ROOT_H_PIECES = asm.h
+ROOT_H_FILES=$(ROOT_H_PIECES:%=$(srcdir)/%)
+RTEMS_SCORE_H_PIECES=ppc.h ppctypes.h
+RTEMS_SCORE_H_FILES=$(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
+H_PIECES=$(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
+H_FILES=$(H_PIECES%=$(srcdir)/%)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES =
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += 
+CFLAGS   += $(CFLAGS_OS_V)
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+all:$(SRCS) preinstall
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL_CHANGE)
+install:  all
+
+preinstall: ${ARCH}
+	$(INSTALL_CHANGE) -m 444 ${RTEMS_SCORE_H_FILES} $(PROJECT_INCLUDE)/rtems/score
+	$(INSTALL_CHANGE) -m 444 ${ROOT_H_FILES} $(PROJECT_INCLUDE)
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
@@ -0,0 +1,73 @@
+/*  ppctypes.h
+ *
+ *  This include file contains type definitions pertaining to the PowerPC
+ *  processor family.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_TYPES_h
+#define __PPC_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned32     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void ppc_isr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */
@@ -82,7 +82,7 @@ SCORE_EXTERN boolean    _ISR_Signals_to_thread_executing;
 *  When this variable is zero, a thread is executing.
 */

-SCORE_EXTERN unsigned32 _ISR_Nest_level;
+SCORE_EXTERN volatile unsigned32 _ISR_Nest_level;

 /*
 *  The following declares the Vector Table.  Application
@@ -234,7 +234,7 @@ SCORE_EXTERN Context_Control _Thread_BSP_context;
 *  moments.
 */

-SCORE_EXTERN unsigned32 _Thread_Dispatch_disable_level;
+SCORE_EXTERN volatile unsigned32 _Thread_Dispatch_disable_level;

 /*
 *  If this is non-zero, then the post-task switch extension
@@ -29,10 +29,19 @@
 *  directives available to an interrupt service routine are restricted.
 */

+#if defined(powerpc)
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS
+#endif
+
+#ifndef CPU_PROVIDES_ISR_IS_IN_PROGRESS
+
 RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
 {
  return (_ISR_Nest_level != 0);
 }
+#else
+#include <rtems/score/c_isr.inl>
+#endif

 /*PAGE
 *
@@ -346,7 +346,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
      }
    }
    /*
-     * must disable slave pic anyway
+     * must enable slave pic anyway
     */
    BSP_irq_enable_at_i8259s (2);
    _CPU_ISR_Enable(level);
@@ -374,6 +374,6 @@ void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx)
  }
  /*
   * I plan to process other thread related events here.
-   * This will include DEBUG session requsted from keyboard...
+   * This will include DEBUG session requested from keyboard...
   */
 }
@@ -93,7 +93,7 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_LINES_NUMBER]={
   *	255 means all other interrupts are masked
   * The second entry has a priority of 255 because
   * it is the slave pic entry and is should always remain
-   * unamsked.
+   * unmasked.
   */
  0,0,
  255,
@@ -0,0 +1,20 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/directory.cfg
+
+SRCS=README
+
+all: $(SRCS)
+
+# wrapup is the one that actually builds and installs the library
+#  from the individual .rel files built in other directories
+SUB_DIRS= console include pci residual openpic irq vectors start startup bootloader wrapup
@@ -0,0 +1,48 @@
+#
+#  $Id$
+#
+
+BSP NAME:           MCP750
+BOARD:              MCP750 from motorola
+BUS:                PCI
+CPU FAMILY:         ppc
+CPU:                PowerPC 750
+COPROCESSORS:       N/A
+MODE:               32 bit mode
+
+DEBUG MONITOR:      PPCBUG mode 
+
+PERIPHERALS
+===========
+TIMERS:             PPC internal Timebase register
+  RESOLUTION:         ???
+SERIAL PORTS:       simulated via bug
+REAL-TIME CLOCK:    PPC internal Decrementer register
+DMA:                none
+VIDEO:              none
+SCSI:               none
+NETWORKING:         DEC21140
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER:       PPC internal
+IOSUPP DRIVER:      N/A
+SHMSUPP:            N/A
+TIMER DRIVER:       PPC internal
+TTY DRIVER:         PPC internal
+
+STDIO
+=====
+PORT:               Console port 0
+ELECTRICAL:         na
+BAUD:               na
+BITS PER CHARACTER: na
+PARITY:             na
+STOP BITS:          na
+
+Notes
+=====
+
+Based on papyrus bsp which only really supports
+the PowerOpen ABI with an ELF assembler.
+
@@ -0,0 +1,84 @@
+#
+#  $Id: 
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@:@srcdir@/../../../shared:@srcdir@/../console
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=misc pci zlib mm em86 polled_io
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=bootldr.h zlib.h pci.h
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=head exception em86real consoleLib
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) 
+OBJS=$(S_O_FILES) $(C_O_FILES) 
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CC_PIECES=
+CC_FILES=$(CC_PIECES:%=%.cc)
+CC_O_FILES=$(CC_PIECES:%=${ARCH}/%.o)
+
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += -D__BOOT__ -DDEBUG
+CFLAGS   += -msoft-float -mstrict-align -fno-builtin -Wall -mmultiple -mstring \
+		-O2 -fomit-frame-pointer -mrelocatable -ffixed-r13 \
+		-mno-sdata -D__BOOT__ -DDEBUG 
+
+ASFLAGS	 += -mrelocatable 
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+IMAGES := rtems.gz
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += bootloader
+CLOBBER_ADDITIONS += $(IMAGES)
+
+bootloader : ${OBJS} $(IMAGES) $(BINARY_LOADED) ppcboot.lds
+	$(LD) -o bootloader $(OBJS) --just-symbols=$(BINARY_LOADED) \
+	-b binary $(IMAGES) -T @srcdir@/ppcboot.lds \
+	 -Map bootloader.map
+
+rtems.gz: $(BINARY_LOADED)
+	$(OBJCOPY)  $(BINARY_LOADED) rtems -O binary -R .comment -S 
+	gzip -vf9 rtems
+	rm -f rtems
+
+
+all:	${ARCH} $(SRCS) ${OBJ}
+
+
+
+
+
+
+
+
+
+
@@ -0,0 +1,94 @@
+OUTPUT_ARCH(powerpc)
+OUTPUT_FORMAT(ppcboot)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .text :
+  {
+    /* We have to build the header by hand, painful since ppcboot
+	format support is very poor in binutils. 
+	objdump -b ppcboot zImage --all-headers can be used to check. */
+    /* The following line can be added as a branch to use the same image
+     * for netboot as for prepboots, the only problem is that objdump
+     * did not in this case recognize the format since it insisted
+     * in checking the x86 code area held only zeroes. 
+     */
+    LONG(0x48000000+start);
+    . = 0x1be; BYTE(0x80); BYTE(0)
+    BYTE(2); BYTE(0); BYTE(0x41); BYTE(1);
+    BYTE(0x12); BYTE(0x4f); LONG(0);
+    BYTE(((_edata + 0x1ff)>>9)&0xff); 
+    BYTE(((_edata + 0x1ff)>>17)&0xff); 
+    BYTE(((_edata + 0x1ff)>>25)&0xff);
+    . = 0x1fe;
+    BYTE(0x55);
+    BYTE(0xaa);
+    BYTE(start&0xff);
+    BYTE((start>>8)&0xff);
+    BYTE((start>>16)&0xff);
+    BYTE((start>>24)&0xff);
+    BYTE(_edata&0xff);
+    BYTE((_edata>>8)&0xff);
+    BYTE((_edata>>16)&0xff);
+    BYTE((_edata>>24)&0xff);
+    BYTE(0); /* flags */
+    BYTE(0); /* os_id */
+    BYTE(0x4C); BYTE(0x69); BYTE(0x6e); 
+    BYTE(0x75); BYTE(0x78); /* Partition name */
+    . = 0x400;
+    *(.text)
+    *(.sdata2)
+    *(.rodata)
+  }
+/*  . = ALIGN(16); */
+  .image :
+  {
+    rtems.gz(*)
+    . = ALIGN(4);
+    *.gz(*)
+  }
+  /* Read-write section, merged into data segment: */
+  /* . = ALIGN(4096); */
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .handlers : 
+  {
+    *(.exception)
+  }
+
+  .data    :
+  {
+    *(.data)
+    *(.sdata)
+    . = ALIGN(4);
+    _edata = .;
+  }
+  PROVIDE(_binary_initrd_gz_start = 0);
+  PROVIDE(_binary_initrd_gz_end = 0);
+  _rtems_gz_size = _binary_rtems_gz_end - _binary_rtems_gz_start;
+  _rtems_size = __rtems_end - __rtems_start;
+  .bss :
+  {
+    *(.sbss)
+    *(.bss)
+    . = ALIGN(4);
+  }
+  __bss_words = SIZEOF(.bss)>>2;
+  __size = . ;
+  /DISCARD/ : 
+  {
+    *(.comment)
+  }
+}
+
@@ -0,0 +1,23 @@
+%rename cpp old_cpp
+%rename lib old_lib
+%rename endfile old_endfile
+%rename startfile old_startfile
+%rename link old_link
+
+*cpp:
+%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
+
+*lib:
+%{!qrtems: %(old_lib)} %{qrtems: --start-group \
+%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \
+-lc -lgcc --end-group  ecrtn%O%s \
+%{!qnolinkcmds: -T linkcmds%s}}
+
+*startfile:
+%{!qrtems: %(old_startfile)} %{qrtems:  ecrti%O%s \
+%{!qrtems_debug: start.o%s} \
+%{qrtems_debug: start_g.o%s}}
+
+*link:
+%{!qrtems: %(old_link)} %{qrtems: -Qy -dp -Bstatic -T linkcmds%s -e __rtems_entry_point -u __vectors}
+
@@ -0,0 +1,63 @@
+#
+#  $Id: 
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@:@srcdir@/../../../shared
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=polled_io uart console inch
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/consoleIo.h $(srcdir)/keyboard.h $(srcdir)/uart.h
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) 
+OBJS=$(S_O_FILES) $(C_O_FILES) 
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CC_PIECES=
+CC_FILES=$(CC_PIECES:%=%.cc)
+CC_O_FILES=$(CC_PIECES:%=${ARCH}/%.o)
+
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+CPPFLAGS += -DSTATIC_LOG_ALLOC
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+all:	${ARCH} $(SRCS) preinstall ${OBJS}
+
+
+
+
+
+
+
+
+
+
@@ -0,0 +1,33 @@
+#ifndef __CONSOLE_IO_H
+#define __CONSOLE_IO_H
+
+
+typedef enum {
+  CONSOLE_LOG 		= 1,
+  CONSOLE_SERIAL       	= 2,
+  CONSOLE_VGA		= 3,
+  CONSOLE_VACUUM	= 4
+}ioType;
+
+typedef volatile unsigned char * __io_ptr;
+
+typedef struct {
+  __io_ptr io_base;
+  __io_ptr isa_mem_base;
+  __io_ptr pci_mmio_base;
+  __io_ptr pci_dma_offset;
+} board_memory_map;
+
+extern board_memory_map *ptr_mem_map;
+extern unsigned long ticks_per_ms;
+
+extern int select_console(ioType t);
+extern int printk(const char *, ...) __attribute__((format(printf, 1, 2)));
+extern void udelay(int);
+extern void debug_putc(const unsigned char c);
+extern int debug_getc(void);
+extern int debug_tstc(void);
+int kbdreset(void);
+
+
+#endif
@@ -0,0 +1,23 @@
+/*
+ * $Id$
+ *	
+ * This code is loaded by the ROM loader at some arbitrary location.
+ * Move it to high memory so that it can load the kernel at 0x0000.
+ *
+ */
+/* A few utility functions, some copied from arch/ppc/lib/string.S */
+#include <libcpu/cpu.h>
+#include <rtems/score/targopts.h>
+#include "asm.h"
+		
+	.text
+	
+        .globl  strlen
+	.type	strlen,@function
+strlen:
+        addi    r4,r3,-1
+1:      lbzu    r0,1(r4)
+        cmpwi   0,r0,0
+        bne     1b
+        subf    r3,r3,r4
+        blr
@@ -0,0 +1,169 @@
+
+
+/*
+ * This software is Copyright (C) 1998 by T.sqware - all rights limited
+ * It is provided in to the public domain "as is", can be freely modified
+ * as far as this copyight notice is kept unchanged, but does not imply
+ * an endorsement by T.sqware of the product in which it is included.
+ */
+
+#ifndef _BSPUART_H
+#define _BSPUART_H
+
+void BSP_uart_init(int uart, int baud, int hwFlow);
+void BSP_uart_set_baud(int aurt, int baud);
+void BSP_uart_intr_ctrl(int uart, int cmd);
+void BSP_uart_throttle(int uart);
+void BSP_uart_unthrottle(int uart);
+int  BSP_uart_polled_status(int uart);
+void BSP_uart_polled_write(int uart, int val);
+int  BSP_uart_polled_read(int uart);
+void BSP_uart_termios_set(int uart, void *ttyp);
+int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
+int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
+void BSP_uart_termios_isr_com1();
+void BSP_uart_termios_isr_com2();
+void BSP_uart_dbgisr_com1(void);
+void BSP_uart_dbgisr_com2(void);
+extern unsigned BSP_poll_char_via_serial(void);
+extern void BSP_output_char_via_serial(int val);
+extern int BSPConsolePort;
+extern int BSPBaseBaud;
+/*
+ * Command values for BSP_uart_intr_ctrl(),
+ * values are strange in order to catch errors 
+ * with assert
+ */
+#define BSP_UART_INTR_CTRL_DISABLE  (0)
+#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
+#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
+#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
+
+/* Return values for uart_polled_status() */
+#define BSP_UART_STATUS_ERROR    (-1) /* No character */
+#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
+#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
+#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
+
+/* PC UART definitions */
+#define BSP_UART_COM1            (0)
+#define BSP_UART_COM2            (1)
+
+/*
+ * Base IO for UART
+ */
+
+#define COM1_BASE_IO	0x3F8
+#define COM2_BASE_IO	0x2F8
+
+/*
+ * Offsets from base
+ */
+
+/* DLAB 0 */
+#define RBR  (0)    /* Rx Buffer Register (read) */
+#define THR  (0)    /* Tx Buffer Register (write) */
+#define IER  (1)    /* Interrupt Enable Register */
+
+/* DLAB X */
+#define IIR  (2)    /* Interrupt Ident Register (read) */
+#define FCR  (2)    /* FIFO Control Register (write) */
+#define LCR  (3)    /* Line Control Register */
+#define MCR  (4)    /* Modem Control Register */
+#define LSR  (5)    /* Line Status Register */
+#define MSR  (6)    /* Modem Status  Register */
+#define SCR  (7)    /* Scratch register */
+
+/* DLAB 1 */
+#define DLL  (0)    /* Divisor Latch, LSB */
+#define DLM  (1)    /* Divisor Latch, MSB */
+#define AFR  (2)    /* Alternate Function register */
+
+/*
+ * Interrupt source definition via IIR
+ */
+#define MODEM_STATUS				0
+#define NO_MORE_INTR				1
+#define TRANSMITTER_HODING_REGISTER_EMPTY	2
+#define RECEIVER_DATA_AVAIL			4
+#define RECEIVER_ERROR  			6
+#define CHARACTER_TIMEOUT_INDICATION		12
+
+/*
+ * Bits definition of IER
+ */
+#define	RECEIVE_ENABLE		0x1
+#define	TRANSMIT_ENABLE		0x2
+#define RECEIVER_LINE_ST_ENABLE	0x4
+#define MODEM_ENABLE	   	0x8
+#define INTERRUPT_DISABLE	0x0
+
+/*
+ * Bits definition of the Line Status Register (LSR)
+ */
+#define DR	0x01	/* Data Ready */
+#define OE	0x02	/* Overrun Error */
+#define PE	0x04	/* Parity Error */
+#define FE	0x08	/* Framing Error */
+#define BI	0x10	/* Break Interrupt */
+#define THRE	0x20	/* Transmitter Holding Register Empty */
+#define TEMT	0x40	/* Transmitter Empty */
+#define ERFIFO	0x80	/* Error receive Fifo */
+
+/*
+ * Bits definition of the MODEM Control Register (MCR)
+ */
+#define DTR	0x01	/* Data Terminal Ready */
+#define RTS 	0x02	/* Request To Send */
+#define OUT_1	0x04	/* Output 1, (reserved on COMPAQ I/O Board) */
+#define OUT_2	0x08	/* Output 2, Enable Asynchronous Port Interrupts */
+#define LB	0x10	/* Enable Internal Loop Back */
+
+/*
+ * Bits definition of the Line Control Register (LCR)
+ */
+#define CHR_5_BITS 0
+#define CHR_6_BITS 1
+#define CHR_7_BITS 2
+#define CHR_8_BITS 3
+
+#define WL	0x03	/* Word length mask */
+#define STB	0x04	/* 1 Stop Bit, otherwise 2 Stop Bits */
+#define PEN	0x08	/* Parity Enabled */
+#define EPS	0x10	/* Even Parity Select, otherwise Odd */
+#define SP	0x20	/* Stick Parity */
+#define BCB	0x40	/* Break Control Bit */
+#define DLAB	0x80	/* Enable Divisor Latch Access */
+
+/*
+ * Bits definition of the MODEM Status Register (MSR)
+ */
+#define DCTS	0x01	/* Delta Clear To Send */
+#define DDSR	0x02	/* Delta Data Set Ready */
+#define TERI	0x04 	/* Trailing Edge Ring Indicator */
+#define DDCD	0x08	/* Delta Carrier Detect Indicator */
+#define CTS  	0x10 	/* Clear To Send (when loop back is active) */
+#define DSR	0x20	/* Data Set Ready (when loop back is active) */
+#define RI  	0x40 	/* Ring Indicator (when loop back is active) */
+#define DCD	0x80	/* Data Carrier Detect (when loop back is active) */
+
+/*
+ * Bits definition of the FIFO Control Register : WD16C552 or NS16550
+ */
+
+#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
+#define FIFO_EN	    0x01    /* Enable the FIFO */
+#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
+#define RCV_RESET   0x04    /* Receive FIFO Reset */
+#define FCR3	    0x08    /* do not understand manual! */
+
+#define RECEIVE_FIFO_TRIGGER1	0x0  /* trigger recieve interrupt after 1 byte  */
+#define RECEIVE_FIFO_TRIGGER4	0x40 /* trigger recieve interrupt after 4 byte  */
+#define RECEIVE_FIFO_TRIGGER8	0x80 /* trigger recieve interrupt after 8 byte  */
+#define RECEIVE_FIFO_TRIGGER12	0xc0 /* trigger recieve interrupt after 12 byte */
+#define TRIG_LEVEL  		0xc0 /* Mask for the trigger level 		*/
+
+#endif /* _BSPUART_H */
+
+
+
@@ -0,0 +1,35 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+H_FILES = $(srcdir)/nvram.h $(srcdir)/bsp.h
+
+#
+#  Equate files are for including from assembly preprocessed by
+#  gm4 or gasp.  No examples are provided except for those for
+#  other CPUs.  The best way to generate them would be to
+#  provide a program which generates the constants used based
+#  on the C equivalents.
+#
+
+EQ_FILES =
+
+SRCS=$(H_FILES) $(EQ_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)
+
+all:	$(SRCS) preinstall
@@ -0,0 +1,45 @@
+/*
+ * empty file. Just because referenced by portable application layer.
+ */
+#ifndef LIBBSP_POWERPC_MCP750_BSP_H
+#define LIBBSP_POWERPC_MCP750_BSP_H
+
+#include <rtems.h>
+#include <console.h>
+#include <libcpu/io.h>
+#include <clockdrv.h>
+
+#ifndef ASM
+#define outport_byte(port,value) outb(value,port)
+#define outport_word(port,value) outw(value,port)
+#define outport_long(port,value) outl(value,port)
+
+#define inport_byte(port,value) (value = inb(port))
+#define inport_word(port,value) (value = inw(port))
+#define inport_long(port,value) (value = inl(port))
+/*
+ * Vital Board data Start using DATA RESIDUAL
+ */
+/*
+ * Total memory using RESIDUAL DATA
+ */
+unsigned int BSP_mem_size;
+/*
+ * PCI Bus Frequency
+ */
+unsigned int BSP_bus_frequency;
+/*
+ * processor clock frequency
+ */
+unsigned int BSP_processor_frequency;
+/*
+ * Time base divisior (how many tick for 1 second).
+ */
+unsigned int BSP_time_base_divisor;
+
+extern rtems_configuration_table  BSP_Configuration;
+extern void BSP_panic(char *s);
+extern int printk(const char *, ...) __attribute__((format(printf, 1, 2)));
+#endif
+
+#endif
@@ -0,0 +1,166 @@
+/*
+ * PreP compliant NVRAM access
+ */
+
+#ifndef _PPC_NVRAM_H
+#define _PPC_NVRAM_H
+
+#define NVRAM_AS0  0x74
+#define NVRAM_AS1  0x75
+#define NVRAM_DATA 0x77
+
+
+/* RTC Offsets */
+
+#define MOTO_RTC_SECONDS	0x1FF9
+#define MOTO_RTC_MINUTES	0x1FFA
+#define MOTO_RTC_HOURS		0x1FFB
+#define MOTO_RTC_DAY_OF_WEEK	0x1FFC
+#define MOTO_RTC_DAY_OF_MONTH	0x1FFD
+#define MOTO_RTC_MONTH		0x1FFE
+#define MOTO_RTC_YEAR		0x1FFF
+#define MOTO_RTC_CONTROLA       0x1FF8
+#define MOTO_RTC_CONTROLB       0x1FF9
+
+#ifndef BCD_TO_BIN
+#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
+#endif
+
+#ifndef BIN_TO_BCD
+#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
+#endif
+
+/* Structure map for NVRAM on PowerPC Reference Platform */
+/* All fields are either character/byte strings which are valid either
+  endian or they are big-endian numbers.
+
+  There are a number of Date and Time fields which are in RTC format,
+  big-endian. These are stored in UT (GMT).
+
+  For enum's: if given in hex then they are bit significant, i.e. only
+  one bit is on for each enum.
+*/
+
+#define NVSIZE 		4096	/* size of NVRAM */
+#define OSAREASIZE 	512	/* size of OSArea space */
+#define CONFSIZE 	1024	/* guess at size of Configuration space */
+
+#ifndef ASM
+
+typedef struct _SECURITY {
+  unsigned long BootErrCnt;	    /* Count of boot password errors */
+  unsigned long ConfigErrCnt;	    /* Count of config password errors */
+  unsigned long BootErrorDT[2];	    /* Date&Time from RTC of last error in pw */
+  unsigned long ConfigErrorDT[2];   /* Date&Time from RTC of last error in pw */
+  unsigned long BootCorrectDT[2];   /* Date&Time from RTC of last correct pw */
+  unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */
+  unsigned long BootSetDT[2];	    /* Date&Time from RTC of last set of pw */
+  unsigned long ConfigSetDT[2];	    /* Date&Time from RTC of last set of pw */
+  unsigned char Serial[16];	    /* Box serial number */
+} SECURITY;
+
+typedef enum _OS_ID {
+  Unknown 	= 0,
+  Firmware 	= 1,
+  AIX 		= 2,
+  NT 		= 3,
+  MKOS2 	= 4,
+  MKAIX 	= 5,
+  Taligent 	= 6,
+  Solaris 	= 7,
+  MK 		= 12
+} OS_ID;
+
+typedef struct _ERROR_LOG {
+  unsigned char ErrorLogEntry[40]; /* To be architected */
+} ERROR_LOG;
+
+typedef enum _BOOT_STATUS {
+  BootStarted 		= 0x01,
+  BootFinished 		= 0x02,
+  RestartStarted 	= 0x04,
+  RestartFinished 	= 0x08,
+  PowerFailStarted 	= 0x10,
+  PowerFailFinished 	= 0x20,
+  ProcessorReady 	= 0x40,
+  ProcessorRunning 	= 0x80,
+  ProcessorStart 	= 0x0100
+} BOOT_STATUS;
+
+typedef struct _RESTART_BLOCK {
+  unsigned short 		Version;
+  unsigned short 		Revision;
+  unsigned long 		ResumeReserve1[2];
+  volatile unsigned long	BootStatus;
+  unsigned long 		CheckSum; 		/* Checksum of RESTART_BLOCK */
+  void* 			RestartAddress;
+  void* 			SaveAreaAddr;
+  unsigned long 		SaveAreaLength;
+} RESTART_BLOCK;
+
+typedef enum _OSAREA_USAGE {
+  Empty = 0,
+  Used  = 1
+} OSAREA_USAGE;
+
+typedef enum _PM_MODE {
+  Suspend = 0x80, /* Part of state is in memory */
+  Normal  = 0x00  /* No power management in effect */
+} PMMode;
+
+typedef struct _HEADER {
+  unsigned short 	Size;       /* NVRAM size in K(1024) */
+  unsigned char 	Version;     /* Structure map different */
+  unsigned char 	Revision;    /* Structure map the same -may
+					be new values in old fields
+					in other words old code still works */
+  unsigned short 	Crc1;       /* check sum from beginning of nvram to OSArea */
+  unsigned short 	Crc2;       /* check sum of config */
+  unsigned char 	LastOS;     /* OS_ID */
+  unsigned char 	Endian;     /* B if big endian, L if little endian */
+  unsigned char 	OSAreaUsage;/* OSAREA_USAGE */
+  unsigned char 	PMMode;     /* Shutdown mode */
+  RESTART_BLOCK 	RestartBlock;
+  SECURITY 		Security;
+  ERROR_LOG 		ErrorLog[2];
+
+  /* Global Environment information */
+  void* 		GEAddress;
+  unsigned long 	GELength;
+
+  /* Date&Time from RTC of last change to Global Environment */
+  unsigned long 	GELastWriteDT[2];
+
+  /* Configuration information */
+  void* 		ConfigAddress;
+  unsigned long 	ConfigLength;
+
+  /* Date&Time from RTC of last change to Configuration */
+  unsigned long 	ConfigLastWriteDT[2];
+  unsigned long 	ConfigCount; /* Count of entries in Configuration */
+
+  /* OS dependent temp area */
+  void* 		OSAreaAddress;
+  unsigned long 	OSAreaLength;
+
+  /* Date&Time from RTC of last change to OSAreaArea */
+  unsigned long 	OSAreaLastWriteDT[2];
+} HEADER;
+
+/* Here is the whole map of the NVRAM */
+typedef struct _NVRAM_MAP {
+  HEADER 	Header;
+  unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)];
+  unsigned char OSArea[OSAREASIZE];
+  unsigned char ConfigArea[CONFSIZE];
+} NVRAM_MAP;
+
+/* Routines to manipulate the NVRAM */
+void init_prep_nvram(void);
+char *prep_nvram_get_var(const char *name);
+char *prep_nvram_first_var(void);
+char *prep_nvram_next_var(char *name);
+
+#endif /* ASM */
+	  
+#endif /* _PPC_NVRAM_H */
@@ -0,0 +1,59 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=irq_init i8259 irq
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/irq.h
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=irq_asm
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+OBJS=$(S_O_FILES) $(C_O_FILES) $(CC_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+all:	${ARCH} $(SRCS) preinstall ${OBJS}
+
+install:  all
@@ -0,0 +1,152 @@
+/* i8259.c
+ *
+ *  This file contains the implementation of the function described in irq.h
+ *  related to Intel 8259 Programmable Interrupt controller.
+ *
+ *  CopyRight (C) 1998 valette@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+
+#include <bsp.h>
+#include <bsp/irq.h>
+
+/*-------------------------------------------------------------------------+
+| Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register.
+--------------------------------------------------------------------------*/
+/*
+ * lower byte is interrupt mask on the master PIC.
+ * while upper bits are interrupt on the slave PIC.
+ * This cache is initialized in ldseg.s
+ */
+volatile rtems_i8259_masks i8259s_cache;
+
+/*-------------------------------------------------------------------------+
+|         Function:  BSP_irq_disable_at_i8259s
+|      Description: Mask IRQ line in appropriate PIC chip.
+| Global Variables: i8259s_cache
+|        Arguments: vector_offset - number of IRQ line to mask.
+|          Returns: Nothing. 
+--------------------------------------------------------------------------*/
+int BSP_irq_disable_at_i8259s    (const rtems_irq_symbolic_name irqLine)
+{
+  unsigned short mask;
+  unsigned int 	level;
+
+  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
+       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
+       )
+    return 1;
+  
+  _CPU_ISR_Disable(level);
+  
+  mask = 1 << irqLine;
+  i8259s_cache |= mask;
+  
+  if (irqLine < 8)
+  {
+    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
+  }
+  else
+  {
+    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
+  }
+  _CPU_ISR_Enable (level);
+
+  return 0;
+} 
+
+/*-------------------------------------------------------------------------+
+|         Function:  BSP_irq_enable_at_i8259s
+|      Description: Unmask IRQ line in appropriate PIC chip.
+| Global Variables: i8259s_cache
+|        Arguments: irqLine - number of IRQ line to mask.
+|          Returns: Nothing. 
+--------------------------------------------------------------------------*/
+int BSP_irq_enable_at_i8259s    (const rtems_irq_symbolic_name irqLine)
+{
+  unsigned short mask;
+  unsigned int 	level;
+
+  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
+       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET )
+       )
+    return 1;
+
+  _CPU_ISR_Disable(level);
+  
+  mask = ~(1 << irqLine);
+  i8259s_cache &= mask;
+  
+  if (irqLine < 8)
+  {
+    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
+  }
+  else
+  {
+    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
+  }
+  _CPU_ISR_Enable (level);
+
+  return 0;
+} /* mask_irq */
+
+int BSP_irq_enabled_at_i8259s        	(const rtems_irq_symbolic_name irqLine)
+{
+  unsigned short mask;
+
+  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
+       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
+     )
+    return 1;
+
+  mask = (1 << irqLine);
+  return  (~(i8259s_cache & mask));
+}
+  
+
+/*-------------------------------------------------------------------------+
+|         Function: BSP_irq_ack_at_i8259s
+|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
+| Global Variables: None.
+|        Arguments: irqLine - number of IRQ line to acknowledge.
+|          Returns: Nothing. 
+--------------------------------------------------------------------------*/
+int BSP_irq_ack_at_i8259s  	(const rtems_irq_symbolic_name irqLine)
+{
+  if (irqLine >= 8) {
+   outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI);
+  }
+  outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI);
+
+  return 0;
+
+} /* ackIRQ */
+
+void BSP_i8259s_init(void)
+{
+  /*
+   * init master 8259 interrupt controller
+   */
+  outport_byte(PIC_MASTER_COMMAND_IO_PORT, 0x11); /* Start init sequence */
+  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x00);/* Vector base  = 0 */
+  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x04);/* edge tiggered, Cascade (slave) on IRQ2 */
+  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x01);/* Select 8086 mode */
+  outport_byte(PIC_MASTER_IMR_IO_PORT, 0xFB); /* Mask all except cascade */
+  /*
+   * init slave  interrupt controller
+   */
+  outport_byte(PIC_SLAVE_COMMAND_IO_PORT, 0x11); /* Start init sequence */
+  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x08);/* Vector base  = 8 */
+  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x02);/* edge triggered, Cascade (slave) on IRQ2 */
+  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x01); /* Select 8086 mode */
+  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */
+  
+  i8259s_cache = 0xFFFB;
+}
+
@@ -0,0 +1,62 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+PGM=${ARCH}/openpic.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=$(OPENPIC_PIECES)
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/openpic.h
+
+SRCS=$(C_FILES) $(H_FILES)
+OBJS=$(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+OPENPIC_PIECES=openpic
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+all:	${ARCH} $(SRCS) preinstall $(PGM)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+install:  all
@@ -0,0 +1,62 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+PGM=${ARCH}/pci.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=$(PCI_PIECES)
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/pci.h
+
+SRCS=$(C_FILES) $(H_FILES)
+OBJS=$(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+PCI_PIECES=pci
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+all:	${ARCH} $(SRCS) preinstall $(PGM)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+install:  all
@@ -0,0 +1,62 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+PGM=${ARCH}/residual.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=$(RESIDUAL_PIECES)
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/pnp.h $(srcdir)/residual.h 
+
+SRCS=$(C_FILES) $(H_FILES)
+OBJS=$(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+RESIDUAL_PIECES=residual
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+all:	${ARCH} $(SRCS) preinstall $(PGM)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+install:  all
@@ -0,0 +1,91 @@
+#include <bsp/residual.h>
+#include <libcpu/io.h>
+#include <libcpu/byteorder.h>
+
+
+static int same_DevID(unsigned short vendor,
+	       unsigned short Number,
+	       char * str) 
+{
+	static unsigned const char hexdigit[]="0123456789ABCDEF";
+	if (strlen(str)!=7) return 0;
+	if ( ( ((vendor>>10)&0x1f)+'A'-1 == str[0])  &&
+	     ( ((vendor>>5)&0x1f)+'A'-1 == str[1])   &&
+	     ( (vendor&0x1f)+'A'-1 == str[2])        &&
+	     (hexdigit[(Number>>12)&0x0f] == str[3]) &&
+	     (hexdigit[(Number>>8)&0x0f] == str[4])  &&
+	     (hexdigit[(Number>>4)&0x0f] == str[5])  &&
+	     (hexdigit[Number&0x0f] == str[6]) ) return 1;
+	return 0;
+}
+
+PPC_DEVICE *residual_find_device(RESIDUAL *res,unsigned long BusMask,
+				 unsigned char * DevID,
+				 int BaseType,
+				 int SubType,
+				 int Interface,
+				 int n)
+{
+	int i;
+	if ( !res || !res->ResidualLength ) return NULL;
+	for (i=0; i<res->ActualNumDevices; i++) {
+#define Dev res->Devices[i].DeviceId
+		if ( (Dev.BusId&BusMask)                                  &&
+		     (BaseType==-1 || Dev.BaseType==BaseType)             &&
+		     (SubType==-1 || Dev.SubType==SubType)                &&
+		     (Interface==-1 || Dev.Interface==Interface)          &&
+		     (DevID==NULL || same_DevID((Dev.DevId>>16)&0xffff,
+						Dev.DevId&0xffff, DevID)) &&
+		     !(n--) ) return res->Devices+i;
+#undef Dev
+	}
+	return 0;
+}
+
+PnP_TAG_PACKET *PnP_find_packet(unsigned char *p,
+				unsigned packet_tag,
+				int n)
+{
+	unsigned mask, masked_tag, size;
+	if(!p) return 0;
+	if (tag_type(packet_tag)) mask=0xff; else mask=0xF8;
+	masked_tag = packet_tag&mask;
+	for(; *p != END_TAG; p+=size) {
+		if ((*p & mask) == masked_tag && !(n--)) 
+			return (PnP_TAG_PACKET *) p;
+		if (tag_type(*p))
+			size=ld_le16((unsigned short *)(p+1))+3;
+		else 
+			size=tag_small_count(*p)+1;
+	}
+	return 0; /* not found */
+}
+
+PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
+					     unsigned packet_type,
+					     int n)
+{
+	int next=0;
+	while (p) {
+		p = (unsigned char *) PnP_find_packet(p, 0x70, next);
+		if (p && p[1]==packet_type && !(n--)) 
+			return (PnP_TAG_PACKET *) p;
+		next = 1;
+	};
+	return 0; /* not found */
+}
+
+PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
+					   unsigned packet_type,
+					   int n)
+{
+	int next=0;
+	while (p) {
+		p = (unsigned char *) PnP_find_packet(p, 0x84, next);
+		if (p && p[3]==packet_type && !(n--)) 
+			return (PnP_TAG_PACKET *) p;
+		next = 1;
+	};
+	return 0; /* not found */
+}
+
@@ -5,8 +5,8 @@
@SET_MAKE@
 srcdir = @srcdir@
 top_srcdir = @top_srcdir@
-top_builddir = ../../../../../../../..
-subdir = c/src/exec/score/cpu/powerpc/rtems/score
+top_builddir = ../../../../../../..
+subdir = c/src/lib/libbsp/powerpc/mcp750/start

 INSTALL = @INSTALL@

@@ -15,16 +15,17 @@ PROJECT_ROOT = @PROJECT_ROOT@

 VPATH = @srcdir@

+PGM=${ARCH}/start.o
+
 # C source names, if any, go here -- minus the .c
 C_PIECES=
 C_FILES=$(C_PIECES:%=%.c)
 C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)

-H_PIECES=cpu.h ppc.h ppctypes.h
-H_FILES=$(H_PIECES:%=$(srcdir)/%)
+H_FILES=

 # Assembly source names, if any, go here -- minus the .S
-S_PIECES=
+S_PIECES=start 
 S_FILES=$(S_PIECES:%=%.S)
 S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)

@@ -40,7 +41,7 @@ include $(RTEMS_ROOT)/make/leaf.cfg

 DEFINES  +=
 CPPFLAGS +=
-CFLAGS   += 
+CFLAGS   +=

 LD_PATHS  +=
 LD_LIBS   +=
@@ -54,16 +55,10 @@ LDFLAGS   +=
 #

 CLEAN_ADDITIONS +=
-CLOBBER_ADDITIONS += $(BUILT_SOURCES)
+CLOBBER_ADDITIONS +=

-# Install the program(s), appending _g or _p as appropriate.
-# for include files, just use $(INSTALL_CHANGE)
-all: install-headers
-
-install-headers: ${H_FILES}
-	$(INSTALL_CHANGE) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
-
-preinstall: install-headers
+all:	${ARCH} $(SRCS) $(OBJS) $(PGM)
+	$(INSTALL_VARIANT) -m 555 ${PGM} ${PROJECT_RELEASE}/lib

 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	cd $(top_builddir) \
@@ -0,0 +1,149 @@
+/*
+ *  arch/ppc/kernel/head.S
+ *
+ *  $Id$
+ *
+ *  PowerPC version 
+ *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
+ *  Adapted for Power Macintosh by Paul Mackerras.
+ *  Low-level exception handlers and MMU support
+ *  rewritten by Paul Mackerras.
+ *    Copyright (C) 1996 Paul Mackerras.
+ *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
+ *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
+ *
+ *  This file contains the low-level support and setup for the
+ *  PowerPC platform, including trap and interrupt dispatch.
+ *  Also included here is low-level thread/task switch support.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *	
+ */
+
+#include <libcpu/cpu.h>
+#include <libcpu/io.h>
+#include <rtems/score/targopts.h>
+#include "asm.h"
+	
+#define SYNC \
+	sync; \
+	isync
+
+#define KERNELBASE	0x0
+
+#define MONITOR_ENTER			\
+	mfmsr	r10		;	\
+	ori	r10,r10,MSR_IP	;	\
+	mtmsr	r10		;	\
+	li	r10,0x63	;	\
+	sc
+			
+	.text
+	.globl	__rtems_entry_point
+	.type	__rtems_entry_point,@function
+__rtems_entry_point:
+#ifdef DEBUG_EARLY_START
+	MONITOR_ENTER
+#endif	
+		
+/* 
+ * PREP
+ * This is jumped to on prep systems right after the kernel is relocated
+ * to its proper place in memory by the boot loader.  The expected layout
+ * of the regs is:	
+ *   r3: ptr to residual data
+ *   r4: initrd_start or if no initrd then 0
+ *   r5: initrd_end - unused if r4 is 0
+ *   r6: Start of command line string
+ *   r7: End of command line string
+ *
+ */
+	
+	mr	r31,r3			/* save parameters */
+	mr	r30,r4
+	mr	r29,r5
+	mr	r28,r6
+	mr	r27,r7
+/*
+ * Use the first pair of BAT registers to map the 1st 64MB
+ * of RAM to KERNELBASE. 
+ */
+	lis	r11,KERNELBASE@h
+	ori	r11,r11,0x7fe		/* set up BAT registers for 604 */
+	li	r8,2			/* R/W access */
+	mtspr	DBAT0L,r8		/* N.B. 6xx (not 601) have valid */
+	mtspr	DBAT0U,r11		/* bit in upper BAT register */
+	mtspr	IBAT0L,r8
+	mtspr	IBAT0U,r11
+	isync
+
+/*
+ * we now have the 1st 64M of ram mapped with the bats.
+ */
+	
+enter_C_code:
+	bl	MMUon
+	/*
+	 * stack = &__rtems_end + 4096
+	 */
+	addis	r9,r0, __rtems_end+4096@ha
+        addi	r9,r9, __rtems_end+4096@l
+	mr	r1, r9
+	bl	zero_bss
+	/*
+	 * restore prep boot params
+	 */
+	mr	r3,r31
+	mr	r4,r30
+	mr	r5,r29
+	mr	r6,r28
+	mr	r7,r27 
+	bl	save_boot_params
+	bl	boot_card
+	bl	_return_to_ppcbug
+	
+	.globl  MMUon
+	.type	MMUon,@function
+MMUon:	
+	mfmsr	r0
+	ori	r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1
+	xori	r0, r0, MSR_EE | MSR_IP | MSR_FP
+	mflr	r11
+	mtsrr0	r11
+	mtsrr1	r0
+	SYNC
+	rfi
+	
+	.globl  MMUoff
+	.type	MMUoff,@function
+MMUoff:	
+	mfmsr	r0
+	ori	r0,r0,MSR_IR| MSR_DR | MSR_IP
+	mflr	r11
+	xori	r0,r0,MSR_IR|MSR_DR
+	mtsrr0	r11
+	mtsrr1	r0
+	SYNC
+	rfi
+
+	.globl	_return_to_ppcbug
+	.type	_return_to_ppcbug,@function
+
+	
+_return_to_ppcbug:
+	mflr	r30
+	bl	MMUoff
+	MONITOR_ENTER
+	bl	MMUon
+	mtctr	r30
+	bctr	
+	
+	
+
+
+
@@ -0,0 +1,56 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@:
+VPATH = @srcdir@:@srcdir@/../console:@srcdir@/../../../shared:
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=main bspstart bsppost bsplibc sbrk bspclean
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=consoleLib
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+OBJS=$(S_O_FILES) $(C_O_FILES) $(CC_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+all:	${ARCH} $(SRCS) $(OBJS)
+	$(INSTALL_VARIANT) -m 555 ${PGM} ${PROJECT_RELEASE}/lib
+	$(INSTALL_CHANGE) @srcdir@/linkcmds ${PROJECT_RELEASE}/lib
+
+${PROJECT_RELEASE}/lib/libbsp.a:
+	cd ../wrapup; $(MAKE)
@@ -0,0 +1,121 @@
+/*
+ *
+ */
+#include <bsp/consoleIo.h>
+#include <libcpu/spr.h>
+#include <bsp/residual.h>
+#include <bsp/pci.h>
+#include <bsp/openpic.h>
+#include <bsp/irq.h>
+#include <bsp.h>
+#include <libcpu/bat.h>
+
+extern void _return_to_ppcbug();
+extern unsigned long __rtems_end;
+
+RESIDUAL residualCopy;
+#define INIT_STACK_SIZE 0x1000
+#define INTR_STACK_SIZE 0x4000
+
+void BSP_panic(char *s)
+{
+  printk("RTEMS 4.x PANIC %s\n", s);
+  _return_to_ppcbug();
+}
+
+void _BSP_Fatal_error(unsigned int v)
+{
+  printk("RTEMS 4.x PANIC ERROR %x\n", v);
+  _return_to_ppcbug();
+}
+
+void
+boot_card(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options)
+{
+  int err;
+  unsigned char *stack;
+  unsigned l2cr;
+  register unsigned char* intrStack;
+  register unsigned int intrNestingLevel = 0;
+  
+  L1_caches_enables();
+  stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE;
+  intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE;
+  asm volatile ("mtspr	273, %0" : "=r" (intrStack) : "0" (intrStack));
+  asm volatile ("mtspr	272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
+  residualCopy = *r3;
+#define NO_DYNAMIC_EXCEPTION_VECTOR_INSTALL
+#undef  NO_DYNAMIC_EXCEPTION_VECTOR_INSTALL
+#ifndef NO_DYNAMIC_EXCEPTION_VECTOR_INSTALL  
+  initialize_exceptions();
+#endif
+  select_console(CONSOLE_LOG);
+
+  /* We check that the keyboard is present and immediately 
+   * select the serial console if not.
+   */
+  err = kbdreset();
+  if (err) select_console(CONSOLE_SERIAL);
+
+  
+  printk("Welcome to RTEMS 4.0.2 on Motorola MCP750\n\n\n");
+  printk("-----------------------------------------\n");
+  printk("Residuals are located at %x\n", (unsigned) r3);
+  printk("Additionnal boot options are %s\n", additional_boot_options);
+  printk("-----------------------------------------\n");
+
+  printk("Initial system stack at %x\n",stack);
+  l2cr = get_L2CR();
+  printk("Initial L2CR value = %x\n", l2cr);
+  if (! (l2cr & 0x80000000))
+    set_L2CR(0xb9A14000);
+#ifdef TEST_RETURN_TO_PPCBUG  
+  printk("Hit <Enter> to return to PPCBUG monitor\n");
+  printk("When Finished hit GO. It should print <Back from monitor>\n");
+  debug_getc();
+  _return_to_ppcbug();
+  printk("Back from monitor\n");
+  _return_to_ppcbug();
+#endif /* TEST_RETURN_TO_PPCBUG  */
+
+  /*
+   * Init MMU block address translation to enable hardware
+   * access
+   */
+  /*
+   * PC legacy IO space used for inb/outb and all PC
+   * compatible hardware
+   */
+  setdbat(1, 0x80000000, 0x80000000, 0x10000000, IO_PAGE);
+  /*
+   * PCI devices memory area. Needed to access OPENPIC features
+   * provided by the RAVEN
+   */
+  setdbat(2, 0xc0000000, 0xc0000000, 0x08000000, IO_PAGE);
+  /*
+   * Must have acces to open pic PCI ACK registers 
+   * provided by the RAVEN
+   */
+  setdbat(3, 0xfeff0000, 0xfeff0000, 0x10000, IO_PAGE);
+
+  printk("Going to start PCI buses scanning and initialization\n");
+  InitializePCI();
+  printk("Number of PCI buses is found : %d\n", BusCountPCI());
+#ifdef TEST_RAW_EXCEPTION_CODE  
+  printk("Testing exception handling Part 1\n");
+  /*
+   * Cause a software exception
+   */
+  __asm__ __volatile ("sc");
+  /*
+   * Check we can still catch exceptions
+   */
+  printk("Testing exception handling Part 2\n");
+  __asm__ __volatile ("sc");
+#endif  
+  BSP_rtems_irq_mng_init(0);
+  printk("Init done\n");
+  debug_getc();
+  while(1);
+}
+
@@ -0,0 +1,147 @@
+OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
+              "elf32-powerpc")
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PROVIDE (__stack = 0);
+MEMORY {
+	VECTORS	: ORIGIN = 0x0 ,  LENGTH = 0x3000
+	CODE : ORIGIN = 0x3000 , LENGTH = 0x100000 
+}
+SECTIONS
+{
+  .entry_point_section :
+  {
+	*(.entry_point_section)
+  } > VECTORS
+
+  /*
+   * This section is used only if NO_DYNAMIC_EXCEPTION_VECTOR_INSTALL
+   * is defined in vectors/vectors.S
+   */
+  .vectors :
+  {
+    *(.vectors)
+  } > VECTORS
+
+  /* Read-only sections, merged into text segment: */
+  .interp   : { *(.interp) }	> CODE
+  .hash           : { *(.hash)          }	> CODE
+  .dynsym         : { *(.dynsym)                }	> CODE
+  .dynstr         : { *(.dynstr)                }	> CODE
+  .gnu.version   : { *(.gnu.version)      }	> CODE
+  .gnu.version_d   : { *(.gnu.version_d)  }	> CODE
+  .gnu.version_r   : { *(.gnu.version_r)  }	> CODE
+  .rela.text     :
+    { *(.rela.text) *(.rela.gnu.linkonce.t*) }	> CODE
+  .rela.data     :
+    { *(.rela.data) *(.rela.gnu.linkonce.d*) }	> CODE
+  .rela.rodata   :
+    { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }	> CODE
+  .rela.got       : { *(.rela.got)      }	> CODE
+  .rela.got1      : { *(.rela.got1)     }	> CODE
+  .rela.got2      : { *(.rela.got2)     }	> CODE
+  .rela.ctors     : { *(.rela.ctors)    }	> CODE
+  .rela.dtors     : { *(.rela.dtors)    }	> CODE
+  .rela.init      : { *(.rela.init)     }	> CODE
+  .rela.fini      : { *(.rela.fini)     }	> CODE
+  .rela.bss       : { *(.rela.bss)      }	> CODE
+  .rela.plt       : { *(.rela.plt)      }	> CODE
+  .rela.sdata     : { *(.rela.sdata)    }	> CODE
+  .rela.sbss      : { *(.rela.sbss)     }	> CODE
+  .rela.sdata2    : { *(.rela.sdata2)   }	> CODE
+  .rela.sbss2     : { *(.rela.sbss2)    }	> CODE
+  .text      :	
+  {
+    *(.text)	
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  }  > CODE
+  .init           : { *(.init)          } 	> CODE
+  .fini           : { *(.fini)          } 	> CODE
+  .rodata         : { *(.rodata) *(.gnu.linkonce.r*) }	> CODE
+  .rodata1        : { *(.rodata1) }	> CODE
+  _etext = .;
+  PROVIDE (etext = .);
+  .sdata2   : { *(.sdata2) }	> CODE
+  .sbss2   : { *(.sbss2) }	> CODE
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  It would
+     be more correct to do this:
+       . = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1));
+     The current expression does not correctly handle the case of a
+     text segment ending precisely at the end of a page; it causes the
+     data segment to skip a page.  The above expression does not have
+     this problem, but it will currently (2/95) cause BFD to allocate
+     a single segment, combining both text and data, for this case.
+     This will prevent the text segment from being shared among
+     multiple executions of the program; I think that is more
+     important than losing a page of the virtual address space (note
+     that no actual memory is lost; the page which is skipped can not
+     be referenced).  */
+  . = ALIGN(0x1000);
+ .data    :
+  {
+    *(.data)
+    *(.gnu.linkonce.d*)	
+    CONSTRUCTORS
+  } > CODE
+  .data1   : { *(.data1) }	> CODE
+  PROVIDE (__EXCEPT_START__ = .);
+  .gcc_except_table   : { *(.gcc_except_table) } > CODE
+  PROVIDE (__EXCEPT_END__ = .);
+  .got1           : { *(.got1) }	> CODE
+  .dynamic        : { *(.dynamic) }	> CODE
+  /* Put .ctors and .dtors next to the .got2 section, so that the pointers
+     get relocated with -mrelocatable. Also put in the .fixup pointers.
+     The current compiler no longer needs this, but keep it around for 2.7.2  */
+                PROVIDE (_GOT2_START_ = .);
+  .got2           :  { *(.got2) }	> CODE
+                PROVIDE (__CTOR_LIST__ = .);
+  .ctors          : { *(.ctors) }	> CODE
+                PROVIDE (__CTOR_END__ = .);
+                PROVIDE (__DTOR_LIST__ = .);
+  .dtors          : { *(.dtors) }	> CODE
+                PROVIDE (__DTOR_END__ = .);
+                PROVIDE (_FIXUP_START_ = .);
+  .fixup          : { *(.fixup) }	> CODE
+                PROVIDE (_FIXUP_END_ = .);
+                PROVIDE (_GOT2_END_ = .);
+                PROVIDE (_GOT_START_ = .);
+  .got            : { *(.got) }	> CODE
+  .got.plt        : { *(.got.plt) }	> CODE
+                PROVIDE (_GOT_END_ = .);
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          : { *(.sdata) }	> CODE
+  _edata  =  .;
+  PROVIDE (edata = .);
+  .sbss      :
+  {
+    PROVIDE (__sbss_start = .);
+    *(.sbss)
+    *(.scommon)
+    *(.dynsbss)
+    PROVIDE (__sbss_end = .);
+  } > CODE
+  .plt   : { *(.plt) }	> CODE
+  .bss       :
+  {
+   PROVIDE (__bss_start = .);
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  . = ALIGN(16);
+  } > CODE
+  . = ALIGN(16);
+  _end = . ;
+  __rtems_end = . ;
+  PROVIDE (end = .);
+  /DISCARD/ : 
+  {
+    *(.comment)
+  }
+}
@@ -0,0 +1,64 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@:@srcdir@/../console:
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+INSTALL = @INSTALL@
+
+PGM=${ARCH}/vectors.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=vectors_init 
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=$(srcdir)/vectors.h
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=vectors 
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+OBJS=$(S_O_FILES) $(C_O_FILES) $(CC_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+preinstall:
+	$(MKDIR) $(PROJECT_INCLUDE)/bsp
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/bsp
+
+all:	${ARCH} $(SRCS) preinstall $(OBJS) $(PGM)
+
+
@@ -0,0 +1,142 @@
+/*
+ * (c) 1999, Eric Valette valette@crf.canon.fr
+ *
+ *
+ *  This file contains the assembly code for the PowerPC 
+ *  exception veneers for RTEMS.
+ *
+ * $Id$
+ */
+	
+
+
+#include <bsp/vectors.h>
+#include <libcpu/cpu.h>
+#include <rtems/score/targopts.h>
+#include "asm.h"
+	
+
+#define SYNC \
+	sync; \
+	isync
+	
+	PUBLIC_VAR (__rtems_start)
+	.section .entry_point_section,"awx",@progbits
+/*
+ * Entry point information used by bootloader code
+ */
+SYM (__rtems_start):		
+	.long   __rtems_entry_point
+
+	/*
+	 * end of special Entry point section
+	 */	
+	.text
+	.p2align 5	
+		
+PUBLIC_VAR(default_exception_vector_code_prolog)
+SYM (default_exception_vector_code_prolog):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r3, GPR3_OFFSET(r1)
+	stw	r2, GPR2_OFFSET(r1)
+	mflr	r2
+	stw	r2, EXC_LR_OFFSET(r1)
+	bl	0f
+0:	/*
+	 * r3 = exception vector entry point 
+	 * (256 * vector number) + few instructions
+	 */
+	mflr	r3
+	/*
+	 * r3 = r3 >> 8 = vector
+	 */
+	srwi	r3,r3,8
+	ba	push_normalized_frame
+	
+	PUBLIC_VAR (default_exception_vector_code_prolog_size)
+	
+	default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog
+	
+	.p2align 5
+PUBLIC_VAR (push_normalized_frame)	
+SYM (push_normalized_frame):
+	stw	r3, EXCEPTION_NUMBER_OFFSET(r1)
+	stw	r0, GPR0_OFFSET(r1)
+	mfsrr0  r2
+	stw	r2, SRR0_FRAME_OFFSET(r1)
+	mfsrr1  r3
+	stw	r3, SRR1_FRAME_OFFSET(r1)
+	/*
+	 * Save general purpose registers
+	 * Already saved in prolog : R1, R2, R3, LR.
+	 * Saved a few line above  : R0
+	 *
+	 * Manual says that "stmw" instruction may be slower than
+	 * series of individual "stw" but who cares about performance 
+	 * for the DEFAULT exception handler?
+	 */
+	stmw	r4, GPR4_OFFSET(r1)	/* save R4->R31 */
+
+	mfcr	r31
+	stw	r31,  EXC_CR_OFFSET(r1)
+	mfctr	r30
+	stw	r30,  EXC_CTR_OFFSET(r1)
+	mfxer	r28
+	stw	r28,  EXC_XER_OFFSET(r1)
+	/*
+	 * Enable data and instruction address translation, exception nesting
+	 */
+	mfmsr	r3
+	ori     r3,r3, MSR_RI | MSR_IR | MSR_DR
+	mtmsr   r3
+	SYNC
+	
+	/*
+	 * Call C exception handler
+	 */
+	addi	r3, r1, 0x8
+	bl C_exception_handler
+	/*
+	 * Restore registers status
+	 */
+	lwz	r31,  EXC_CR_OFFSET(r1)
+	mtcr	r31
+	lwz	r30,  EXC_CTR_OFFSET(r1)
+	mtctr	r30
+	lwz	r29,  EXC_LR_OFFSET(r1)
+	mtlr	r29
+	lwz	r28,  EXC_XER_OFFSET(r1)
+	mtxer	r28
+
+	lmw	r4, GPR4_OFFSET(r1)
+	lwz	r2, GPR2_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)
+
+	/*
+	 * Disable data and instruction translation. Make path non recoverable...
+	 */
+	mfmsr	r3
+	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
+	mtmsr   r3
+	SYNC
+	/*
+	 * Restore rfi related settings
+	 */
+		 
+	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	mtsrr1	r3
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	mtsrr0	r3
+	
+	lwz	r3, GPR3_OFFSET(r1)
+	addi 	r1,r1, EXCEPTION_FRAME_END
+	SYNC
+	rfi
+
+
+
+
+
@@ -0,0 +1,123 @@
+#ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
+#define LIBBSP_POWERPC_MCP750_VECTORS_H
+
+/*
+ * The callee (high level exception code written in C) 
+ * will store the Link Registers (return address) at entry r1 + 4 !!!.
+ * So let room for it!!!.
+ */ 
+#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
+#define SRR0_FRAME_OFFSET 8
+#define SRR1_FRAME_OFFSET 12
+#define EXCEPTION_NUMBER_OFFSET 16
+#define GPR0_OFFSET 20
+#define GPR1_OFFSET 24
+#define GPR2_OFFSET 28
+#define GPR3_OFFSET 32
+#define GPR4_OFFSET 36
+#define GPR5_OFFSET 40
+#define GPR6_OFFSET 44
+#define GPR7_OFFSET 48
+#define GPR8_OFFSET 52
+#define GPR9_OFFSET 56
+#define GPR10_OFFSET 60
+#define GPR11_OFFSET 64
+#define GPR12_OFFSET 68
+#define GPR13_OFFSET 72
+#define GPR14_OFFSET 76
+#define GPR15_OFFSET 80
+#define GPR16_OFFSET 84
+#define GPR17_OFFSET 88
+#define GPR18_OFFSET 92
+#define GPR19_OFFSET 96
+#define GPR20_OFFSET 100
+#define GPR21_OFFSET 104
+#define GPR22_OFFSET 108
+#define GPR23_OFFSET 112
+#define GPR24_OFFSET 116
+#define GPR25_OFFSET 120
+#define GPR26_OFFSET 124
+#define GPR27_OFFSET 128
+#define GPR28_OFFSET 132
+#define GPR29_OFFSET 136
+#define GPR30_OFFSET 140
+#define GPR31_OFFSET 144
+#define EXC_CR_OFFSET 148
+#define EXC_CTR_OFFSET 152
+#define EXC_XER_OFFSET 156
+#define EXC_LR_OFFSET 160
+#define EXC_DAR_OFFSET 164
+/*
+ * maintain the EABI requested 8 bytes aligment
+ * As SVR4 ABI requires 16, make it 16 (as some
+ * exception may need more registers to be processed...)
+ */
+#define    EXCEPTION_FRAME_END 176
+
+#ifndef ASM
+/*
+ * default raw exception handlers
+ */
+
+extern	void default_exception_vector_code_prolog();
+extern	int  default_exception_vector_code_prolog_size;
+
+/* codemove is like memmove, but it also gets the cache line size
+ * as 4th parameter to synchronize them. If this last parameter is
+ * zero, it performs more or less like memmove. No copy is performed if
+ * source and destination addresses are equal. However the caches
+ * are synchronized. Note that the size is always rounded up to the
+ * next mutiple of 4. 
+ */
+extern void * codemove(void *, const void *, unsigned int, unsigned long);
+extern void initialize_exceptions();
+
+typedef struct {
+  unsigned 	EXC_SRR0;
+  unsigned 	EXC_SRR1;
+  unsigned	_EXC_number;
+  unsigned	GPR0;
+  unsigned	GPR1;
+  unsigned	GPR2;
+  unsigned	GPR3;
+  unsigned	GPR4;
+  unsigned	GPR5;
+  unsigned	GPR6;
+  unsigned	GPR7;
+  unsigned	GPR8;
+  unsigned	GPR9;
+  unsigned	GPR10;
+  unsigned	GPR11;
+  unsigned	GPR12;
+  unsigned	GPR13;
+  unsigned	GPR14;
+  unsigned	GPR15;
+  unsigned	GPR16;
+  unsigned	GPR17;
+  unsigned	GPR18;
+  unsigned	GPR19;
+  unsigned	GPR20;
+  unsigned	GPR21;
+  unsigned	GPR22;
+  unsigned	GPR23;
+  unsigned	GPR24;
+  unsigned	GPR25;
+  unsigned	GPR26;
+  unsigned	GPR27;
+  unsigned	GPR28;
+  unsigned	GPR29;
+  unsigned	GPR30;
+  unsigned	GPR31;
+  unsigned 	EXC_CR;
+  unsigned 	EXC_CTR;
+  unsigned 	EXC_XER;
+  unsigned	EXC_LR;
+  unsigned 	EXC_MSR;
+  unsigned	EXC_DAR;
+} exception_frame;
+
+extern void C_exception_handler(exception_frame* excPtr);
+
+#endif /* ASM */
+
+#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */
@@ -0,0 +1,100 @@
+/*
+ *
+ */
+#include <bsp/vectors.h>
+#include <libcpu/raw_exception.h>
+
+static rtems_raw_except_global_settings exception_config;
+static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
+
+void C_exception_handler(exception_frame* excPtr)
+{
+  int recoverable = 0;
+  
+  printk("exception handler called for exception %d\n", excPtr->_EXC_number);
+  printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0);
+  printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1);
+  printk("\t R0 = %x\n", excPtr->GPR0);
+  printk("\t R1 = %x\n", excPtr->GPR1);
+  printk("\t R2 = %x\n", excPtr->GPR2);
+  printk("\t R3 = %x\n", excPtr->GPR3);
+  printk("\t R4 = %x\n", excPtr->GPR4);
+  printk("\t R5 = %x\n", excPtr->GPR5);
+  printk("\t R6 = %x\n", excPtr->GPR6);
+  printk("\t R7 = %x\n", excPtr->GPR7);
+  printk("\t R8 = %x\n", excPtr->GPR8);
+  printk("\t R9 = %x\n", excPtr->GPR9);
+  printk("\t R10 = %x\n", excPtr->GPR10);
+  printk("\t R11 = %x\n", excPtr->GPR11);
+  printk("\t R12 = %x\n", excPtr->GPR12);
+  printk("\t R13 = %x\n", excPtr->GPR13);
+  printk("\t R14 = %x\n", excPtr->GPR14);
+  printk("\t R15 = %x\n", excPtr->GPR15);
+  printk("\t R16 = %x\n", excPtr->GPR16);
+  printk("\t R17 = %x\n", excPtr->GPR17);
+  printk("\t R18 = %x\n", excPtr->GPR18);
+  printk("\t R19 = %x\n", excPtr->GPR19);
+  printk("\t R20 = %x\n", excPtr->GPR20);
+  printk("\t R21 = %x\n", excPtr->GPR21);
+  printk("\t R22 = %x\n", excPtr->GPR22);
+  printk("\t R23 = %x\n", excPtr->GPR23);
+  printk("\t R24 = %x\n", excPtr->GPR24);
+  printk("\t R25 = %x\n", excPtr->GPR25);
+  printk("\t R26 = %x\n", excPtr->GPR26);
+  printk("\t R27 = %x\n", excPtr->GPR27);
+  printk("\t R28 = %x\n", excPtr->GPR28);
+  printk("\t R29 = %x\n", excPtr->GPR29);
+  printk("\t R30 = %x\n", excPtr->GPR30);
+  printk("\t R31 = %x\n", excPtr->GPR31);
+  printk("\t CR = %x\n", excPtr->EXC_CR);
+  printk("\t CTR = %x\n", excPtr->EXC_CTR);
+  printk("\t XER = %x\n", excPtr->EXC_XER);
+  printk("\t LR = %x\n", excPtr->EXC_LR);
+  printk("\t MSR = %x\n", excPtr->EXC_MSR);
+  if ( (excPtr->_EXC_number == ASM_DEC_VECTOR) ||
+       (excPtr->_EXC_number == ASM_SYS_VECTOR)
+     )
+       recoverable = 1;
+  if (!recoverable) BSP_panic("unrecoverable exception!!! Push reset button\n");
+}
+
+void nop_except_enable(const rtems_raw_except_connect_data* ptr)
+{
+}
+int except_always_enabled(const rtems_raw_except_connect_data* ptr)
+{
+  return 1;
+}
+
+void initialize_exceptions()
+{
+  int i;
+  
+  exception_config.exceptSize 		= LAST_VALID_EXC + 1;
+  exception_config.rawExceptHdlTbl 	= &exception_table[0];
+  exception_config.defaultRawEntry.exceptIndex	= 0;
+  exception_config.defaultRawEntry.hdl.vector	= 0;
+  exception_config.defaultRawEntry.hdl.raw_hdl	= default_exception_vector_code_prolog;
+  /*
+   * Note that next line the '&' before default_exception_vector_code_prolog_size
+   * is not a bug as it is defined a .set directly in asm...
+   */
+  exception_config.defaultRawEntry.hdl.raw_hdl_size = (unsigned) &default_exception_vector_code_prolog_size;
+  for (i=0; i <= exception_config.exceptSize; i++) {
+    if (!mpc750_vector_is_valid (i)) {
+      continue;
+    }
+    exception_table[i].exceptIndex	= i;
+    exception_table[i].hdl		= exception_config.defaultRawEntry.hdl;
+    exception_table[i].hdl.vector	= i;
+    exception_table[i].on		= nop_except_enable;
+    exception_table[i].off		= nop_except_enable;
+    exception_table[i].isOn		= except_always_enabled;
+  }
+  if (!mpc60x_init_exceptions(&exception_config)) {
+    BSP_panic("Exception handling initialization failed\n");
+  }
+  else {
+    printk("Exception handling initialization done\n");
+  }
+}
@@ -0,0 +1,59 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/lib/libbsp/powerpc/mpc750/wrapup
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+BSP_PIECES=console irq openpic pci residual startup vectors
+GENERIC_PIECES=
+
+# bummer; have to use $foreach since % pattern subst rules only replace 1x
+OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/*.o) \
+     $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/*.o)
+LIB=$(ARCH)/libbsp.a
+
+include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
+include $(RTEMS_ROOT)/make/lib.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+$(LIB): ${OBJS}
+	$(make-library)
+
+all:	${ARCH} $(SRCS) $(LIB)
+	$(INSTALL_VARIANT) -m 644 $(LIB) ${PROJECT_RELEASE}/lib
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
@@ -0,0 +1,20 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/directory.cfg
+
+SRCS=README
+
+all: $(SRCS)
+
+# wrapup is the one that actually builds and installs the library
+#  from the individual .rel files built in other directories
+SUB_DIRS= console include pci residual openpic irq vectors start startup bootloader wrapup
@@ -0,0 +1,48 @@
+#
+#  $Id$
+#
+
+BSP NAME:           MCP750
+BOARD:              MCP750 from motorola
+BUS:                PCI
+CPU FAMILY:         ppc
+CPU:                PowerPC 750
+COPROCESSORS:       N/A
+MODE:               32 bit mode
+
+DEBUG MONITOR:      PPCBUG mode 
+
+PERIPHERALS
+===========
+TIMERS:             PPC internal Timebase register
+  RESOLUTION:         ???
+SERIAL PORTS:       simulated via bug
+REAL-TIME CLOCK:    PPC internal Decrementer register
+DMA:                none
+VIDEO:              none
+SCSI:               none
+NETWORKING:         DEC21140
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER:       PPC internal
+IOSUPP DRIVER:      N/A
+SHMSUPP:            N/A
+TIMER DRIVER:       PPC internal
+TTY DRIVER:         PPC internal
+
+STDIO
+=====
+PORT:               Console port 0
+ELECTRICAL:         na
+BAUD:               na
+BITS PER CHARACTER: na
+PARITY:             na
+STOP BITS:          na
+
+Notes
+=====
+
+Based on papyrus bsp which only really supports
+the PowerOpen ABI with an ELF assembler.
+
@@ -0,0 +1,84 @@
+#
+#  $Id: 
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@:@srcdir@/../../../shared:@srcdir@/../console
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=misc pci zlib mm em86 polled_io
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=bootldr.h zlib.h pci.h
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=head exception em86real consoleLib
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) 
+OBJS=$(S_O_FILES) $(C_O_FILES) 
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CC_PIECES=
+CC_FILES=$(CC_PIECES:%=%.cc)
+CC_O_FILES=$(CC_PIECES:%=${ARCH}/%.o)
+
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += -D__BOOT__ -DDEBUG
+CFLAGS   += -msoft-float -mstrict-align -fno-builtin -Wall -mmultiple -mstring \
+		-O2 -fomit-frame-pointer -mrelocatable -ffixed-r13 \
+		-mno-sdata -D__BOOT__ -DDEBUG 
+
+ASFLAGS	 += -mrelocatable 
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+IMAGES := rtems.gz
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += bootloader
+CLOBBER_ADDITIONS += $(IMAGES)
+
+bootloader : ${OBJS} $(IMAGES) $(BINARY_LOADED) ppcboot.lds
+	$(LD) -o bootloader $(OBJS) --just-symbols=$(BINARY_LOADED) \
+	-b binary $(IMAGES) -T @srcdir@/ppcboot.lds \
+	 -Map bootloader.map
+
+rtems.gz: $(BINARY_LOADED)
+	$(OBJCOPY)  $(BINARY_LOADED) rtems -O binary -R .comment -S 
+	gzip -vf9 rtems
+	rm -f rtems
+
+
+all:	${ARCH} $(SRCS) ${OBJ}
+
+
+
+
+
+
+
+
+
+
@@ -0,0 +1,94 @@
+OUTPUT_ARCH(powerpc)
+OUTPUT_FORMAT(ppcboot)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .text :
+  {
+    /* We have to build the header by hand, painful since ppcboot
+	format support is very poor in binutils. 
+	objdump -b ppcboot zImage --all-headers can be used to check. */
+    /* The following line can be added as a branch to use the same image
+     * for netboot as for prepboots, the only problem is that objdump
+     * did not in this case recognize the format since it insisted
+     * in checking the x86 code area held only zeroes. 
+     */
+    LONG(0x48000000+start);
+    . = 0x1be; BYTE(0x80); BYTE(0)
+    BYTE(2); BYTE(0); BYTE(0x41); BYTE(1);
+    BYTE(0x12); BYTE(0x4f); LONG(0);
+    BYTE(((_edata + 0x1ff)>>9)&0xff); 
+    BYTE(((_edata + 0x1ff)>>17)&0xff); 
+    BYTE(((_edata + 0x1ff)>>25)&0xff);
+    . = 0x1fe;
+    BYTE(0x55);
+    BYTE(0xaa);
+    BYTE(start&0xff);
+    BYTE((start>>8)&0xff);
+    BYTE((start>>16)&0xff);
+    BYTE((start>>24)&0xff);
+    BYTE(_edata&0xff);
+    BYTE((_edata>>8)&0xff);
+    BYTE((_edata>>16)&0xff);
+    BYTE((_edata>>24)&0xff);
+    BYTE(0); /* flags */
+    BYTE(0); /* os_id */
+    BYTE(0x4C); BYTE(0x69); BYTE(0x6e); 
+    BYTE(0x75); BYTE(0x78); /* Partition name */
+    . = 0x400;
+    *(.text)
+    *(.sdata2)
+    *(.rodata)
+  }
+/*  . = ALIGN(16); */
+  .image :
+  {
+    rtems.gz(*)
+    . = ALIGN(4);
+    *.gz(*)
+  }
+  /* Read-write section, merged into data segment: */
+  /* . = ALIGN(4096); */
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .handlers : 
+  {
+    *(.exception)
+  }
+
+  .data    :
+  {
+    *(.data)
+    *(.sdata)
+    . = ALIGN(4);
+    _edata = .;
+  }
+  PROVIDE(_binary_initrd_gz_start = 0);
+  PROVIDE(_binary_initrd_gz_end = 0);
+  _rtems_gz_size = _binary_rtems_gz_end - _binary_rtems_gz_start;
+  _rtems_size = __rtems_end - __rtems_start;
+  .bss :
+  {
+    *(.sbss)
+    *(.bss)
+    . = ALIGN(4);
+  }
+  __bss_words = SIZEOF(.bss)>>2;
+  __size = . ;
+  /DISCARD/ : 
+  {
+    *(.comment)
+  }
+}
+