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bsp/beagle: Partial re-write of I2C driver.
The old driver worked well for EEPROMS with the RTEMS EEPROM driver. But it had problems with a lot of other situations. Although it's not a direct port, the new driver is heavily modeled after the FreeBSD ti_i2c driver. Closes #3764.
This commit is contained in:
Christian Mauderer
committed by
Christian Mauderer
Christian Mauderer
parent
5803f3738f
commit
b89d6cc5e4
+395
-353
File diff suppressed because it is too large
Load Diff
@@ -24,76 +24,15 @@
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#define LIBBSP_ARM_BEAGLE_I2C_H
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#include <rtems.h>
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#include <dev/i2c/i2c.h>
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#include <bsp.h>
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#include <dev/i2c/i2c.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* I2C Configuration Register (I2C_CON): */
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#define BBB_I2C_CON_EN (1 << 15) /* I2C module enable */
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#define BBB_I2C_CON_BE (1 << 14) /* Big endian mode */
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#define BBB_I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
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#define BBB_I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define BBB_I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
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/* (master mode only) */
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#define BBB_I2C_CON_XA (1 << 8) /* Expand address */
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#define BBB_I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
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#define BBB_I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
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#define BBB_I2C_CON_CLR 0x0 /* Clear configuration register */
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/* I2C Status Register (I2C_STAT): */
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#define BBB_I2C_STAT_SBD (1 << 15) /* Single byte data */
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#define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */
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#define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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#define BBB_I2C_STAT_AAS (1 << 9) /* Address as slave */
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#define BBB_I2C_STAT_GC (1 << 5)
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#define BBB_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
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#define BBB_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
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#define BBB_I2C_STAT_ARDY (1 << 2) /* Register access ready */
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#define BBB_I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
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#define BBB_I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
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/* I2C Interrupt Enable Register (I2C_IE): */
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#define BBB_I2C_IE_GC_IE (1 << 5)
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#define BBB_I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
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#define BBB_I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
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#define BBB_I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
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#define BBB_I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
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#define BBB_I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
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/* I2C SYSC Register (I2C_SYSC): */
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#define BBB_I2C_SYSC_SRST (1 << 1)
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#define BBB_I2C_TIMEOUT 1000
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#define BBB_I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */
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#define BBB_CONFIG_SYS_I2C_SPEED 100000
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#define BBB_CONFIG_SYS_I2C_SLAVE 1
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#define BBB_I2C_ALL_FLAGS 0x7FFF
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#define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF
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#define BBB_I2C_SYSCLK 48000000
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#define BBB_I2C_INTERNAL_CLK 12000000
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#define BBB_I2C_SPEED_CLK 100000
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#define BBB_I2C_IRQ_ERROR \
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( AM335X_I2C_IRQSTATUS_NACK \
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| AM335X_I2C_IRQSTATUS_ROVR \
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| AM335X_I2C_IRQSTATUS_AL \
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| AM335X_I2C_IRQSTATUS_ARDY \
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| AM335X_I2C_IRQSTATUS_RRDY \
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| AM335X_I2C_IRQSTATUS_XRDY \
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| AM335X_I2C_IRQSTATUS_XUDF )
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#define BBB_I2C_IRQ_USED \
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( AM335X_I2C_IRQSTATUS_ARDY \
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| AM335X_I2C_IRQSTATUS_XRDY )
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#define BBB_I2C_0_BUS_PATH "/dev/i2c-0"
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#define BBB_I2C_1_BUS_PATH "/dev/i2c-1"
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@@ -103,9 +42,6 @@ extern "C" {
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#define BBB_I2C1_IRQ 71
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#define BBB_I2C2_IRQ 30
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#define BBB_MODE2 2
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#define BBB_MODE3 3
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typedef enum {
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I2C0,
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I2C1,
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@@ -151,26 +87,10 @@ typedef struct i2c_regs {
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uint32_t BBB_I2C_SBLOCK;
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} bbb_i2c_regs;
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typedef struct bbb_i2c_bus {
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i2c_bus base;
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volatile bbb_i2c_regs *regs;
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i2c_msg *msgs;
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uint32_t msg_todo;
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uint32_t current_msg_todo;
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uint8_t *current_msg_byte;
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uint32_t current_todo;
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bool read;
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bool hold;
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rtems_id task_id;
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rtems_vector_number irq;
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uint32_t input_clock;
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uint32_t already_transferred;
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} bbb_i2c_bus;
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int am335x_i2c_bus_register(
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const char *bus_path,
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uintptr_t register_base,
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uint32_t input_clock,
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uint32_t input_clock, /* FIXME: Unused. Left for compatibility. */
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rtems_vector_number irq
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);
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@@ -664,6 +664,9 @@
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#define AM335X_I2C_CON_MST (0x00000400u)
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#define AM335X_I2C_CON_STB (0x00000800u)
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#define AM335X_I2C_SYSC_AUTOIDLE (0x00000001u)
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#define AM335X_I2C_SYSC_SRST (0x00000002u)
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#define AM335X_I2C_SYSC_ENAWAKEUP (0x00000004u)
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#define AM335X_I2C_SYSS_RDONE (0x00000001u)
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/*I2C0 module clock registers*/
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#define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4)
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@@ -686,29 +689,39 @@
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#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST (0x00030000u)
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#define AM335X_I2C_BUF_TXTRSH_SHIFT (0)
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#define AM335X_I2C_BUF_TXTRSH_MASK (0x0000003Fu)
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#define AM335X_I2C_BUF_TXTRSH(X) (((X) << AM335X_I2C_BUF_TXTRSH_SHIFT) \
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& AM335X_I2C_BUF_TXTRSH_MASK)
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#define AM335X_I2C_BUF_TXFIFO_CLR (0x00000040u)
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#define AM335X_I2C_BUF_RXTRSH_SHIFT (8)
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#define AM335X_I2C_BUF_RXTRSH_MASK (0x00003F00u)
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#define AM335X_I2C_BUF_RXTRSH(X) (((X) << AM335X_I2C_BUF_RXTRSH_SHIFT) \
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& AM335X_I2C_BUF_RXTRSH_MASK)
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#define AM335X_I2C_BUF_RXFIFO_CLR (0x00004000u)
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/* I2C status Register */
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#define AM335X_I2C_IRQSTATUS_AL (1 << 0)
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#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
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#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
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#define AM335X_I2C_IRQSTATUS_AL (1<<0)
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#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
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#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
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#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
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#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
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#define AM335X_I2C_BUF_TXFIFO_CLR (0x00000040u)
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#define AM335X_I2C_BUF_RXFIFO_CLR (0x00004000u)
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#define AM335X_I2C_IRQSTATUS_AAS (1 << 9)
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#define AM335X_I2C_IRQSTATUS_BF (1 << 8)
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#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
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#define AM335X_I2C_IRQSTATUS_STC (1 << 6)
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#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
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#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
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#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
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#define AM335X_I2C_IRQSTATUS_AERR (1 << 7)
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#define AM335X_I2C_IRQSTATUS_BF (1 << 8)
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#define AM335X_I2C_IRQSTATUS_AAS (1 << 9)
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#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
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#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
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#define AM335X_I2C_IRQSTATUS_BB (1 << 12)
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#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
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#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
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#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
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#define AM335X_I2C_CON_STOP (0x00000002u)
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#define AM335X_I2C_CON_START (0x00000001u)
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#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
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#define AM335X_I2C_CFG_MST_TX (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
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#define AM335X_I2C_IRQSTATUS_RAW_BB (0x00001000u)
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#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
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#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
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