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encoding: Fix encoding for 3 files

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board_memories: WINDOWS-1250
aes.c: ISO-8859-3
sdramc.c: WINDOWS-1250

These have been converted to utf-8 with the broken characters fixed.  The
original encoding is wrong and has been corrupted.  Now they are ASCII.
This commit is contained in:
Amar Takhar
2025-05-21 20:06:29 -04:00
parent 70ad0926b0
commit b2b8b2604a
3 changed files with 6 additions and 6 deletions
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bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
+4 -4
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@@ -196,7 +196,7 @@ void BOARD_ConfigureSdram(void)
SDRAMC->SDRAMC_MDR = BOARD_Sdram_Config.sdramc_mdr;
#endif /* __rtems__ */
/* 4. A minimum pause of 200 ¦Ìs is provided to precede any signal toggle.*/
/* 4. A minimum pause of 200 us is provided to precede any signal toggle.*/
for (i = 0; i < 100000; i++);
/* 5. (1)A NOP command is issued to the SDRAM devices. The application must
@@ -277,10 +277,10 @@ void BOARD_ConfigureSdram(void)
/* 11. Write the refresh rate into the count field in the SDRAMC Refresh
Timer register. (Refresh rate = delay between refresh cycles).
The SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs.
The SDRAM device requires a refresh every 15.625 us or 7.81 us.
With a 100 MHz frequency, the Refresh Timer Counter Register must be set
with the value 1562(15.625 ¦Ìs x 100 MHz) or 781(7.81 ¦Ìs x 100 MHz). */
// For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ¦Ìs
with the value 1562(15.625 us x 100 MHz) or 781(7.81 us x 100 MHz). */
// For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 us
/* ((32 x 10(^-3))/2048) x150 x (10^6) */
#ifndef __rtems__
SDRAMC->SDRAMC_TR = 1562;
bsps/arm/atsam/contrib/libraries/libchip/source/aes.c
+1 -1
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@@ -249,7 +249,7 @@ void AES_SetGcmHash(uint32_t *hash)
/**
* \brief Get The four 32-bit Tag which contain the final 128-bit GCM
* Authentication tag ¡°T¡± when GCM processing is complete.
* Authentication tag T when GCM processing is complete.
* \param tag point to the word of the tag.
*/
void AES_GetGcmTag(uint32_t *tag)
bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c
+1 -1
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@@ -128,7 +128,7 @@ extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
/* Step 4 */
/* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle.
/* A minimum pause of 200 us is provided to precede any signal toggle.
(6 core cycles per iteration) */
for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);