mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-11-09 08:37:58 +08:00
2005-06-01 Philippe Simons <loki_666@fastmail.fm>
* Makefile.am: Add s3c2400/lcd/lcd.c, s3c2400/clock/support.c * s3c2400/clock/clockdrv.c: Update to use get_PCLK() * s3c2400/timer/timer.c: Update to use get_PCLK()
This commit is contained in:
Joel Sherrill committed
1 parent
32cf23b18e
commit
b2a4e861dc
7 files changed
+410
-27
No files matched your search
@@ -1,3 +1,9 @@
|
||||
2005-06-01 Philippe Simons <loki_666@fastmail.fm>
|
||||
|
||||
* Makefile.am: Add s3c2400/lcd/lcd.c, s3c2400/clock/support.c
|
||||
* s3c2400/clock/clockdrv.c: Update to use get_PCLK()
|
||||
* s3c2400/timer/timer.c: Update to use get_PCLK()
|
||||
|
||||
2005-05-17 Jennifer Averett <jennifer.averett@oarcorp.com>
|
||||
|
||||
* at91rm9200/irq/irq.h, mc9328mxl/irq/irq.h, s3c2400/irq/irq.h:
|
||||
|
||||
@@ -96,7 +96,7 @@ include_HEADERS = s3c2400/include/s3c2400.h
|
||||
|
||||
## s3c2400/clock
|
||||
noinst_PROGRAMS += s3c2400/clock.rel
|
||||
s3c2400_clock_rel_SOURCES = s3c2400/clock/clockdrv.c
|
||||
s3c2400_clock_rel_SOURCES = s3c2400/clock/clockdrv.c s3c2400/clock/support.c
|
||||
s3c2400_clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
s3c2400_clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
@@ -106,6 +106,12 @@ s3c2400_timer_rel_SOURCES = s3c2400/timer/timer.c
|
||||
s3c2400_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
s3c2400_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
## s3c2400/lcd
|
||||
noinst_PROGRAMS += s3c2400/lcd.rel
|
||||
s3c2400_lcd_rel_SOURCES = s3c2400/lcd/lcd.c
|
||||
s3c2400_lcd_rel_CPPFLAGS = $(AM_CPPLAGS)
|
||||
s3c2400_lcd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
## s3c2400/interrupt
|
||||
include_HEADERS += s3c2400/irq/irq.h
|
||||
|
||||
|
||||
@@ -77,13 +77,7 @@ rtems_irq_connect_data clock_isr_data = {BSP_INT_TIMER4,
|
||||
/* set MUX for Timer4 to 1/16 */ \
|
||||
cr=rTCFG1 & 0xFFF0FFFF; \
|
||||
rTCFG1=(cr | (3<<16)); \
|
||||
/* compute MPLL freq */ \
|
||||
m = M_MDIV + 8; \
|
||||
p = M_PDIV + 2; \
|
||||
s = M_SDIV; \
|
||||
freq =(BSP_OSC_FREQ * m) / (p << s); \
|
||||
/* PCLK = MPLL/4 */ \
|
||||
freq = freq / 4; \
|
||||
freq = get_PCLK(); \
|
||||
/* set TIMER4 counter, input freq=PLCK/16/16Mhz*/ \
|
||||
freq = (freq /16)/16; \
|
||||
rTCNTB4 = ((freq / 1000) * BSP_Configuration.microseconds_per_tick) / 1000; \
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
#include <s3c2400.h>
|
||||
|
||||
#define MPLL 0
|
||||
#define UPLL 1
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* NOTE: This describes the proper use of this file.
|
||||
*
|
||||
* BSP_OSC_FREQ should be defined as the input frequency of the PLL.
|
||||
*
|
||||
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
|
||||
* the specified bus in HZ.
|
||||
*/
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static uint32_t get_PLLCLK(int pllreg)
|
||||
{
|
||||
uint32_t r, m, p, s;
|
||||
|
||||
if (pllreg == MPLL)
|
||||
r = rMPLLCON;
|
||||
else if (pllreg == UPLL)
|
||||
r = rUPLLCON;
|
||||
else
|
||||
return 0;
|
||||
|
||||
m = ((r & 0xFF000) >> 12) + 8;
|
||||
p = ((r & 0x003F0) >> 4) + 2;
|
||||
s = r & 0x3;
|
||||
|
||||
return((BSP_OSC_FREQ * m) / (p << s));
|
||||
}
|
||||
|
||||
/* return FCLK frequency */
|
||||
uint32_t get_FCLK(void)
|
||||
{
|
||||
return(get_PLLCLK(MPLL));
|
||||
}
|
||||
|
||||
/* return HCLK frequency */
|
||||
uint32_t get_HCLK(void)
|
||||
{
|
||||
return((rCLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
|
||||
}
|
||||
|
||||
/* return PCLK frequency */
|
||||
uint32_t get_PCLK(void)
|
||||
{
|
||||
return((rCLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
|
||||
}
|
||||
|
||||
/* return UCLK frequency */
|
||||
uint32_t get_UCLK(void)
|
||||
{
|
||||
return(get_PLLCLK(UPLL));
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,156 @@
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
#include <s3c2400.h>
|
||||
|
||||
void gp32_setFramebuffer(void *add) {
|
||||
uint32_t addr = (uint32_t) add;
|
||||
uint32_t LCDBANK = addr >> 22;
|
||||
uint32_t LCDBASEU = (addr & 0x3FFFFF) >> 1;
|
||||
uint32_t LCDBASEL;
|
||||
uint16_t OFFSIZE = 0;
|
||||
uint16_t PAGEWIDTH;
|
||||
uint16_t vidmode = ((rLCDCON1>>1) & 15)-8;
|
||||
const uint8_t faktor[]= {15,30,60,120,240};
|
||||
|
||||
LCDBASEL = LCDBASEU + 320*faktor[vidmode];
|
||||
PAGEWIDTH = faktor[vidmode];
|
||||
|
||||
rLCDSADDR1 = (LCDBANK<<21) | (LCDBASEU<<0) ;
|
||||
rLCDSADDR2 = (LCDBASEL<<0) ;
|
||||
rLCDSADDR3 = (OFFSIZE<<11) | (PAGEWIDTH<<0) ;
|
||||
}
|
||||
|
||||
short gp32_initFramebufferN(void *add,uint32_t bitmode,uint32_t refreshrate) {
|
||||
uint32_t addr = (uint32_t) add;
|
||||
uint32_t GPHCLK = get_HCLK();
|
||||
{ uint16_t BPPMODE = 12;
|
||||
uint16_t CLKVAL = 3;
|
||||
uint16_t ENVID = 1;
|
||||
uint16_t MMODE = 0;
|
||||
uint16_t PNRMODE = 3;
|
||||
switch (bitmode) {
|
||||
case 16 : BPPMODE=12; break;
|
||||
case 8 : BPPMODE=11; break;
|
||||
case 4 : BPPMODE=10; break;
|
||||
case 2 : BPPMODE= 9; break;
|
||||
case 1 : BPPMODE= 8; break;
|
||||
default : BPPMODE= 12; break;
|
||||
}
|
||||
/* Get the correct CLKVAL for refreshrate
|
||||
works in all bitmodes now :)
|
||||
*/
|
||||
if (refreshrate < 50) refreshrate = 50;
|
||||
if (refreshrate > 120) refreshrate =120;
|
||||
CLKVAL = (GPHCLK/(83385*2*refreshrate))-1;
|
||||
if (CLKVAL == 0) CLKVAL=1;
|
||||
refreshrate = GPHCLK / (83385*2*(CLKVAL+1));
|
||||
rLCDCON1 = (CLKVAL<<8) | (MMODE<<7) | (PNRMODE<<5) | (BPPMODE<<1) | (ENVID<<0) ;
|
||||
}
|
||||
{ uint16_t LINEVAL = 320-1;
|
||||
uint16_t VBPD = 1;
|
||||
uint16_t VFPD = 2;
|
||||
uint16_t VSPW = 1;
|
||||
rLCDCON2 = 0;
|
||||
rLCDCON2 = (VBPD<<24) | (LINEVAL<<14) | (VFPD<<6) | (VSPW<<0) ;
|
||||
}
|
||||
{ uint16_t HBPD = 6;
|
||||
uint16_t HFPD = 2;
|
||||
uint16_t HOZVAL = 240-1;
|
||||
rLCDCON3 = 0;
|
||||
rLCDCON3 = (HBPD<<19) | (HOZVAL<<8) | (HFPD<<0) ;
|
||||
}
|
||||
{ uint16_t ADDVAL = 0;
|
||||
uint16_t HSPW = 4;
|
||||
uint16_t MVAL = 0;
|
||||
uint16_t PALADDEN = 0;
|
||||
rLCDCON4 = 0;
|
||||
rLCDCON4 = (PALADDEN<<24) | (ADDVAL<<16) | (MVAL<<8) | (HSPW<<0) ;
|
||||
}
|
||||
{ uint16_t BSWP = 0;
|
||||
uint16_t ENLEND = 0;
|
||||
uint16_t HWSWP = 1;
|
||||
uint16_t INVENDLINE = 0;
|
||||
uint16_t INVVCLK = 1;
|
||||
uint16_t INVVD = 0;
|
||||
uint16_t INVVDEN = 0;
|
||||
uint16_t INVVFRAME = 1;
|
||||
uint16_t INVVLINE = 1;
|
||||
if (bitmode<16) { BSWP=1;HWSWP=0; }
|
||||
rLCDCON5 = 0;
|
||||
rLCDCON5 = (INVVCLK<<10) | (INVVLINE<<9) | (INVVFRAME<<8) | (INVVD<<7) | (INVVDEN<<6)
|
||||
| (INVENDLINE<<4) | (ENLEND<<2) | (BSWP<<1) | (HWSWP<<0) ;
|
||||
}
|
||||
gp32_setFramebuffer((uint32_t*)addr);
|
||||
|
||||
return refreshrate;
|
||||
}
|
||||
|
||||
short gp32_initFramebufferBP(void *add,uint32_t bitmode,uint32_t refreshrate) {
|
||||
uint32_t addr = (uint32_t) add;
|
||||
uint32_t GPHCLK = get_HCLK();
|
||||
{ uint16_t BPPMODE = 12;
|
||||
uint16_t CLKVAL = 3;
|
||||
uint16_t ENVID = 1;
|
||||
uint16_t MMODE = 0;
|
||||
uint16_t PNRMODE = 3;
|
||||
switch (bitmode) {
|
||||
case 16 : BPPMODE=12; break;
|
||||
case 8 : BPPMODE=11; break;
|
||||
case 4 : BPPMODE=10; break;
|
||||
case 2 : BPPMODE= 9; break;
|
||||
case 1 : BPPMODE= 8; break;
|
||||
}
|
||||
/* Get the correct CLKVAL for refreshrate
|
||||
works in all bitmodes now :)
|
||||
*/
|
||||
if (refreshrate < 50) refreshrate = 50;
|
||||
if (refreshrate > 120) refreshrate =120;
|
||||
CLKVAL = (GPHCLK/(109850*2*refreshrate))-1;
|
||||
if (CLKVAL == 0) CLKVAL=1;
|
||||
refreshrate = GPHCLK / (109850*2*(CLKVAL+1));
|
||||
rLCDCON1 = (CLKVAL<<8) | (MMODE<<7) | (PNRMODE<<5) | (BPPMODE<<1) | (ENVID<<0);
|
||||
}
|
||||
{ uint16_t LINEVAL = 320-1;
|
||||
uint16_t VBPD = 8;
|
||||
uint16_t VFPD = 2;
|
||||
uint16_t VSPW = 5;
|
||||
rLCDCON2 = 0;
|
||||
rLCDCON2 = (VBPD<<24) | (LINEVAL<<14) | (VFPD<<6) | (VSPW<<0);
|
||||
}
|
||||
{ uint16_t HBPD = 50;
|
||||
uint16_t HFPD = 2;
|
||||
uint16_t HOZVAL = 240-1;
|
||||
rLCDCON3 = 0;
|
||||
rLCDCON3 = (HBPD<<19) | (HOZVAL<<8) | (HFPD<<0);
|
||||
}
|
||||
{ uint16_t ADDVAL = 0;
|
||||
uint16_t HSPW = 30;
|
||||
uint16_t MVAL = 0;
|
||||
uint16_t PALADDEN = 0;
|
||||
rLCDCON4 = 0;
|
||||
rLCDCON4 = (PALADDEN<<24) | (ADDVAL<<16) | (MVAL<<8) | (HSPW<<0);
|
||||
}
|
||||
{ uint16_t BSWP = 0;
|
||||
uint16_t ENLEND = 0;
|
||||
uint16_t HWSWP = 1;
|
||||
uint16_t INVENDLINE = 0;
|
||||
uint16_t INVVCLK = 1;
|
||||
uint16_t INVVD = 0;
|
||||
uint16_t INVVDEN = 0;
|
||||
uint16_t INVVFRAME = 1;
|
||||
uint16_t INVVLINE = 1;
|
||||
if (bitmode<16) { BSWP=1;HWSWP=0; }
|
||||
rLCDCON5 = 0;
|
||||
rLCDCON5 = (INVVCLK<<10) | (INVVLINE<<9) | (INVVFRAME<<8) | (INVVD<<7) | (INVVDEN<<6)
|
||||
| (INVENDLINE<<4) | (ENLEND<<2) | (BSWP<<1) | (HWSWP<<0);
|
||||
}
|
||||
gp32_setFramebuffer((uint32_t*)addr);
|
||||
|
||||
return refreshrate;
|
||||
}
|
||||
|
||||
void gp32_setPalette( unsigned char pos, uint16_t color) {
|
||||
unsigned long *palette=(unsigned long *)0x14A00400;
|
||||
while ((rLCDCON5>>19) == 2);
|
||||
palette[pos]=color;
|
||||
}
|
||||
@@ -36,9 +36,6 @@ rtems_boolean Timer_driver_Find_average_overhead;
|
||||
void Timer_initialize( void )
|
||||
{
|
||||
uint32_t cr;
|
||||
uint32_t m;
|
||||
uint32_t p;
|
||||
uint32_t s;
|
||||
|
||||
/* stop TIMER1*/
|
||||
cr=rTCON & 0xFFFFF0FF;
|
||||
@@ -48,17 +45,8 @@ void Timer_initialize( void )
|
||||
cr=rTCFG1 & 0xFFFFFF0F;
|
||||
rTCFG1=(cr | (0<<4));
|
||||
|
||||
/* compute MPLL freq */
|
||||
m = M_MDIV + 8;
|
||||
p = M_PDIV + 2;
|
||||
s = M_SDIV;
|
||||
g_freq =(BSP_OSC_FREQ * m) / (p << s);
|
||||
|
||||
/* PCLK = MPLL/4 */
|
||||
g_freq = g_freq / 4;
|
||||
|
||||
/* input freq=PLCK/2 Mhz*/
|
||||
g_freq = g_freq / 2000;
|
||||
g_freq = get_PCLK() / 2000;
|
||||
rTCNTB1 = 0xFFFF;
|
||||
|
||||
/* start TIMER1 with manual reload */
|
||||
|
||||
Reference in new issue
Block a user