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This commit is contained in:
Ralf Corsepius
2009-11-30 04:37:44 +00:00
parent 9eac014ad3
commit ac7af4a359
171 changed files with 1883 additions and 1883 deletions
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c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c
+4 -4
View File
@@ -25,15 +25,15 @@
#include <rtems/bspIo.h>
#define DEBUG_PRINT 1
#define DEBUG_PRINT 1
void M360SetupMemory( M68360_t ptr ){
volatile m360_t *m360;
m360 = ptr->m360;
#if DEBUG_PRINT
printk("m360->mcr:0x%08x Q1_360_SIM_MCR:0x%08x\n",
printk("m360->mcr:0x%08x Q1_360_SIM_MCR:0x%08x\n",
(unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));
#endif
ptr->bdregions[0].base = (char *)&m360->dpram1[0];
@@ -93,7 +93,7 @@ M360AllocateBufferDescriptors (M68360_t ptr, int count)
continue;
}
*cp = 0x0;
}
}
have = ptr->bdregions[i].size - ptr->bdregions[i].used;
if (have >= want) {
c/src/lib/libbsp/powerpc/ep1a/console/config.c
+12 -12
View File
@@ -1,6 +1,6 @@
/*
* This file contains the TTY driver table for the EP1A
*
*
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
@@ -386,47 +386,47 @@ static bool config_68360_scc_base_probe(int minor, unsigned long busNo, unsigned
static bool config_68360_scc_base_probe_1( int minor ) {
return config_68360_scc_base_probe(minor, 0, 11, 1);
}
static bool config_68360_scc_base_probe_2( int minor ) {
return config_68360_scc_base_probe(minor, 0, 11, 2);
}
static bool config_68360_scc_base_probe_3( int minor ) {
return config_68360_scc_base_probe( minor, 0, 11, 3);
}
static bool config_68360_scc_base_probe_4( int minor ) {
return config_68360_scc_base_probe( minor, 0, 11, 4);
}
static bool config_68360_scc_base_probe_5( int minor ) {
return config_68360_scc_base_probe( minor, 0, 16, 1);
}
static bool config_68360_scc_base_probe_6( int minor ) {
return config_68360_scc_base_probe( minor, 0, 16, 2);
}
static bool config_68360_scc_base_probe_7( int minor ) {
return config_68360_scc_base_probe( minor, 0, 16, 3);
}
static bool config_68360_scc_base_probe_8( int minor ) {
return config_68360_scc_base_probe( minor, 0, 16, 4);
}
static bool config_68360_scc_base_probe_9( int minor ) {
return config_68360_scc_base_probe( minor, 0, 15, 1);
}
static bool config_68360_scc_base_probe_10( int minor ) {
return config_68360_scc_base_probe( minor, 0, 15, 2);
}
static bool config_68360_scc_base_probe_11( int minor ) {
return config_68360_scc_base_probe( minor, 0, 15, 3);
}
static bool config_68360_scc_base_probe_12( int minor ) {
return config_68360_scc_base_probe( minor, 0, 15, 4);
}
c/src/lib/libbsp/powerpc/ep1a/console/console.c
+9 -9
View File
@@ -1,5 +1,5 @@
/*
* This file contains the TTY driver for the ep1a
* This file contains the TTY driver for the ep1a
*
* This driver uses the termios pseudo driver.
*
@@ -32,7 +32,7 @@
console_data Console_Port_Data[NUM_CONSOLE_PORTS];
unsigned long Console_Port_Count;
rtems_device_minor_number Console_Port_Minor;
/* PAGE
*
* console_open
@@ -70,9 +70,9 @@ rtems_device_driver console_open(
Callbacks.pollRead = c->deviceRead;
Callbacks.write = c->deviceWrite;
Callbacks.setAttributes = c->deviceSetAttributes;
Callbacks.stopRemoteTx =
Callbacks.stopRemoteTx =
Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx;
Callbacks.startRemoteTx =
Callbacks.startRemoteTx =
Console_Port_Tbl[minor].pDeviceFlow->deviceStartRemoteTx;
Callbacks.outputUsesInterrupts = c->deviceOutputUsesInterrupts;
status = rtems_termios_open ( major, minor, arg, &Callbacks);
@@ -102,7 +102,7 @@ rtems_device_driver console_open(
return status;
}
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -120,7 +120,7 @@ rtems_device_driver console_close(
return rtems_termios_close (arg);
}
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -129,7 +129,7 @@ rtems_device_driver console_read(
{
return rtems_termios_read (arg);
}
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -138,7 +138,7 @@ rtems_device_driver console_write(
{
return rtems_termios_write (arg);
}
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -194,7 +194,7 @@ rtems_device_driver console_initialize(
*/
rtems_fatal_error_occurred(RTEMS_IO_ERROR);
}
Console_Port_Minor=minor;
/*
c/src/lib/libbsp/powerpc/ep1a/console/m68360.h
+22 -22
View File
@@ -1,20 +1,20 @@
/*
* MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
*
* HARDWARE DECLARATIONS
*
*
* Submitted By:
*
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
* University of Saskatchewan
* 107 North Road
* Saskatoon, Saskatchewan, CANADA
* S7N 5C6
*
* eric@skatter.usask.ca
*
* MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)
*
* HARDWARE DECLARATIONS
*
*
* Submitted By:
*
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
* University of Saskatchewan
* 107 North Road
* Saskatoon, Saskatchewan, CANADA
* S7N 5C6
*
* eric@skatter.usask.ca
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
@@ -759,7 +759,7 @@ typedef struct m360_ {
volatile uint8_t _pad14[0xF0-0xD0];
volatile uint8_t _pad15[0x100-0xF0];
volatile uint8_t _pad16[0x500-0x100];
/*
* IDMA1 Block
*/
@@ -777,7 +777,7 @@ typedef struct m360_ {
volatile uint8_t csr1;
volatile uint8_t _pad21;
volatile uint16_t _pad22;
/*
* SDMA Block
*/
@@ -785,7 +785,7 @@ typedef struct m360_ {
volatile uint8_t _pad23;
volatile uint16_t sdcr;
volatile uint32_t sdar;
/*
* IDMA2 Block
*/
@@ -802,7 +802,7 @@ typedef struct m360_ {
volatile uint8_t _pad28;
volatile uint16_t _pad29;
volatile uint32_t _pad30;
/*
* CPIC Block
*/
@@ -826,7 +826,7 @@ typedef struct m360_ {
volatile uint16_t pcint;
volatile uint16_t _pad32;
volatile uint32_t _pad33[5];
/*
* TIMER Block
*/
@@ -854,7 +854,7 @@ typedef struct m360_ {
volatile uint16_t ter3;
volatile uint16_t ter4;
volatile uint32_t _pad36[2];
/*
* CP Block
*/
c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c
+24 -24
View File
@@ -148,10 +148,10 @@ void scc_write32(
void mc68360_sccShow_Regs(int minor){
M68360_serial_ports_t ptr;
ptr = Console_Port_Tbl[minor].pDeviceParams;
printk( "scce 0x%08x", &ptr->pSCCR->scce );
printk( " 0x%04x\n", ptr->pSCCR->scce );
}
#define TX_BUFFER_ADDRESS( _ptr ) \
@@ -212,11 +212,11 @@ mc68360_sccBRGC(int baud, int m360_clock_rate)
else data = (33333333 / (baud * 16 * 16) ) - 1;
data *= 2;
data &= 0x00001ffe ;
/* really data = 0x010000 | data | ((baud>300)? 0 : 1 ) ; */
data |= ((baud>300)? 0 : 1 ) ;
data |= 0x010000 ;
return data;
}
@@ -285,7 +285,7 @@ if (length > 1)
&data,
1);
}
scc_write16( "sccRxBd->status", &chip->port[port].sccRxBd->status,
scc_write16( "sccRxBd->status", &chip->port[port].sccRxBd->status,
M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT );
status =scc_read16( "sccRxBd->status", &chip->port[port].sccRxBd->status);
}
@@ -304,10 +304,10 @@ if (length > 1)
scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);
#if 1
rtems_termios_dequeue_characters(
Console_Port_Data[chip->port[port].minor].termios_data,
Console_Port_Data[chip->port[port].minor].termios_data,
chip->port[port].sccTxBd->length);
#else
mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5);
mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5);
#endif
}
}
@@ -378,7 +378,7 @@ uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
pbdat_data = 0x3;
for (i=0; i<4; i++) {
minor = chip->port[i].minor;
if mc68360_scc_Is_422( minor )
if mc68360_scc_Is_422( minor )
pbdat_data |= type422data[i];
}
@@ -408,7 +408,7 @@ void mc68360_scc_initialize_interrupts(int minor)
ptr = Console_Port_Tbl[minor].pDeviceParams;
m360 = ptr->chip->m360;
#ifdef DEBUG_360
printk("m360 0x%08x baseaddr 0x%08x\n",
m360, ptr->chip->board_data->baseaddr);
@@ -585,7 +585,7 @@ void mc68360_scc_initialize_interrupts(int minor)
scc_write16( "sccRxBd->status", &ptr->sccRxBd->status, 0x0000 );
SYNC();
scc_write16( "sccRxBd->length", &ptr->sccRxBd->length, 0x0000 );
scc_write16( "sccRxBd->status", &ptr->sccRxBd->status,
scc_write16( "sccRxBd->status", &ptr->sccRxBd->status,
M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT );
/* XXX Radstone Example writes RX buffer ptr as two u16's */
scc_write32( "sccRxBd->buffer", &ptr->sccRxBd->buffer,
@@ -612,14 +612,14 @@ void mc68360_scc_initialize_interrupts(int minor)
scc_write16( "pSCCR->sccm", &ptr->pSCCR->sccm, M360_SCCE_TX | M360_SCCE_RX );
data = scc_read32("cimr", &m360->cimr);
data = scc_read32("cimr", &m360->cimr);
data |= (0x80000000 >> ptr->channel);
scc_write32( "cimr", &m360->cimr, data );
SYNC();
scc_write32( "cipr", &m360->cipr, scc_read32( "cipr", &m360->cipr ) );
scc_write32( "pSCCR->gsmr_h", &ptr->pSCCR->gsmr_h, M360_GSMR_RFW );
scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,
scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,
(M360_GSMR_TDCR_16X | M360_GSMR_RDCR_16X | M360_GSMR_MODE_UART) );
scc_write16( "pSCCR->dsr", &ptr->pSCCR->dsr, 0x7e7e );
@@ -641,12 +641,12 @@ void mc68360_scc_initialize_interrupts(int minor)
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );
data &= (~PMCQ1_INT_MASK_QUICC);
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK, data );
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK, data );
data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS );
data &= (~PMCQ1_INT_STATUS_QUICC);
PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );
#endif
#endif
}
/*
@@ -696,10 +696,10 @@ int mc68360_scc_write_support_int(
scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0 );
memcpy((void *) ptr->txBuf, buf, len);
scc_write32( "sccTxBd->buffer", &ptr->sccTxBd->buffer,
scc_write32( "sccTxBd->buffer", &ptr->sccTxBd->buffer,
TX_BUFFER_ADDRESS(ptr->txBuf) );
scc_write16( "sccTxBd->length", &ptr->sccTxBd->length, len );
scc_write16( "sccTxBd->status", &ptr->sccTxBd->status,
scc_write16( "sccTxBd->status", &ptr->sccTxBd->status,
(M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT) );
rtems_interrupt_enable(Irql);
@@ -802,18 +802,18 @@ printk("mc68360_scc_set_attributes\n");
else
value |= M360_PSMR_SL_1; /* One stop bit */
/* Set Parity M360_PSMR_PEN bit should be clear on no parity so
* do nothing in that case
/* Set Parity M360_PSMR_PEN bit should be clear on no parity so
* do nothing in that case
*/
if (t->c_cflag & PARENB) /* enable parity detection? */
{
value |= M360_PSMR_PEN;
value |= M360_PSMR_PEN;
if (t->c_cflag & PARODD){
value |= M360_PSMR_RPM_ODD; /* select odd parity */
value |= M360_PSMR_TPM_ODD;
value |= M360_PSMR_TPM_ODD;
} else {
value |= M360_PSMR_RPM_EVEN; /* select even parity */
value |= M360_PSMR_TPM_EVEN;
value |= M360_PSMR_TPM_EVEN;
}
}
@@ -865,7 +865,7 @@ int mc68360_scc_write_support_polled(
int len
)
{
printk("mc68360_scc_write_support_polled: minor %d char %c len %d\n",
printk("mc68360_scc_write_support_polled: minor %d char %c len %d\n",
minor, buf, len );
return 0;
}
@@ -955,7 +955,7 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
chip->board_data->slotNo,
chip->board_data->funcNo,
&mc68360_sccInterruptHandler,
chip
chip
);
return RTEMS_SUCCESSFUL;
c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c
+3 -3
View File
@@ -1,4 +1,4 @@
/*
/*
* This include file contains all console driver definations for the nc16550
*
* COPYRIGHT (c) 1989-2008.
@@ -14,7 +14,7 @@
#include <rtems.h>
#include <bsp.h>
#include "console.h"
typedef struct uart_reg
{
unsigned char reg;
@@ -41,7 +41,7 @@ void Write_ns16550_register(
{
volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;
volatile int i;
p[ucRegNum].reg = ucData;
p[ucRegNum].reg = ucData;
asm volatile("sync");
asm volatile("isync");
asm volatile("eieio");
c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c
+71 -71
View File
@@ -206,34 +206,34 @@ unsigned int keymap_count = 7;
*/
char func_buf[] = {
'\033', '[', '[', 'A', 0,
'\033', '[', '[', 'B', 0,
'\033', '[', '[', 'C', 0,
'\033', '[', '[', 'D', 0,
'\033', '[', '[', 'E', 0,
'\033', '[', '1', '7', '~', 0,
'\033', '[', '1', '8', '~', 0,
'\033', '[', '1', '9', '~', 0,
'\033', '[', '2', '0', '~', 0,
'\033', '[', '2', '1', '~', 0,
'\033', '[', '2', '3', '~', 0,
'\033', '[', '2', '4', '~', 0,
'\033', '[', '2', '5', '~', 0,
'\033', '[', '2', '6', '~', 0,
'\033', '[', '2', '8', '~', 0,
'\033', '[', '2', '9', '~', 0,
'\033', '[', '3', '1', '~', 0,
'\033', '[', '3', '2', '~', 0,
'\033', '[', '3', '3', '~', 0,
'\033', '[', '3', '4', '~', 0,
'\033', '[', '1', '~', 0,
'\033', '[', '2', '~', 0,
'\033', '[', '3', '~', 0,
'\033', '[', '4', '~', 0,
'\033', '[', '5', '~', 0,
'\033', '[', '6', '~', 0,
'\033', '[', 'M', 0,
'\033', '[', 'P', 0,
'\033', '[', '[', 'A', 0,
'\033', '[', '[', 'B', 0,
'\033', '[', '[', 'C', 0,
'\033', '[', '[', 'D', 0,
'\033', '[', '[', 'E', 0,
'\033', '[', '1', '7', '~', 0,
'\033', '[', '1', '8', '~', 0,
'\033', '[', '1', '9', '~', 0,
'\033', '[', '2', '0', '~', 0,
'\033', '[', '2', '1', '~', 0,
'\033', '[', '2', '3', '~', 0,
'\033', '[', '2', '4', '~', 0,
'\033', '[', '2', '5', '~', 0,
'\033', '[', '2', '6', '~', 0,
'\033', '[', '2', '8', '~', 0,
'\033', '[', '2', '9', '~', 0,
'\033', '[', '3', '1', '~', 0,
'\033', '[', '3', '2', '~', 0,
'\033', '[', '3', '3', '~', 0,
'\033', '[', '3', '4', '~', 0,
'\033', '[', '1', '~', 0,
'\033', '[', '2', '~', 0,
'\033', '[', '3', '~', 0,
'\033', '[', '4', '~', 0,
'\033', '[', '5', '~', 0,
'\033', '[', '6', '~', 0,
'\033', '[', 'M', 0,
'\033', '[', 'P', 0,
};
char *funcbufptr = func_buf;
@@ -321,7 +321,7 @@ unsigned int accent_table_size = 68;
/* These #defines have been copied from drivers/char/pc_keyb.h, by
* Martin Mares (mj@ucw.cz).
* Martin Mares (mj@ucw.cz).
* converted to offsets by Till Straumann <strauman@slac.stanford.edu>
*/
#define KBD_STATUS_REG 0x4 /* Status register (R) */
@@ -386,7 +386,7 @@ SPR_RO(PVR)
#endif /* USE_KBD_SUPPORT */
/* Early messages after mm init but before console init are kept in log
/* Early messages after mm init but before console init are kept in log
* buffers.
*/
#define PAGE_LOG_CHARS (PAGE_SIZE-sizeof(int)-sizeof(u_long)-1)
@@ -511,7 +511,7 @@ static void pfree(void* p)
--global_index;
}
#endif
void log_putc(const u_char c) {
console_log *l;
@@ -521,11 +521,11 @@ void log_putc(const u_char c) {
if (!l) {
l=__palloc(sizeof(console_log));
memset(l, 0, sizeof(console_log));
if (!console_global_data.log)
if (!console_global_data.log)
console_global_data.log = l;
else {
console_log *p;
for (p=console_global_data.log;
for (p=console_global_data.log;
p->next; p=p->next);
p->next = l;
}
@@ -536,7 +536,7 @@ void log_putc(const u_char c) {
/* This puts is non standard since it does not automatically add a newline
* at the end. So it is made private to avoid confusion in other files.
*/
static
static
void puts(const u_char *s)
{
char c;
@@ -551,10 +551,10 @@ static
void flush_log(void) {
console_log *p, *next;
if (console_global_data.vacuum_sent) {
#ifdef TRACE_FLUSH_LOG
printk("%d characters sent into oblivion before MM init!\n",
#ifdef TRACE_FLUSH_LOG
printk("%d characters sent into oblivion before MM init!\n",
console_global_data.vacuum_sent);
#endif
#endif
}
for(p=console_global_data.log; p; p=next) {
puts(p->data);
@@ -572,7 +572,7 @@ void serial_putc(const u_char c)
while ((INL_CONSOLE_INB(lsr) & LSR_THRE) == 0) ;
INL_CONSOLE_OUTB(thr, c);
}
int serial_getc(void)
{
while ((INL_CONSOLE_INB(lsr) & LSR_DR) == 0) ;
@@ -589,16 +589,16 @@ static void scroll(void)
{
int i;
memcpy ( (u_char *)vidmem, (u_char *)vidmem + console_global_data.cols * 2,
memcpy ( (u_char *)vidmem, (u_char *)vidmem + console_global_data.cols * 2,
( console_global_data.lines - 1 ) * console_global_data.cols * 2 );
for ( i = ( console_global_data.lines - 1 ) * console_global_data.cols * 2;
i < console_global_data.lines * console_global_data.cols * 2;
for ( i = ( console_global_data.lines - 1 ) * console_global_data.cols * 2;
i < console_global_data.lines * console_global_data.cols * 2;
i += 2 )
vidmem[i] = ' ';
}
/*
* cursor() sets an offset (0-1999) into the 80x25 text area
* cursor() sets an offset (0-1999) into the 80x25 text area
*/
static void
cursor(int x, int y)
@@ -610,7 +610,7 @@ cursor(int x, int y)
vga_outb(0x15, pos);
}
void
void
vga_putc(const u_char c)
{
int x,y;
@@ -630,7 +630,7 @@ vga_putc(const u_char c)
} else if (c == '\r') {
x = 0;
} else {
vidmem [ ( x + console_global_data.cols * y ) * 2 ] = c;
vidmem [ ( x + console_global_data.cols * y ) * 2 ] = c;
if ( ++x >= console_global_data.cols ) {
x = 0;
if ( ++y >= console_global_data.lines ) {
@@ -767,7 +767,7 @@ static int kbd_get(int ms) {
else
return data;
}
if (--ms < 0) return -1;
if (--ms < 0) return -1;
#ifdef __BOOT__
boot_udelay(1000);
#else
@@ -778,7 +778,7 @@ static int kbd_get(int ms) {
static void kbd_put(u_char c, int ms, int port) {
while (kbd_inb(KBD_STATUS_REG) & KBD_STAT_IBF) {
if (--ms < 0) return;
if (--ms < 0) return;
#ifdef __BOOT__
boot_udelay(1000);
#else
@@ -802,14 +802,14 @@ int kbdreset(void)
/* Enable then reset the KB */
kbd_put(KBD_CCMD_KBD_ENABLE, 10, KBD_CNTL_REG);
while (1) {
kbd_put(KBD_CMD_RESET, 10, KBD_DATA_REG);
c = kbd_get(1000);
if (c == KBD_REPLY_ACK) break;
if (c != KBD_REPLY_RESEND) return 2;
}
if (kbd_get(1000) != KBD_REPLY_POR) return 3;
/* Disable the keyboard while setting up the controller */
@@ -818,7 +818,7 @@ int kbdreset(void)
/* Enable interrupts and keyboard controller */
kbd_put(KBD_CCMD_WRITE_MODE, 10, KBD_CNTL_REG);
kbd_put(KBD_MODE_KBD_INT | KBD_MODE_SYS |
kbd_put(KBD_MODE_KBD_INT | KBD_MODE_SYS |
KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC,
10, KBD_DATA_REG);
@@ -835,30 +835,30 @@ int kbd_tstc(void)
}
#endif /* USE_KBD_SUPPORT */
const struct console_io
const struct console_io
vacuum_console_functions = {
vacuum_putc,
vacuum_getc,
vacuum_putc,
vacuum_getc,
vacuum_tstc
};
static const struct console_io
log_console_functions = {
log_putc,
vacuum_getc,
log_putc,
vacuum_getc,
vacuum_tstc
}
,
serial_console_functions = {
serial_putc,
serial_getc,
serial_putc,
serial_getc,
serial_tstc
}
#if defined(USE_KBD_SUPPORT) && defined(USE_VGA_SUPPORT)
,
vga_console_functions = {
vga_putc,
kbd_getc,
vga_putc,
kbd_getc,
kbd_tstc
}
#endif
@@ -868,7 +868,7 @@ console_io* curIo = (console_io*) &vacuum_console_functions;
int select_console(ioType t) {
static ioType curType = CONSOLE_VACUUM;
switch (t) {
case CONSOLE_VACUUM : curIo = (console_io*)&vacuum_console_functions; break;
case CONSOLE_LOG : curIo = (console_io*)&log_console_functions; break;
@@ -911,7 +911,7 @@ int printk(const char *fmt, ...) {
int i;
/* Should not be a problem with 8kB of stack */
char buf[1024];
va_start(args, fmt);
i = k_vsprintf(buf, fmt, args);
va_end(args);
@@ -949,7 +949,7 @@ do { u32 t1, t2, t3; \
"=r" (num), "=&r" (t1), "=&r" (t2), "=&r"(t3), "=&b" (rmd) : \
"0" (num)); \
\
} while(0);
} while(0);
#define SIGN 1 /* unsigned/signed long */
#define LARGE 2 /* use 'ABCDEF' instead of 'abcdef' */
@@ -976,7 +976,7 @@ static char * number(char * str, int size, int type, u64 num)
sign = '-';
num = -num;
size--;
}
}
}
i = 0;
@@ -990,7 +990,7 @@ static char * number(char * str, int size, int type, u64 num)
}
tmp[i++] = digits[rem];
} while (num != 0);
size -= i;
if (!(type&(ZEROPAD)))
while(size-->0)
@@ -1024,14 +1024,14 @@ int k_vsprintf(char *buf, const char *fmt, va_list args)
*str++ = *fmt;
continue;
}
/* process flags, only 0 padding needed */
flags = 0;
if (*++fmt == '0' ) {
flags |= ZEROPAD;
fmt++;
}
/* get field width */
field_width = -1;
if (is_digit(*fmt))
@@ -1094,14 +1094,14 @@ int k_vsprintf(char *buf, const char *fmt, va_list args)
--fmt;
continue;
}
/* This ugly code tries to minimize the number of va_arg()
* since they expand to a lot of code on PPC under the SYSV
* calling conventions (but not with -mcall-aix which has
/* This ugly code tries to minimize the number of va_arg()
* since they expand to a lot of code on PPC under the SYSV
* calling conventions (but not with -mcall-aix which has
* other problems). Arguments have at least the size of a
* long allocated, and we use this fact to minimize bloat.
* (and pointers are assimilated to unsigned long too).
*/
if (sizeof(long long) > sizeof(long) && flags & LLONG)
if (sizeof(long long) > sizeof(long) && flags & LLONG)
num = va_arg(args, unsigned long long);
else {
u_long n = va_arg(args, unsigned long);
@@ -1111,10 +1111,10 @@ int k_vsprintf(char *buf, const char *fmt, va_list args)
else
n = (unsigned short) n;
} else if (! flags & LONG) {
/* Here the compiler correctly removes this
/* Here the compiler correctly removes this
* do nothing code on 32 bit PPC.
*/
if (flags & SIGN)
if (flags & SIGN)
n = (int) n;
else
n = (unsigned) n;
c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c
+21 -21
View File
@@ -1,6 +1,6 @@
/* rsPMCQ1.c - Radstone PMCQ1 Common Initialisation Code
*
* Copyright 2000 Radstone Technology
* Copyright 2000 Radstone Technology
*
* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
@@ -34,7 +34,7 @@ call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's.
#include <libcpu/io.h>
#include <bsp/irq.h>
#include <stdlib.h>
#include <rtems/bspIo.h>
#include <rtems/bspIo.h>
#include <bsp/pci.h>
#include <bsp.h>
#include "rsPMCQ1.h"
@@ -103,7 +103,7 @@ int read32( int addr){
void rsPMCQ1_scc_nullFunc(void) {}
/*******************************************************************************
* rsPMCQ1Int - handle a PMCQ1 interrupt
*
@@ -185,7 +185,7 @@ unsigned int rsPMCQ1MaIntConnect (
for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
{
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
(boardData->funcNo == funcNo))
{
boardData->maInt = routine;
@@ -206,7 +206,7 @@ unsigned int rsPMCQ1MaIntConnect (
return (status);
}
/*******************************************************************************
*
* rsPMCQ1MaIntDisconnect - disconnect a MiniAce interrupt routine
@@ -227,7 +227,7 @@ unsigned int rsPMCQ1MaIntDisconnect(
unsigned int status = RTEMS_IO_ERROR;
for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) {
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
(boardData->funcNo == funcNo))
{
boardData->maInt = NULL;
@@ -239,7 +239,7 @@ unsigned int rsPMCQ1MaIntDisconnect(
return (status);
}
/*******************************************************************************
*
* rsPMCQ1QuiccIntConnect - connect a Quicc interrupt routine
@@ -263,8 +263,8 @@ unsigned int rsPMCQ1QuiccIntConnect(
for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
{
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
(boardData->funcNo == funcNo))
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
(boardData->funcNo == funcNo))
{
boardData->quiccInt = routine;
boardData->quiccArg = arg;
@@ -274,7 +274,7 @@ unsigned int rsPMCQ1QuiccIntConnect(
}
return (status);
}
/*******************************************************************************
*
* rsPMCQ1QuiccIntDisconnect - disconnect a Quicc interrupt routine
@@ -294,9 +294,9 @@ unsigned int rsPMCQ1QuiccIntDisconnect(
PPMCQ1BoardData boardData;
unsigned int status = RTEMS_IO_ERROR;
for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
{
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&
(boardData->funcNo == funcNo))
{
boardData->quiccInt = NULL;
@@ -308,8 +308,8 @@ unsigned int rsPMCQ1QuiccIntDisconnect(
return (status);
}
/*******************************************************************************
*
* rsPMCQ1Init - initialize the PMCQ1's
@@ -363,7 +363,7 @@ unsigned int rsPMCQ1Init(void)
eieio();
/*
* Hold QBus in reset for 1ms
* Hold QBus in reset for 1ms
*/
MsDelay();
@@ -376,7 +376,7 @@ unsigned int rsPMCQ1Init(void)
/* If a QUICC is fitted initialise it */
if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED)
{
#ifdef DEBUG_360
#ifdef DEBUG_360
printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
#endif
@@ -393,7 +393,7 @@ unsigned int rsPMCQ1Init(void)
eieio();
/* Disable the SWT and perform basic initialisation */
write8(baseaddr+Q1_360_SIM_SYPCR,0);
write8(baseaddr+Q1_360_SIM_SYPCR,0);
eieio();
write32(baseaddr+Q1_360_SIM_MCR,0xa0001029);
@@ -411,11 +411,11 @@ unsigned int rsPMCQ1Init(void)
eieio();
write32(baseaddr+Q1_360_SIM_OR0,0x1ff00000); /*| MEMC_OR_FC*/
eieio();
write32(baseaddr+Q1_360_SIM_BR0,0);
write32(baseaddr+Q1_360_SIM_BR0,0);
eieio();
write32(baseaddr+Q1_360_SIM_OR1,(0x5ff00000 | 0x00000780)); /*| MEMC_OR_FC*/
eieio();
write32(baseaddr+Q1_360_SIM_BR1,(0x00000040 | 0x00000001 | 0x00200280) );
write32(baseaddr+Q1_360_SIM_BR1,(0x00000040 | 0x00000001 | 0x00200280) );
eieio();
}
@@ -465,7 +465,7 @@ unsigned int rsPMCQ1Init(void)
/*
* Enable PMCQ1 Interrupts from QSPAN-II
*/
*(unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
eieio();
*(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
@@ -549,7 +549,7 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo )
printk("Error writing byte %d expected 0x%02x got 0x%02x\n",
i, rsPMCQ1eeprom[i], (unsigned char)(val >> 8));
status = RTEMS_IO_ERROR;
break;
break;
}
}
}
c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h
+21 -21
View File
@@ -37,28 +37,28 @@
* PMCQ1 definitions
*/
/*
* 360 definitions
/*
* 360 definitions
*/
#define Q1_360_MBAR 0x0003ff00 /* master base address register */
#define REG_B_OFFSET 0x1000 /* offset to the internal registers */
#define Q1_360_SIM_MCR (REG_B_OFFSET+0x00)
#define Q1_360_SIM_PEPAR (REG_B_OFFSET+0x16)
#define Q1_360_SIM_SYPCR (REG_B_OFFSET+0x22)
#define Q1_360_SIM_PICR (REG_B_OFFSET+0x26)
#define Q1_360_SIM_PITR (REG_B_OFFSET+0x2A)
#define Q1_360_SIM_GMR (REG_B_OFFSET+0x40)
#define Q1_360_SIM_BR0 (REG_B_OFFSET+0x50)
#define Q1_360_SIM_OR0 (REG_B_OFFSET+0x54)
#define Q1_360_SIM_BR1 (REG_B_OFFSET+0x60)
#define Q1_360_SIM_OR1 (REG_B_OFFSET+0x64)
#define Q1_360_SIM_MCR (REG_B_OFFSET+0x00)
#define Q1_360_SIM_PEPAR (REG_B_OFFSET+0x16)
#define Q1_360_SIM_SYPCR (REG_B_OFFSET+0x22)
#define Q1_360_SIM_PICR (REG_B_OFFSET+0x26)
#define Q1_360_SIM_PITR (REG_B_OFFSET+0x2A)
#define Q1_360_SIM_GMR (REG_B_OFFSET+0x40)
#define Q1_360_SIM_BR0 (REG_B_OFFSET+0x50)
#define Q1_360_SIM_OR0 (REG_B_OFFSET+0x54)
#define Q1_360_SIM_BR1 (REG_B_OFFSET+0x60)
#define Q1_360_SIM_OR1 (REG_B_OFFSET+0x64)
#define Q1_360_CPM_ICCR (REG_B_OFFSET+0x500)
#define Q1_360_CPM_SDCR (REG_B_OFFSET+0x51E)
#define Q1_360_CPM_CICR (REG_B_OFFSET+0x540)
#define Q1_360_CPM_ICCR (REG_B_OFFSET+0x500)
#define Q1_360_CPM_SDCR (REG_B_OFFSET+0x51E)
#define Q1_360_CPM_CICR (REG_B_OFFSET+0x540)
/*
* EPLD offsets
@@ -123,9 +123,9 @@ typedef void (*FUNCION_PTR) (int);
typedef struct _PMCQ1BoardData
typedef struct _PMCQ1BoardData
{
struct _PMCQ1BoardData *pNext;
struct _PMCQ1BoardData *pNext;
unsigned long busNo;
unsigned long slotNo;
unsigned long funcNo;
@@ -143,10 +143,10 @@ extern PPMCQ1BoardData pmcq1BoardData;
* Function declarations
*/
extern unsigned int rsPMCQ1QuiccIntConnect(
unsigned long busNo,
unsigned long slotNo,
unsigned long funcNo,
FUNCION_PTR routine,
unsigned long busNo,
unsigned long slotNo,
unsigned long funcNo,
FUNCION_PTR routine,
int arg
);
unsigned int rsPMCQ1Init(void);
c/src/lib/libbsp/powerpc/ep1a/include/bsp.h
+8 -8
View File
@@ -21,18 +21,18 @@
#include <bsp/vectors.h>
/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
#define _IO_BASE CHRP_ISA_IO_BASE
#define _IO_BASE CHRP_ISA_IO_BASE
#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
#define PCI_MEM_BASE 0x80000000
#define PCI_MEM_BASE_ADJUSTMENT 0
#define PCI_MEM_BASE_ADJUSTMENT 0
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
/* offset of pci memory as seen from the CPU */
#undef PCI_MEM_BASE
#define PCI_MEM_BASE 0x00000000
#define PCI_MEM_BASE 0x00000000
/* Override the default values for the following DEFAULT */
#define PCI_CONFIG_ADDR 0xfec00000 /* 0xcf8 */
@@ -67,7 +67,7 @@
#define PMC_SLOT1_PRESENT 0x02
#define PMC_SLOT2_PRESENT 0x01
/* BOARD_REVISION_REGISTER1 */
#define ARTWORK_REVISION_MASK 0xf0
#define BUILD_REVISION_MASK 0x0f
@@ -105,7 +105,7 @@
* address definitions for several devices
*
*/
#define UART_OFFSET_1_8245 (0x04500)
#define UART_OFFSET_1_8245 (0x04500)
#define UART_OFFSET_2_8245 (0x04600)
#define UART_BASE_COM1 0xff800000
#define UART_BASE_COM2 0xff800040
@@ -117,7 +117,7 @@
* 8245 docs.
* This is an offset from EUMBBAR
*/
#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
* to implement VME IRQ priorities in software.
@@ -151,7 +151,7 @@
extern unsigned int EUMBBAR;
/*
* Total memory
* Total memory
*/
extern unsigned int BSP_mem_size;
@@ -181,7 +181,7 @@ extern int BSP_disconnect_clock_handler (void);
extern int BSP_connect_clock_handler (void);
/*
* FLASH
* FLASH
*/
int BSP_FLASH_Enable_writes( uint32_t area );
int BSP_FLASH_Disable_writes( uint32_t area );
c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
+6 -6
View File
@@ -127,7 +127,7 @@ static unsigned char mcp750_openpic_initsenses[] = {
1, /*14 MCP750_INT_PCI_BUS2_INTC */
1, /*15 MCP750_INT_PCI_BUS2_INTD */
1,
1,
1,
1,
1,
1,
@@ -151,9 +151,9 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
/*
* First initialize the Interrupt management hardware
*/
#ifdef TRACE_IRQ_INIT
#ifdef TRACE_IRQ_INIT
printk("Going to initialize openpic compliant device\n");
#endif
#endif
/* FIXME (t.s.): we should probably setup the EOI delay by
* passing a non-zero 'epic_freq' argument (frequency of the
* EPIC serial interface) but I don't know the value on this
@@ -161,7 +161,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
*/
openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */);
#ifdef TRACE_IRQ_INIT
#ifdef TRACE_IRQ_INIT
printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
#endif
@@ -191,8 +191,8 @@ printk("Call BSP_rtems_irq_mngt_set\n");
*/
BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
}
#ifdef TRACE_IRQ_INIT
#ifdef TRACE_IRQ_INIT
printk("RTEMS IRQ management is now operationnal\n");
#endif
}
c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c
+1 -1
View File
@@ -109,7 +109,7 @@ printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);
BSP_irq_enable_at_i8259s ((int) name);
}
#endif
if (is_pci_irq(name)) {
/*
* Enable interrupt at OPENPIC level
c/src/lib/libbsp/powerpc/ep1a/pci/no_host_bridge.c
+4 -4
View File
@@ -8,20 +8,20 @@
*
* $Id$
*/
#include <libcpu/io.h>
#include <libcpu/spr.h>
#include <bsp.h>
#include <bsp/pci.h>
#include <bsp/consoleIo.h>
#include <bsp/residual.h>
#include <bsp/openpic.h>
#include <rtems/bspIo.h>
/*
* For the 8240 and the 8245 there is no host bridge the
* For the 8240 and the 8245 there is no host bridge the
* Open PIC device is built into the processor chip.
*/
c/src/lib/libbsp/powerpc/ep1a/start/start.S
+2 -2
View File
@@ -40,7 +40,7 @@
#warning The call is "void boot_card(const char* cmdline);"
#warning You need to pass a NULL.
#warning Please check and remove these warnings.
#include <rtems/asm.h>
#include <rtems/score/cpu.h>
#include <libcpu/io.h>
@@ -73,7 +73,7 @@ __rtems_entry_point:
*/
li r3,MSR_IR | MSR_DR | MSR_FP
mtmsr r3
/* XXX - ADD BACK IN CACHING INSTRUCTIONS */
/* clear bss */
c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c
+26 -26
View File
@@ -88,7 +88,7 @@ uint32_t VME_Slot1 = FALSE;
/*
* PCI Bus Frequency
*/
unsigned int BSP_bus_frequency;
unsigned int BSP_bus_frequency;
/*
* processor clock frequency
@@ -103,25 +103,25 @@ unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */
void BSP_panic(char *s)
{
printk("%s PANIC %s\n",_RTEMS_version, s);
__asm__ __volatile ("sc");
__asm__ __volatile ("sc");
}
void _BSP_Fatal_error(unsigned int v)
{
printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
__asm__ __volatile ("sc");
__asm__ __volatile ("sc");
}
int BSP_FLASH_Disable_writes(
uint32_t area
)
{
unsigned char data;
data = *GENERAL_REGISTER1;
data |= DISABLE_USER_FLASH;
*GENERAL_REGISTER1 = data;
return RTEMS_SUCCESSFUL;
}
@@ -130,11 +130,11 @@ int BSP_FLASH_Enable_writes(
)
{
unsigned char data;
data = *GENERAL_REGISTER1;
data &= (~DISABLE_USER_FLASH);
*GENERAL_REGISTER1 = data;
return RTEMS_SUCCESSFUL;
}
@@ -143,7 +143,7 @@ void BSP_FLASH_set_page(
)
{
unsigned char data;
/* Set the flash page register. */
data = *GENERAL_REGISTER2;
data &= ~(BSP_FLASH_PAGE_MASK);
@@ -170,7 +170,7 @@ void zero_bss(void)
char * save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options)
{
#if 0
#if 0
residualCopy = *r3;
strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM);
loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
@@ -186,14 +186,14 @@ unsigned int get_eumbbar(void) {
asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) );
asm volatile("sync");
asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a));
asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a));
asm volatile("sync");
asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
asm volatile("sync");
asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
asm volatile("isync");
return e;
@@ -212,12 +212,12 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK;
if ( value == HARDWARE_ID_PPC5_EP1A )
printk(" EP1A ");
else if ( value == HARDWARE_ID_EP1B )
else if ( value == HARDWARE_ID_EP1B )
printk(" EP1B ");
else
printk(" Unknown ");
value = *BOARD_REVISION_REGISTER2&0x1;
value = *BOARD_REVISION_REGISTER2&0x1;
printk("Board ID %08x", value);
if(value == 0x0){
VME_Slot1 = TRUE;
@@ -293,10 +293,10 @@ void bsp_start( void )
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
EUMBBAR = get_eumbbar();
EUMBBAR = get_eumbbar();
printk("EUMBBAR 0x%08x\n", EUMBBAR );
/*
/*
* Note this sets BSP_processor_frequency based upon register settings.
* It must be done prior to setting up hooks.
*/
@@ -341,13 +341,13 @@ ShowBATS();
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Going to start PCI buses scanning and initialization\n");
#endif
#endif
pci_initialize();
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Number of PCI buses found is : %d\n", pci_bus_count());
#endif
#ifdef TEST_RAW_EXCEPTION_CODE
#ifdef TEST_RAW_EXCEPTION_CODE
printk("Testing exception handling Part 1\n");
/*
@@ -360,17 +360,17 @@ ShowBATS();
*/
printk("Testing exception handling Part 2\n");
__asm__ __volatile ("sc");
#endif
#endif
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
/* Activate the page table mappings only after
* initializing interrupts because the irq_mng_init()
* routine needs to modify the text
*/
*/
if (pt) {
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Page table setup finished; will activate it NOW...\n");
@@ -394,5 +394,5 @@ ShowBATS();
#ifdef SHOW_MORE_INIT_SETTINGS
ShowBATS();
printk("Exit from bspstart\n");
#endif
#endif
}
c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h
+11 -11
View File
@@ -4,19 +4,19 @@
/* BSP specific address space configuration parameters */
/*
/*
* Authorship
* ----------
* This software was created by
* Till Straumann <strauman@slac.stanford.edu>, 2002,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* This software was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -25,18 +25,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -45,9 +45,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
/*
* The BSP maps VME address ranges into
* one BAT.
@@ -77,7 +77,7 @@
* at _VME_DRAM_OFFSET
*/
#undef _VME_DRAM_OFFSET
#define _VME_DRAM_OFFSET 0xc0000000
#define _VME_DRAM_OFFSET 0xc0000000
#define _VME_DRAM_32_OFFSET1 0x20000000
#define _VME_DRAM_32_OFFSET2 0x20b00000
#define _VME_DRAM_24_OFFSET1 0x00000000
@@ -85,7 +85,7 @@
#define _VME_DRAM_16_OFFSET1 0x00000000
#define _VME_DRAM_16_OFFSET2 0x00008000
#define _VME_A24_SIZE 0x00100000
#define _VME_A24_SIZE 0x00100000
#define _VME_A16_SIZE 0x00008000
#undef _VME_CSR_ON_PCI
c/src/lib/libbsp/powerpc/gen83xx/console/config.c
+1 -1
View File
@@ -23,7 +23,7 @@
/* derived from: */
/*
* This file contains the TTY driver table for the EP1A
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
c/src/lib/libbsp/powerpc/gen83xx/console/console.c
+9 -9
View File
@@ -56,7 +56,7 @@
console_data Console_Port_Data[NUM_CONSOLE_PORTS];
unsigned long Console_Port_Count;
rtems_device_minor_number Console_Port_Minor;
bool Console_Is_Initialized = false;
bool Console_Is_Initialized = false;
/* PAGE
*
* console_open
@@ -92,9 +92,9 @@ rtems_device_driver console_open(
Callbacks.pollRead = c->deviceRead;
Callbacks.write = c->deviceWrite;
Callbacks.setAttributes = c->deviceSetAttributes;
Callbacks.stopRemoteTx =
Callbacks.stopRemoteTx =
Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx;
Callbacks.startRemoteTx =
Callbacks.startRemoteTx =
Console_Port_Tbl[minor].pDeviceFlow->deviceStartRemoteTx;
Callbacks.outputUsesInterrupts = c->deviceOutputUsesInterrupts;
status = rtems_termios_open ( major, minor, arg, &Callbacks);
@@ -105,7 +105,7 @@ rtems_device_driver console_open(
return status;
}
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -123,7 +123,7 @@ rtems_device_driver console_close(
return rtems_termios_close (arg);
}
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -132,7 +132,7 @@ rtems_device_driver console_read(
{
return rtems_termios_read (arg);
}
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -141,7 +141,7 @@ rtems_device_driver console_write(
{
return rtems_termios_write (arg);
}
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -177,7 +177,7 @@ rtems_device_driver console_initialize(
minor++)
{
/*
* transfer the real internal bus frequency into the
* transfer the real internal bus frequency into the
* console port table
*/
Console_Port_Tbl[minor].ulClock = BSP_bus_frequency;
@@ -202,7 +202,7 @@ rtems_device_driver console_initialize(
*/
rtems_fatal_error_occurred(RTEMS_IO_ERROR);
}
Console_Port_Minor=minor;
/*
c/src/lib/libbsp/powerpc/gen83xx/console/ns16550cfg.c
+3 -3
View File
@@ -37,7 +37,7 @@
#include <rtems.h>
#include <bsp.h>
#include "console.h"
typedef struct uart_reg
{
volatile unsigned char reg;
@@ -50,7 +50,7 @@ uint8_t Read_ns16550_register(
{
struct uart_reg *p = (struct uart_reg *)ulCtrlPort;
uint8_t ucData;
ucData = p[ucRegNum].reg;
ucData = p[ucRegNum].reg;
asm volatile("sync");
return ucData;
}
@@ -62,6 +62,6 @@ void Write_ns16550_register(
)
{
struct uart_reg *p = (struct uart_reg *)ulCtrlPort;
p[ucRegNum].reg = ucData;
p[ucRegNum].reg = ucData;
asm volatile("sync");
}
c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c
+2 -2
View File
@@ -47,7 +47,7 @@ static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
.irq_number = BSP_IPIC_IRQ_I2C2,
.base_frq = 0 /* will be set during initiailization */
}
}
}
};
rtems_libi2c_bus_t *mpc83xx_i2c_bus_descriptor[2] = {
@@ -89,7 +89,7 @@ rtems_status_code bsp_register_i2c
* I2C1 is clocked with TSEC 1
*/
if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) {
mpc83xx_i2c_bus_tbl[0].softc.base_frq =
mpc83xx_i2c_bus_tbl[0].softc.base_frq =
(BSP_bus_frequency
/((mpc83xx.clk.sccr >> (31-1)) & 0x03));
}
c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
+1 -1
View File
@@ -36,7 +36,7 @@
#endif /* MPC8313ERDB */
#include <libcpu/powerpc-utility.h>
#include <libcpu/powerpc-utility.h>
#include <bsp/hwreg_vals.h>
c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
+12 -12
View File
@@ -40,7 +40,7 @@
* clocking infos
*/
#define BSP_CLKIN_FRQ 66000000L
#define RCFG_SYSPLL_MF 4
#define RCFG_SYSPLL_MF 4
#define RCFG_COREPLL_MF 4
/*
@@ -80,7 +80,7 @@
* clocking infos
*/
#define BSP_CLKIN_FRQ 30000000L
#define RCFG_SYSPLL_MF 11
#define RCFG_SYSPLL_MF 11
#define RCFG_COREPLL_MF 4
/*
* Reset configuration words
@@ -115,7 +115,7 @@
#endif
#if defined(MPC8349EAMDS)
#if defined(MPC8349EAMDS)
/**************************
* for Freescale MPC8349EAMDS
*/
@@ -126,7 +126,7 @@
/*
* Local Access Windows
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define LBLAWBAR0_VAL 0xFE000000
#define LBLAWAR0_VAL 0x80000016
@@ -138,7 +138,7 @@
#define DDRLAWAR0_VAL 0x8000001B
/*
* Local Bus (Memory) Controller
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define BR0_VAL 0xFE001001
#define OR0_VAL 0xFF806FF7
@@ -148,7 +148,7 @@
#define OR2_VAL 0xFC006901
/*
* SDRAM registers
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define MRPTR_VAL 0x20000000
#define LSRT_VAL 0x32000000
@@ -157,7 +157,7 @@
/*
* DDR-SDRAM registers
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define CS2_BNDS_VAL 0x00000007
#define CS3_BNDS_VAL 0x0008000F
@@ -201,7 +201,7 @@
/*
* Local Access Windows
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define LBLAWBAR0_VAL bsp_rom_start
@@ -212,7 +212,7 @@
#define DDRLAWAR0_VAL 0x8000001B
/*
* Local Bus (Memory) Controller
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define BR0_VAL (0xFE000000 | 0x01001)
#define OR0_VAL 0xFE000E54
@@ -238,7 +238,7 @@
/*
* DDR-SDRAM registers
* FIXME: decode bit settings
* FIXME: decode bit settings
*/
#define DDRCDR_VAL 0x00000001
#define CS0_BNDS_VAL 0x0000000F
@@ -273,8 +273,8 @@
/* value of input clock divider (derived from pll mode reg) */
#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
/* value of system pll (derived from pll mode reg) */
#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f)
#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f)
/* value of system pll (derived from pll mode reg) */
#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f)
#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f)
#endif /* __GEN83xx_HWREG_VALS_h */
c/src/lib/libbsp/powerpc/gen83xx/include/irq.h
+1 -1
View File
@@ -26,7 +26,7 @@
#include <rtems/irq-extension.h>
/*
* the following definitions specify the indices used
* the following definitions specify the indices used
* to interface the interrupt handler API
*/
c/src/lib/libbsp/powerpc/gen83xx/irq/irq.c
+3 -3
View File
@@ -291,7 +291,7 @@ static const uint8_t mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBE
};
/*
* this array will be filled with mask values needed
* this array will be filled with mask values needed
* to temporarily disable all IRQ soures with lower or same
* priority of the current source (whose vector is the array index)
*/
@@ -493,8 +493,8 @@ rtems_status_code mpc83xx_ipic_calc_prio2mask( void)
*/
rtems_status_code mpc83xx_ipic_initialize( void)
{
/*
* mask off all interrupts
/*
* mask off all interrupts
*/
mpc83xx.ipic.simsr [0] = 0;
mpc83xx.ipic.simsr [1] = 0;
c/src/lib/libbsp/powerpc/gen83xx/network/network.c
+6 -6
View File
@@ -87,8 +87,8 @@ int BSP_tsec_attach
if (unitNumber == 1) {
/*
* init system I/O configuration registers
* to ensure proper pin functions
* init system I/O configuration registers
* to ensure proper pin functions
*/
mpc83xx.syscon.sicrh = mpc83xx.syscon.sicrh & ~0x1F800000;
/*
@@ -99,8 +99,8 @@ int BSP_tsec_attach
}
if (unitNumber == 2) {
/*
* init system I/O configuration registers
* to ensure proper pin functions
* init system I/O configuration registers
* to ensure proper pin functions
*/
mpc83xx.syscon.sicrh = mpc83xx.syscon.sicrh & ~0x007f8000;
/*
@@ -116,7 +116,7 @@ int BSP_tsec_attach
/*
* Nothing special needed for TSEC1 operation
*/
#endif
#endif
}
/*
* add MAC address into config->hardware_adderss
@@ -131,7 +131,7 @@ int BSP_tsec_attach
/* we expect it htere from the boot loader */
reg_ptr = &mpc83xx.tsec[unitNumber - 1];
config->hardware_address = hw_addr[unitNumber-1];
hw_addr[unitNumber-1][5] = (reg_ptr->macstnaddr[0] >> 24) & 0xff;
hw_addr[unitNumber-1][4] = (reg_ptr->macstnaddr[0] >> 16) & 0xff;
hw_addr[unitNumber-1][3] = (reg_ptr->macstnaddr[0] >> 8) & 0xff;
c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c
+6 -6
View File
@@ -104,13 +104,13 @@ static rtems_status_code bsp_spi_sel_addr
* GPIO1[24] is SPI_A0
* GPIO1[25] is SPI_A1
* GPIO1[26] is SPI_A2
* set pins to address
* set pins to address
*/
mpc83xx.gpio[0].gpdat =
mpc83xx.gpio[0].gpdat =
(mpc83xx.gpio[0].gpdat & ~(0x7 << (31-26)))
| (addr << (31-26));
/*
* GPIO1[27] is high-active strobe
* GPIO1[27] is high-active strobe
*/
mpc83xx.gpio[0].gpdat |= (1 << (31- 27));
@@ -154,7 +154,7 @@ static rtems_status_code bsp_spi_send_start_dummy
#elif defined( HSC_CM01)
/*
* GPIO1[27] is high-active strobe
* GPIO1[27] is high-active strobe
* set it to inactive/ low
*/
mpc83xx.gpio[0].gpdat &= ~(0x1 << (31-27));
@@ -204,7 +204,7 @@ static rtems_status_code bsp_spi_send_stop
/*
* deselect device
* GPIO1[27] is high-active strobe
* GPIO1[27] is high-active strobe
*/
mpc83xx.gpio[0].gpdat &= ~(1 << (31- 27));
@@ -351,7 +351,7 @@ rtems_status_code bsp_register_spi
* GPIO1[24] is SPI_A0
* GPIO1[25] is SPI_A1
* GPIO1[26] is SPI_A2
* GPIO1[27] is high-active strobe
* GPIO1[27] is high-active strobe
* set pins to be output, low
*/
mpc83xx.gpio[0].gpdat &= ~(0xf << (31-27));
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
+43 -43
View File
@@ -16,10 +16,10 @@
+-----------------------------------------------------------------+
| this file contains the startup assembly code |
\*===============================================================*/
/* $Id$ */
/* $Id$ */
#include <libcpu/powerpc-utility.h>
#include <libcpu/powerpc-utility.h>
#include <rtems/powerpc/cache.h>
#include <bsp.h>
#include <mpc83xx/mpc83xx.h>
@@ -27,7 +27,7 @@
.macro SET_IMM_REGW base, reg2, offset, value
LA \reg2, \value
stw \reg2,\offset(\base)
.endm
.endm
#define REP8(l) l ; l; l; l; l; l; l; l;
@@ -37,7 +37,7 @@
#if defined(RESET_CONF_WRD_L)
.section ".resconf","ax"
PUBLIC_VAR (reset_conf_words)
reset_conf_words:
reset_conf_words:
REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff))
@@ -51,10 +51,10 @@ reset_conf_words:
.section ".vectors","ax"
PUBLIC_VAR (reset_vec)
reset_vec:
reset_vec:
bl rom_entry
.section ".entry"
.section ".entry"
PUBLIC_VAR (start)
start:
@@ -84,7 +84,7 @@ copy_uboot_board_info:
#endif /* HAS_UBOOT */
/*
* basic CPU setup:
* basic CPU setup:
* init MSR
*/
mfmsr r30
@@ -93,18 +93,18 @@ copy_uboot_board_info:
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
b start_rom_skip
PUBLIC_VAR (rom_entry)
rom_entry:
/*
* basic CPU setup:
* basic CPU setup:
* init MSR
*/
mfmsr r30
SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_IP|MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
/*
* ROM startup: remap IMMR to 0xE0000000
* use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR"
@@ -147,14 +147,14 @@ rom_entry:
mtlr r29
blr /* now further execution in upper ROM */
start_code_in_rom:
start_code_in_rom:
#ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL
#endif
#ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL
#endif
#endif
#ifdef LBLAWBAR1_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL
#endif
@@ -232,7 +232,7 @@ start_code_in_rom:
*/
#ifdef MRPTR_VAL
SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL
#endif
#endif
/*
* ROM startup: init SDRAM
*/
@@ -357,7 +357,7 @@ start_rom_skip:
start_rom_skip1:
mflr r20
LA r30,start_rom_skip1
sub. r20,r20,r30
sub. r20,r20,r30
/*
* execution address offset == 0?
* then do not relocate code and data
@@ -367,24 +367,24 @@ start_rom_skip1:
* ROM or relocatable startup: copy startup code to SDRAM
*/
/* get start address of text section in RAM */
LA r29, bsp_section_text_start
LA r29, bsp_section_text_start
/* get start address of text section in ROM (add reloc offset) */
add r30, r20, r29
add r30, r20, r29
/* get size of startup code */
LA r28, end_reloc_startup
LA r31, bsp_section_text_start
sub 28,r28,r31
/* copy startup code from ROM to RAM location */
bl copy_image
bl copy_image
/*
* ROM startup: jump to code copy in SDRAM
*/
/* get compile time address of label */
LA r29, copy_rest_of_text
LA r29, copy_rest_of_text
mtlr r29
blr /* now further execution RAM */
copy_rest_of_text:
copy_rest_of_text:
#ifdef LCRR_VAL
SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
#endif
@@ -394,27 +394,27 @@ copy_rest_of_text:
/* get start address of rest of code in RAM */
LA r29, end_reloc_startup
/* get start address of text section in ROM (add reloc offset) */
add r30, r20, r29
add r30, r20, r29
/* get size of rest of code */
LA r28, bsp_section_text_start
LA r31, bsp_section_text_size
add r28,r28,r31
sub r28,r28,r29
bl copy_image /* copy text section from ROM to RAM location */
/*
* ROM or relocatable startup: copy data to SDRAM
*/
/* get start address of data section in RAM */
LA r29, bsp_section_data_start
LA r29, bsp_section_data_start
/* get start address of data section in ROM (add reloc offset) */
add r30, r20, r29
add r30, r20, r29
/* get size of RAM image */
LA r28, bsp_section_data_size
LA r28, bsp_section_data_size
/* copy initialized data section from ROM to RAM location */
bl copy_image
bl copy_image
start_code_in_ram:
start_code_in_ram:
/*
* ROM/RAM startup: clear bss in SDRAM
@@ -427,8 +427,8 @@ start_code_in_ram:
*/
/* Set stack pointer (common for RAM/ROM startup) */
LA r1, bsp_section_text_start
addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
LA r1, bsp_section_text_start
addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
/* Create NULL */
li r0, 0
@@ -451,12 +451,12 @@ start_code_in_ram:
xor r3, r3, r3
bl SYM (boot_card) /* Call the first C routine */
twiddle:
/* We don't expect to return from boot_card but if we do */
/* wait here for watchdog to kick us into hard reset */
b twiddle
b twiddle
copy_image:
mr r27, r28
srwi r28, r28, 2
@@ -466,13 +466,13 @@ copy_image:
sub r27, r27, r28 /* maybe some residual bytes */
copy_image_word:
lswi r28, r30, 0x04
stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
addi r30, r30, 0x04 /* increment source pointer */
addi r29, r29, 0x04 /* increment destination pointer */
bdnz copy_image_word /* decrement ctr and branch if not 0 */
cmpwi r27, 0x00 /* copy image finished ? */
@@ -480,19 +480,19 @@ copy_image_word:
mtctr r27 /* reload counter for residual bytes */
copy_image_byte:
lswi r28, r30, 0x01
stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
addi r30, r30, 0x01 /* increment source pointer */
addi r29, r29, 0x01 /* increment destination pointer */
bdnz copy_image_byte /* decrement ctr and branch if not 0 */
copy_image_end:
blr
/**
* @fn int mpc83xx_zero_4( void *dest, size_t n)
*
@@ -542,7 +542,7 @@ mpc83xx_zero_4_tail:
stwx r0, r3, r8
addi r8, r8, 16
bdnz mpc83xx_zero_4_tail
/* Return */
blr
c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
+12 -12
View File
@@ -110,18 +110,18 @@ static void calc_dbat_regvals(
while ((end_addr & block_mask) != (base_addr & block_mask)) {
block_mask <<= 1;
}
bat_ptr->batu.bepi = base_addr >> (32 - 15);
bat_ptr->batu.bepi = base_addr >> (32 - 15);
bat_ptr->batu.bl = ~(block_mask >> (28 - 11));
bat_ptr->batu.vs = 1;
bat_ptr->batu.vp = 1;
bat_ptr->batl.brpn = base_addr >> (32 - 15);
bat_ptr->batl.w = flg_w;
bat_ptr->batl.i = flg_i;
bat_ptr->batl.m = flg_m;
bat_ptr->batl.g = flg_g;
bat_ptr->batl.pp = flg_bpp;
bat_ptr->batl.brpn = base_addr >> (32 - 15);
bat_ptr->batl.w = flg_w;
bat_ptr->batl.i = flg_i;
bat_ptr->batl.m = flg_m;
bat_ptr->batl.g = flg_g;
bat_ptr->batl.pp = flg_bpp;
}
static void clear_mmu_regs( void)
@@ -132,7 +132,7 @@ static void clear_mmu_regs( void)
for (i = 0;i < 16;i++) {
asm volatile( "mtsrin %0, %1\n" : : "r" (i * 0x1000), "r" (i << (31 - 3)));
}
/* Clear TLBs */
for (i = 0;i < 32;i++) {
asm volatile( "tlbie %0\n" : : "r" (i << (31 - 19)));
@@ -151,7 +151,7 @@ void cpu_init( void)
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK);
PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
/*
* Set up IBAT registers in MMU
*/
@@ -301,7 +301,7 @@ void cpu_init( void)
ppc_set_machine_state_register( msr);
/*
* In HID0:
* In HID0:
* - Enable dynamic power management
* - Enable machine check interrupts
*/
c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S
+13 -13
View File
@@ -36,7 +36,7 @@
* Further changes to derive for the PPC405CR/GP/GPr/EX/EXr
* by Michael Hamel ADInstruments Ltd 2008
*
*
*
* Id: dlentry.S,v 1.2 2000/08/02 16:30:57 joel Exp
*/
@@ -44,7 +44,7 @@
#warning The call is "void boot_card(const char* cmdline);"
#warning You need to pass a NULL.
#warning Please check and remove these warnings.
#include <rtems/asm.h>
/*
@@ -82,7 +82,7 @@
PUBLIC_VAR (start)
PUBLIC_VAR (download_entry)
PUBLIC_VAR (__rtems_entry_point)
SYM(start):
SYM(download_entry):
SYM(__rtems_entry_point):
@@ -95,7 +95,7 @@ SYM(__rtems_entry_point):
/*---------------------------------------------------------------------------
* Parameters from linker
*--------------------------------------------------------------------------*/
base_addr:
toc_pointer:
.long s.got
@@ -125,10 +125,10 @@ text_length:
/* Initialise procesor registers generally */
bl init405
/* Clear .bss and .sbss */
bl bssclr
/*-------------------------------------------------------------------
* C_setup.
*------------------------------------------------------------------*/
@@ -141,9 +141,9 @@ text_length:
stw r3, 12(r1)
bl __eabi /* Initialise EABI: sets up r2 & r13 */
li r3, 0 /* command line */
b SYM (boot_card) /* call the first C routine */
/*---------------------------------------------------------------------------
@@ -175,11 +175,11 @@ clear_sbss: stwu r0,4(r2)
* Generic 405 register setup
*--------------------------------------------------------------------------*/
init405:
li r0, 0
li r0, 0
mtmsr r0
mticcr r0
mtdccr r0
li r3,0x7FFC # 405EX-specific
mtsgr r3 # Clear guarded mode on all storage except PCIe region
@@ -201,13 +201,13 @@ dcloop: dccci 0,r3 # invalidate line
mtdcwr r0 # Select write-back caching
lis r3,0xC000 # Enable 0000 0000 to 0FFF FFFF
# mtdccr r3 # Enable data cache
mtevpr r0
mtesr r0
mtxer r0
lwarx r3,r0,r0 # get some data/set resv bit
stwcx. r3,r0,r0 # store out and clear resv bit
stwcx. r3,r0,r0 # store out and clear resv bit
lis r3,0xDEAD
ori r3,r3,0xBEEF # Make distintive uninitialised value
c/src/lib/libbsp/powerpc/haleakala/include/bsp.h
+2 -2
View File
@@ -72,7 +72,7 @@ extern "C" {
/* Network Defines */
#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
struct rtems_bsdnet_ifconfig;
int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach
@@ -91,7 +91,7 @@ extern "C" {
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
);
#endif /* ASM */
#ifdef __cplusplus
c/src/lib/libbsp/powerpc/haleakala/irq/irq.c
+22 -22
View File
@@ -69,11 +69,11 @@ static inline int IsUICIRQ(const rtems_irq_number irqLine)
static void WriteIState(void)
/* Write the gEnabledInts state masked by gIntInhibited to the hardware */
{
PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER,
PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER,
gEnabledInts[0] & ~gIntInhibited[0]);
PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER,
PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER,
gEnabledInts[1] & ~gIntInhibited[1]);
PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER,
PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER,
gEnabledInts[2] & ~gIntInhibited[2]);
}
@@ -96,7 +96,7 @@ BSP_disable_irq_at_pic(const rtems_irq_number irq)
uint32_t oldState;
int iword = irq>>5;
uint32_t mask = (0x80000000 >> (irq & 0x1F));
oldState = gEnabledInts[iword] & mask;
gEnabledInts[iword] &= ~mask;
WriteIState();
@@ -109,14 +109,14 @@ int
BSP_setup_the_pic(rtems_irq_global_settings* config)
{
int i;
dflt_entry = config->defaultEntry;
rtems_hdl_tblP = config->irqHdlTbl;
for (i=0; i<kUICWords; i++)
gIntInhibited[i] = 0;
/* disable all interrupts */
PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000);
PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000);
/* Set Critical / Non Critical interrupts */
PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000);
/* Set Interrupt Polarities */
@@ -153,7 +153,7 @@ BSP_setup_the_pic(rtems_irq_global_settings* config)
PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001);
/* clear all interrupts */
PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff);
return 1;
}
@@ -164,8 +164,8 @@ BSP_setup_the_pic(rtems_irq_global_settings* config)
*
* No support for critical interrupts here yet
*/
int
int
C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum )
{
if (excNum == ASM_EXT_VECTOR) {
@@ -180,15 +180,15 @@ C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum )
gIntInhibited[0] |= active[0];
gIntInhibited[1] |= active[1];
gIntInhibited[2] |= active[2];
/* ...and update the hardware so the active interrupts are disabled */
WriteIState();
/* Loop, calling bsp_irq_dispatch_list for each active interrupt */
while ((active[0] | active[1] | active[2]) != 0) {
uint32_t index = -1;
uint32_t bit, bmask;
/* Find an active interrupt, searching 0..2, bit 0..bit 31 (IBM order) */
do {
index++;
@@ -201,17 +201,17 @@ C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum )
/* Write a 1-bit to the appropriate status register to clear it */
bmask = 0x80000000 >> bit;
switch (index) {
case 0:
case 0:
PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask);
break;
case 1:
case 1:
PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask);
break;
case 2:
case 2:
PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask);
break;
}
/* Clear in the active record and gIntInhibited */
active[index] &= ~bmask;
gIntInhibited[index] &= ~bmask;
@@ -220,20 +220,20 @@ C_dispatch_irq_handler( BSP_Exception_frame* frame, unsigned int excNum )
/* Update the hardware again so the interrupts we have handled are unmasked */
WriteIState();
return 0;
} else if (excNum == ASM_DEC_VECTOR) { /* 0x1000 remapped by C_dispatch_dec_handler_bookE */
bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_PIT, dflt_entry.hdl);
return 0;
} else if (excNum == ASM_BOOKE_FIT_VECTOR) { /* 0x1010 mapped to 0x13 by ppc_get_vector_addr */
bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_FIT, dflt_entry.hdl);
return 0;
} else if (excNum == ASM_BOOKE_WDOG_VECTOR) { /* 0x1020 mapped to 0x14 by ppc_get_vector_addr */
bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_WDOG, dflt_entry.hdl);
return 0;
} else
} else
return -1; /* unhandled interrupt, panic time */
}
c/src/lib/libbsp/powerpc/haleakala/irq/irq.h
+6 -6
View File
@@ -23,7 +23,7 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode.
These are arbitrary but it makes things easier if they match the CPU interrupt numbers */
@@ -103,7 +103,7 @@ extern "C" {
#define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7)
#define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8)
#define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9)
#define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16)
#define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17)
#define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18)
@@ -127,7 +127,7 @@ extern "C" {
#define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2)
#define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3)
#define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4)
#define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30)
#define BSP_UIC_IRQ_NUMBER (95)
@@ -143,7 +143,7 @@ extern "C" {
#define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */
#define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1
#define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
#define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
#define BSP_PROCESSOR_IRQ_NUMBER (3)
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1)
@@ -154,10 +154,10 @@ extern "C" {
#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
#define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET)
#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1)
extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c
#include <bsp/irq_supp.h>
#ifdef __cplusplus
}
#endif
c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c
+3 -3
View File
@@ -57,7 +57,7 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
void BSP_rtems_irq_mng_init(unsigned cpuId)
{
int i;
/*
* re-init the rtemsIrq table
*/
@@ -82,8 +82,8 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
"Unable to initialize RTEMS interrupt management!!! System locked\n"
);
}
#ifdef TRACE_IRQ_INIT
#ifdef TRACE_IRQ_INIT
printk("RTEMS IRQ management is now operational\n");
#endif
}
c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c
+4 -4
View File
@@ -182,8 +182,8 @@ void bsp_start( void )
EarlyUARTInit(115200);
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables
* so that it can be used later...
*/
myCpu = get_ppc_cpu_type();
@@ -200,9 +200,9 @@ void bsp_start( void )
bsp_timer_internal_clock = TRUE;
bsp_timer_average_overhead = 2;
bsp_timer_least_valid = 3;
/*
* Initialize default raw exception handlers.
* Initialize default raw exception handlers.
*/
sc = ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h
+5 -5
View File
@@ -43,11 +43,11 @@
* NOTE: VME addresses should NEVER be translated using these constants!
* they are strictly for BSP internal use. Drivers etc. should use
* the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
*
*
* CPU ADDR PCI_ADDR VME ADDR
*
*
* 00000000 XXXXXXXX XXXXXXXX
* ^ ^ ........
* ^ ^ ........
* | |
* | | e.g., RAM XXXXXXXX
* | | 00000000
@@ -70,7 +70,7 @@
* VME devices hostbridge mapped by
* visible here universe
* =====================================================
*
*
*/
/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
@@ -82,7 +82,7 @@
/* offset of pci memory as seen from the CPU */
#define PCI_MEM_BASE 0
/* where (in CPU addr. space) does the PCI window start */
#define PCI_MEM_WIN0 0x80000000
#define PCI_MEM_WIN0 0x80000000
#else
#define _IO_BASE PREP_ISA_IO_BASE
c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c
+8 -8
View File
@@ -81,25 +81,25 @@ static void mpc55xx_clock_initialize( void)
}
/* Configure eMIOS channel */
/* Set channel in GPIO mode */
ccr.B.MODE = MPC55XX_EMIOS_MODE_GPIO_INPUT;
regs->CCR.R = ccr.R;
/* Clear status flags */
csr.B.OVR = 1;
csr.B.OVFL = 1;
csr.B.FLAG = 1;
regs->CSR.R = csr.R;
/* Set timer period */
regs->CADR.R = (uint32_t) interval - 1;
/* Set unused registers */
regs->CBDR.R = 0;
regs->CCNTR.R = 0;
regs->ALTCADR.R = 0;
/* Set control register */
ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
ccr.B.UCPREN = 1;
@@ -132,17 +132,17 @@ static uint32_t mpc55xx_clock_nanoseconds_since_last_tick( void)
uint64_t clicks = EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CCNTR.R;
uint64_t clock = bsp_clock_speed;
uint64_t ns = (clicks * 1000000000) / clock;
return (uint32_t) ns;
}
#define Clock_driver_support_initialize_hardware() mpc55xx_clock_initialize()
#define Clock_driver_support_install_isr( isr, old_isr) \
mpc55xx_clock_handler_install()
#define Clock_driver_support_shutdown_hardware() mpc55xx_clock_cleanup()
#define Clock_driver_nanoseconds_since_last_tick \
mpc55xx_clock_nanoseconds_since_last_tick
c/src/lib/libbsp/powerpc/mpc55xxevb/include/smsc9218i.h
+50 -50
View File
@@ -21,7 +21,7 @@
/**
* @name Memory Map
* @{
* @{
*/
typedef struct {
@@ -95,7 +95,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Receive Status
* @{
* @{
*/
#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
@@ -117,7 +117,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Transmit Status
* @{
* @{
*/
#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
@@ -133,7 +133,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Transmit Command A
* @{
* @{
*/
#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
@@ -149,7 +149,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Transmit Command B
* @{
* @{
*/
#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
@@ -162,7 +162,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Chip ID and Revision
* @{
* @{
*/
#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
@@ -174,7 +174,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Interrupt Configuration
* @{
* @{
*/
#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
@@ -190,7 +190,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Interrupt Status
* @{
* @{
*/
#define SMSC9218I_INT_STS_SW SMSC9218I_FLAG(31)
@@ -220,7 +220,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Interrupt Enable
* @{
* @{
*/
#define SMSC9218I_INT_EN_SW SMSC9218I_FLAG(31)
@@ -250,7 +250,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Byte Order Testing
* @{
* @{
*/
#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
@@ -259,7 +259,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name FIFO Level Interrupts
* @{
* @{
*/
#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
@@ -273,7 +273,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Receive Configuration
* @{
* @{
*/
#define SMSC9218I_RX_CFG_END_ALIGN_4 0
@@ -289,7 +289,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Transmit Configuration
* @{
* @{
*/
#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
@@ -302,7 +302,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Hardware Configuration
* @{
* @{
*/
#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
@@ -317,7 +317,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Receive Datapath Control
* @{
* @{
*/
#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
@@ -326,7 +326,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Receive FIFO Information
* @{
* @{
*/
#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
@@ -336,7 +336,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Transmit FIFO Information
* @{
* @{
*/
#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
@@ -346,7 +346,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Power Management Control
* @{
* @{
*/
#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
@@ -368,7 +368,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name General Purpose IO Configuration
* @{
* @{
*/
#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
@@ -393,7 +393,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name General Purpose Timer Configuration
* @{
* @{
*/
#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
@@ -404,7 +404,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name General Purpose Timer Count
* @{
* @{
*/
#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
@@ -413,7 +413,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Word Swap
* @{
* @{
*/
#define SMSC9218I_ENDIAN_BIG 0xffffffffU
@@ -422,7 +422,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Free Run Counter
* @{
* @{
*/
#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
@@ -431,7 +431,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Receiver Dropped Frames Counter
* @{
* @{
*/
#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
@@ -440,7 +440,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name MAC Control and Status Synchronizer Command
* @{
* @{
*/
#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
@@ -452,7 +452,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name MAC Control Register
* @{
* @{
*/
#define SMSC9218I_MAC_CR 0x00000001U
@@ -484,7 +484,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name MAC Address High
* @{
* @{
*/
#define SMSC9218I_MAC_ADDRH 0x00000002U
@@ -494,7 +494,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name MAC Address Low
* @{
* @{
*/
#define SMSC9218I_MAC_ADDRL 0x00000003U
@@ -504,7 +504,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Multicast Hash Table High
* @{
* @{
*/
#define SMSC9218I_MAC_HASHH 0x00000004U
@@ -514,7 +514,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Multicast Hash Table Low
* @{
* @{
*/
#define SMSC9218I_MAC_HASHL 0x00000005U
@@ -524,7 +524,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name MII Access
* @{
* @{
*/
#define SMSC9218I_MAC_MII_ACC 0x00000006U
@@ -537,7 +537,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name MII Data
* @{
* @{
*/
#define SMSC9218I_MAC_MII_DATA 0x00000007U
@@ -546,7 +546,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Flow Control
* @{
* @{
*/
#define SMSC9218I_MAC_FLOW 0x00000008U
@@ -559,7 +559,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name VLAN1 Tag
* @{
* @{
*/
#define SMSC9218I_MAC_VLAN1 0x00000009U
@@ -568,7 +568,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name VLAN2 Tag
* @{
* @{
*/
#define SMSC9218I_MAC_VLAN2 0x0000000aU
@@ -577,7 +577,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Wake-up Frame Filter
* @{
* @{
*/
#define SMSC9218I_MAC_WUFF 0x0000000bU
@@ -586,7 +586,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Wake-up Control and Status
* @{
* @{
*/
#define SMSC9218I_MAC_WUCSR 0x0000000cU
@@ -600,7 +600,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Basic Control
* @{
* @{
*/
#define SMSC9218I_PHY_BCR 0x00000000U
@@ -617,7 +617,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Basic Status
* @{
* @{
*/
#define SMSC9218I_PHY_BSR 0x00000001U
@@ -637,7 +637,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name PHY Identifier 1
* @{
* @{
*/
#define SMSC9218I_PHY_ID1 0x00000002U
@@ -649,7 +649,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name PHY Identifier 2
* @{
* @{
*/
#define SMSC9218I_PHY_ID2 0x00000003U
@@ -663,7 +663,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Auto-negotiation Advertisment
* @{
* @{
*/
#define SMSC9218I_PHY_ANAR 0x00000004U
@@ -684,7 +684,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Auto-negotiation Link Partner Ability
* @{
* @{
*/
#define SMSC9218I_PHY_ANLPAR 0x00000005U
@@ -702,7 +702,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Auto-negotiation Expansion
* @{
* @{
*/
#define SMSC9218I_PHY_ANEXPR 0x00000006U
@@ -716,7 +716,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Mode Control and Status
* @{
* @{
*/
#define SMSC9218I_PHY_MCSR 0x00000011U
@@ -727,7 +727,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Special Modes
* @{
* @{
*/
#define SMSC9218I_PHY_SPMODES 0x00000012U
@@ -736,7 +736,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Special Control and Status Indications
* @{
* @{
*/
#define SMSC9218I_PHY_CSIR 0x0000001bU
@@ -748,7 +748,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Interrupt Source Flag
* @{
* @{
*/
#define SMSC9218I_PHY_ISR 0x0000001dU
@@ -764,7 +764,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name Interrupt Mask
* @{
* @{
*/
#define SMSC9218I_PHY_IMR 0x0000001eU
@@ -780,7 +780,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
/**
* @name PHY Special Control and Status
* @{
* @{
*/
#define SMSC9218I_PHY_PHYSCSR 0x0000001fU
c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
+8 -8
View File
@@ -581,7 +581,7 @@ static void smsc9218i_receive_task(void *arg)
/* Wait for events */
sc = rtems_bsdnet_event_receive(
SMSC9218I_EVENT_RX | SMSC9218I_EVENT_PHY,
SMSC9218I_EVENT_RX | SMSC9218I_EVENT_PHY,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events
@@ -650,7 +650,7 @@ static void smsc9218i_receive_task(void *arg)
/* Wait for eDMA events */
sc = rtems_bsdnet_event_receive(
SMSC9218I_EVENT_EDMA | SMSC9218I_EVENT_EDMA_ERROR,
SMSC9218I_EVENT_EDMA | SMSC9218I_EVENT_EDMA_ERROR,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events
@@ -870,7 +870,7 @@ static struct mbuf *smsc9218i_next_transmit_fragment(
jc->done = true;
SMSC9218I_PRINTF("tx: inactive\n");
}
}
}
return m;
@@ -1222,7 +1222,7 @@ static void smsc9218i_transmit_task(void *arg)
SMSC9218I_EVENT_TX
| SMSC9218I_EVENT_TX_START
| SMSC9218I_EVENT_EDMA
| SMSC9218I_EVENT_EDMA_ERROR,
| SMSC9218I_EVENT_EDMA_ERROR,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events
@@ -1471,8 +1471,8 @@ static void smsc9218i_interface_init(void *arg)
/* Start receive task */
if (e->receive_task == RTEMS_ID_NONE) {
e->receive_task = rtems_bsdnet_newproc(
"ntrx",
4096,
"ntrx",
4096,
smsc9218i_receive_task,
e
);
@@ -1481,8 +1481,8 @@ static void smsc9218i_interface_init(void *arg)
/* Start transmit task */
if (e->transmit_task == RTEMS_ID_NONE) {
e->transmit_task = rtems_bsdnet_newproc(
"nttx",
4096,
"nttx",
4096,
smsc9218i_transmit_task,
e
);
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspgetworkarea.c
+1 -1
View File
@@ -39,7 +39,7 @@ void bsp_get_work_area(
)
{
*work_area_start = bsp_section_bss_end;
*work_area_size = bsp_ram_end - 2 *
*work_area_size = bsp_ram_end - 2 *
MPC55XX_INTERRUPT_STACK_SIZE - bsp_section_bss_end;
*heap_start = bsp_external_ram_start;
*heap_size = (uintptr_t) bsp_external_ram_size;
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
+4 -4
View File
@@ -208,7 +208,7 @@ void bsp_start(void)
RTEMS_DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start);
RTEMS_DEBUG_PRINT( "Interrupt stack end : 0x%08x\n", interrupt_stack_start + interrupt_stack_size);
RTEMS_DEBUG_PRINT( "Interrupt stack size : 0x%08x\n", interrupt_stack_size);
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used
@@ -216,13 +216,13 @@ void bsp_start(void)
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/* Time reference value */
bsp_clicks_per_usec = bsp_clock_speed / 1000000;
/* Initialize External Bus Interface */
mpc55xx_ebi_init();
/* Initialize exceptions */
RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n");
sc = ppc_exc_initialize(
@@ -244,7 +244,7 @@ void bsp_start(void)
} else {
DEBUG_DONE();
}
/* Initialize eMIOS */
mpc55xx_emios_initialize( 1);
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
+7 -7
View File
@@ -22,17 +22,17 @@
#warning The call is "void boot_card(const char* cmdline);"
#warning You need to pass a NULL.
#warning Please check and remove these warnings.
/**
* @defgroup mpc55xx_asm Assembler files
*
* @ingroup mpc55xx
*/
#include <libcpu/powerpc-utility.h>
#include <mpc55xx/reg-defs.h>
.section ".entry", "ax"
.section ".entry", "ax"
PUBLIC_VAR (start)
start:
/*
@@ -214,7 +214,7 @@ start:
/* Clear command line */
xor r3, r3, r3
/* Start RTEMS */
bl SYM (boot_card)
@@ -260,7 +260,7 @@ no_chache_invalidation_abort:
/* Wait? */
bne check_cache_invalidation
/* Enable cache */
LWI r6, L1CSR0_SETTINGS
mfspr r5, L1CSR0
@@ -270,7 +270,7 @@ no_chache_invalidation_abort:
mtspr L1CSR0, r5
/* Return */
blr
blr
twiddle:
twiddle:
b twiddle
c/src/lib/libbsp/powerpc/mpc55xxevb/tests/tests.c
+7 -7
View File
@@ -95,7 +95,7 @@ static rtems_task test_mpc55xx_dspi_writer( rtems_task_argument arg)
sc = rtems_libi2c_send_addr( device, MPC55XX_TEST_DSPI_ADDRESS);
RTEMS_CHECK_SC_TASK( sc, "rtems_libi2c_send_addr");
for (i = 0; i < MPC55XX_TEST_DSPI_BUFSIZE; ++i) {
test_mpc55xx_dspi_writer_outbuf [0] [i] = 0xa5;
test_mpc55xx_dspi_writer_outbuf [1] [i] = 0xa5;
@@ -164,7 +164,7 @@ static rtems_task test_mpc55xx_dspi_reader( rtems_task_argument arg)
sc = rtems_libi2c_send_addr( device, MPC55XX_TEST_DSPI_ADDRESS);
RTEMS_CHECK_SC_TASK( sc, "rtems_libi2c_send_addr");
for (i = 0; i < MPC55XX_TEST_DSPI_BUFSIZE; ++i) {
test_mpc55xx_dspi_reader_inbuf [i] = -1;
}
@@ -182,7 +182,7 @@ static rtems_task test_mpc55xx_dspi_reader( rtems_task_argument arg)
RTEMS_CHECK_SC_TASK( sc, "rtems_semaphore_obtain");
RTEMS_DEBUG_PRINT( "Pong\n");
rv = rtems_libi2c_read_bytes( device, test_mpc55xx_dspi_reader_inbuf, MPC55XX_TEST_DSPI_BUFSIZE);
RTEMS_CHECK_RV_TASK( rv, "rtems_libi2c_read_bytes");
@@ -287,7 +287,7 @@ rtems_status_code mpc55xx_dspi_register(void)
#if 0
rtems_id writer_task_id;
rtems_id reader_task_id;
sc = rtems_task_create(
rtems_build_name( 'T', 'W', 'R', 'T'),
2,
@@ -306,7 +306,7 @@ rtems_status_code mpc55xx_dspi_register(void)
&reader_task_id
);
RTEMS_CHECK_SC( sc, "rtems_task_create");
sc = rtems_task_start( writer_task_id, test_mpc55xx_dspi_writer, 0);
RTEMS_CHECK_SC( sc, "rtems_task_start");
sc = rtems_task_start( reader_task_id, test_mpc55xx_dspi_reader, 0);
@@ -506,7 +506,7 @@ rtems_task test_sd_card( rtems_task_argument arg)
int b = 0;
const char device_name [] = "/dev/spi0.sd-card-0";
fd = open( device_name, O_RDWR);
RTEMS_CHECK_RV_TASK( fd, "open");
while (1) {
for (i = 0; i < TEST_SD_CARD_BUF_SIZE; ++i) {
@@ -520,7 +520,7 @@ rtems_task test_sd_card( rtems_task_argument arg)
}
rv = close( fd);
RTEMS_CHECK_RV_TASK( rv, "close");
/* Read */
fd = open( device_name, O_RDWR);
RTEMS_CHECK_RV_TASK( fd, "open");
c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c
+16 -16
View File
@@ -192,18 +192,18 @@ int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine)
return 0;
}
int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)
{
int cpm_irq_index;
if (!is_cpm_irq(irqLine))
return 0;
cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
(m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)
{
int cpm_irq_index;
if (!is_cpm_irq(irqLine))
return 0;
cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
(m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
}
#ifdef DISPATCH_HANDLER_STAT
@@ -274,8 +274,8 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum)
m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
/*
* make sure, that the masking operations in
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
@@ -291,8 +291,8 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum)
/* disable exceptions again */
_CPU_MSR_SET(msr);
/*
* make sure, that the masking operations in
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
c/src/lib/libbsp/powerpc/mvme3100/flash/flashcfg.c
+9 -9
View File
@@ -2,20 +2,20 @@
/* BSP-specific bits of flash programmer support */
/*
/*
* Authorship
* ----------
* This software ('mvme3100' RTEMS BSP) was created by
*
* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* The 'mvme3100' BSP was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -24,18 +24,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -44,9 +44,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
#include <rtems.h>
#include <bsp.h>
#include <libcpu/spr.h>
c/src/lib/libbsp/powerpc/mvme3100/i2c/i2c_init.c
+10 -10
View File
@@ -2,20 +2,20 @@
/* Register i2c bus driver & devices */
/*
/*
* Authorship
* ----------
* This software ('mvme3100' RTEMS BSP) was created by
*
* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* The 'mvme3100' BSP was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -24,18 +24,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -44,9 +44,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
#include <rtems.h>
#include <bsp.h>
@@ -92,7 +92,7 @@ int busno, succ = 0;
safe_printf("Initializing I2C library failed\n");
return -1;
}
/* Register our bus driver */
if ( (busno=rtems_libi2c_register_bus(
BSP_I2C_BUS0_NAME,
c/src/lib/libbsp/powerpc/mvme3100/i2c/mpc8540_i2c.c
+12 -12
View File
@@ -1,19 +1,19 @@
/* I2C bus driver for mpc8540-based boards */
/*
/*
* Authorship
* ----------
* This software ('mvme3100' RTEMS BSP) was created by
*
* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* The 'mvme3100' BSP was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -22,18 +22,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -42,9 +42,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
/* Note: We maintain base address, IRQ etc. statically and
* globally. We don't bother creating driver-specific
@@ -64,7 +64,7 @@
#include "mpc8540_i2c_busdrv.h"
#define STATIC
#define STATIC
/* I2C controller register definitions */
#define I2CADR 0x3000
@@ -205,7 +205,7 @@ i2c_xfer(int rw, uint8_t *buf, int len)
{
int i;
rtems_status_code sc;
if ( rw ) {
i2c_clr( I2CCR, I2CCR_MTX );
} else {
@@ -233,7 +233,7 @@ rtems_status_code sc;
return i;
}
/*
/*
* This bus controller gives us lagging data, i.e.,
* when we read a byte from the data reg then that
* issues a read cycle on the bus and gives us the
c/src/lib/libbsp/powerpc/mvme3100/i2c/mpc8540_i2c_busdrv.h
+9 -9
View File
@@ -1,20 +1,20 @@
#ifndef MPC8540_I2C_BUS_DRIVER_H
#define MPC8540_I2C_BUS_DRIVER_H
/*
/*
* Authorship
* ----------
* This software ('mvme3100' RTEMS BSP) was created by
*
* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* The 'mvme3100' BSP was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -23,18 +23,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -43,9 +43,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
#ifdef __cplusplus
extern "C" {
c/src/lib/libbsp/powerpc/mvme3100/include/bsp.h
+12 -12
View File
@@ -26,7 +26,7 @@
* confdefs.h overrides for this BSP:
*/
#define CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK
#define BSP_INTERRUPT_STACK_SIZE (16 * 1024)
/*
@@ -47,11 +47,11 @@
* NOTE: VME addresses should NEVER be translated using these constants!
* they are strictly for BSP internal use. Drivers etc. should use
* the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
*
*
* CPU ADDR PCI_ADDR VME ADDR
*
*
* 00000000 XXXXXXXX XXXXXXXX
* ^ ^ ........
* ^ ^ ........
* | |
* | | e.g., RAM XXXXXXXX
* | | 00000000
@@ -74,18 +74,18 @@
* VME devices hostbridge mapped by
* visible here universe
* =====================================================
*
*
*/
/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
#define _IO_BASE 0xe0000000 /* Motload's PCI IO base */
#define _IO_BASE 0xe0000000 /* Motload's PCI IO base */
#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
/* offset of pci memory as seen from the CPU */
#define PCI_MEM_BASE 0
/* where (in CPU addr. space) does the PCI window start */
#define PCI_MEM_WIN0 0x80000000
#define PCI_MEM_WIN0 0x80000000
/*
* Base address definitions for several devices
@@ -117,7 +117,7 @@
#define BSP_USR1_I2C_ADDR (0xA6>>1) /* the 2nd user EEPROM */
#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */
#define BSP_RTC_I2C_ADDR (0xD0>>1) /* the DS1375 wall-clock */
#define BSP_I2C_BUS_DESCRIPTOR mpc8540_i2c_bus_descriptor
#define BSP_I2C_BUS0_NAME "/dev/i2c0"
@@ -152,7 +152,7 @@
#ifdef __cplusplus
extern "C" {
#endif
/* Initialize the I2C driver and register all devices
/* Initialize the I2C driver and register all devices
* RETURNS 0 on success, -1 on error.
*
* Access to the VPD and user EEPROMS as well
@@ -165,15 +165,15 @@ extern "C" {
* /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC)
* /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621)
* /dev/i2c0.ds1375-raw (read-write; transfer bytes to/from the ds1375)
*
*
*/
int
BSP_i2c_initialize();
/* System Control Register */
#define BSP_MVME3100_SYS_CR ((volatile uint8_t *)0xe2000001)
#define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5)
#define BSP_MVME3100_SYS_CR_RESET (5<<5)
#define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5)
#define BSP_MVME3100_SYS_CR_RESET (5<<5)
#define BSP_MVME3100_SYS_CR_EEPROM_WP (1<<1)
#define BSP_MVME3100_SYS_CR_TSTAT_MSK (1<<0)
c/src/lib/libbsp/powerpc/mvme3100/irq/irq.h
+1 -1
View File
@@ -97,7 +97,7 @@ extern "C" {
#define BSP_UART_COM2_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26)
#define BSP_I2C_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 27)
/*
/*
* Some internal (CORE) name definitions
*/
/* Ethernet (FEC) */
c/src/lib/libbsp/powerpc/mvme3100/irq/irq_init.c
+2 -2
View File
@@ -73,7 +73,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
unsigned char pol[56];
int i;
/* Note: The openpic driver initializes only as many
/* Note: The openpic driver initializes only as many
* 'pic-external' interrupt sources as reported
* by the feature register.
* The 8540's openpic supports 12 core-external
@@ -103,7 +103,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
* to 'low/0' will disable the interrupt but
* I found this not to be true: on the device
* I tested the interrupt was asserted hard.
*/
*/
/* core-external sources on the mvme3100 are active-low,
* core-internal sources are active high.

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