Mirrors_Framework/rtems
1
0
Fork 0
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2026-09-25 06:04:17 +08:00
Code Issues Packages Projects Releases Wiki Activity

or1k: Remove secondary functions in cache manager

Browse Source 
Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the
equivalent exported _CPU_cache_{enable,disable}_* functions instead, and
then delete them, in order to reduce the code indirection and aid
readability.

This does not touch the currently unused prefetch, writeback, and lock
functions.
This commit is contained in:
Martin Erik Werner
2016-11-28 07:30:44 +01:00
committed by Sebastian Huber
parent 3b4ddafe99
commit a59dd5cc6f
1 changed files with 34 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libcpu/or1k/shared/cache/cache.c
Vendored
+34 -56
View File
@@ -21,58 +21,6 @@
#include <libcpu/cache.h>
#include <cache_.h>
static inline void _CPU_OR1K_Cache_enable_data(void)
{
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_disable_data(void)
{
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_enable_instruction(void)
{
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_disable_instruction(void)
{
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
_ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
{
ISR_Level level;
@@ -344,22 +292,52 @@ void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
void _CPU_cache_enable_data(void)
{
_CPU_OR1K_Cache_enable_data();
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
_ISR_Local_enable(level);
}
void _CPU_cache_disable_data(void)
{
_CPU_OR1K_Cache_disable_data();
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
_ISR_Local_enable(level);
}
void _CPU_cache_enable_instruction(void)
{
uint32_t sr;
ISR_Level level;
_CPU_OR1K_Cache_enable_instruction();
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
_ISR_Local_enable(level);
}
void _CPU_cache_disable_instruction(void)
{
_CPU_OR1K_Cache_disable_instruction();
uint32_t sr;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
_ISR_Local_enable(level);
}