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new files submitted by Craig Lebakken (lebakken@minn.net) and Derrick Ostertag

Browse Source 
(ostertag@transition.com).
This commit is contained in:
Joel Sherrill
1996-09-18 20:45:27 +00:00
parent 5961dbab25
commit a4d97d942b
14 changed files with 4334 additions and 0 deletions
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c/src/exec/score/cpu/a29k/a29k.h
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/* a29k.h
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*
*/
/* @(#)a29k.h 09/12/96 1.2 */
#ifndef _INCLUDE_A29K_h
#define _INCLUDE_A29K_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* The following define the CPU Family and Model within the family
*
* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
* with the name of the appropriate macro for this target CPU.
*/
#ifdef a29k
#undef a29k
#endif
#define a29k
#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
#undef REPLACE_THIS_WITH_THE_CPU_MODEL
#endif
#define REPLACE_THIS_WITH_THE_CPU_MODEL
#ifdef REPLACE_THIS_WITH_THE_BSP
#undef REPLACE_THIS_WITH_THE_BSP
#endif
#define REPLACE_THIS_WITH_THE_BSP
/*
* This file contains the information required to build
* RTEMS for a particular member of the "no cpu"
* family when executing in protected mode. It does
* this by setting variables to indicate which implementation
* dependent features are present in a particular member
* of the family.
*/
#if defined(a29205)
#define CPU_MODEL_NAME "a29205"
#define A29K_HAS_FPU 0
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "AMD 29K"
#ifdef __cplusplus
}
#endif
#endif /* ! _INCLUDE_A29K_h */
/* end of include file */
c/src/exec/score/cpu/a29k/a29ktypes.h
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/* no_cputypes.h
*
* This include file contains type definitions pertaining to the Intel
* no_cpu processor family.
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*/
#ifndef __NO_CPU_TYPES_h
#define __NO_CPU_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void no_cpu_isr;
typedef void ( *no_cpu_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */
c/src/exec/score/cpu/a29k/amd.ah
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c/src/exec/score/cpu/a29k/asm.h
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/* asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
* COPYRIGHT (c) 1994.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#ifndef __NO_CPU_ASM_h
#define __NO_CPU_ASM_h
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#define ASM
#include <rtems/score/no_cpu.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .globl SYM (sym)
#define EXTERN(sym) .globl SYM (sym)
#endif
/* end of include file */
c/src/exec/score/cpu/a29k/cpu.c
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/*
* AMD 29K CPU Dependent Source
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*/
#ifndef lint
static char _sccsid[] = "@(#)cpu.c 21 Aug 1996 1.6\n";
#endif
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <rtems/score/thread.h>
#include <stdio.h>
#include <stdlib.h>
void a29k_ISR_Handler(unsigned32 vector);
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS:
* cpu_table - CPU table to initialize
* thread_dispatch - address of disptaching routine
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)() /* ignored on this CPU */
)
{
unsigned int i;
/*
* The thread_dispatch argument is the address of the entry point
* for the routine called at the end of an ISR once it has been
* decided a context switch is necessary. On some compilation
* systems it is difficult to call a high-level language routine
* from assembly. This allows us to trick these systems.
*
* If you encounter this problem save the entry point in a CPU
* dependent variable.
*/
_CPU_Thread_dispatch_pointer = thread_dispatch;
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
_CPU_Table = *cpu_table;
for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
{
_ISR_Vector_table[i] = (proc_ptr)NULL;
}
}
/*PAGE
*
* _CPU_ISR_Get_level
*/
unsigned32 _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
*/
return 0;
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*/
extern void intr14( void );
extern void intr3( void );
extern void intr2( void );
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/*
* This is where we install the interrupt handler into the "raw" interrupt
* table used by the CPU to dispatch interrupt handlers.
*/
switch( vector )
{
case 14:
_settrap( vector, intr14 );
break;
case 3:
_settrap( vector, intr3 );
break;
case 2:
_settrap( vector, intr2 );
break;
default:
break;
}
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* If the interrupt vector table is a table of pointer to isr entry
* points, then we need to install the appropriate RTEMS interrupt
* handler for this vector number.
*/
_CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
/*
* We put the actual user ISR address in '_ISR_vector_table'. This will
* be used by the _ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
/*PAGE
*
* _CPU_Install_interrupt_stack
*/
void _CPU_Install_interrupt_stack( void )
{
}
/*PAGE
*
* _CPU_Internal_threads_Idle_thread_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*/
void _CPU_Internal_threads_Idle_thread_body( void )
{
for( ; ; )
{
}
/* insert your "halt" instruction here */ ;
}
void a29k_fatal_error( unsigned32 error )
{
printf("\n\nfatal error %d, rebooting!!!\n",error );
exit(error);
}
/*
* This discussion ignores a lot of the ugly details in a real
* implementation such as saving enough registers/state to be
* able to do something real. Keep in mind that the goal is
* to invoke a user's ISR handler which is written in C and
* uses a certain set of registers.
*
* Also note that the exact order is to a large extent flexible.
* Hardware will dictate a sequence for a certain subset of
* _ISR_Handler while requirements for setting
*/
/*
* At entry to "common" _ISR_Handler, the vector number must be
* available. On some CPUs the hardware puts either the vector
* number or the offset into the vector table for this ISR in a
* known place. If the hardware does not give us this information,
* then the assembly portion of RTEMS for this port will contain
* a set of distinct interrupt entry points which somehow place
* the vector number in a known place (which is safe if another
* interrupt nests this one) and branches to _ISR_Handler.
*
*/
void a29k_ISR_Handler(unsigned32 vector)
{
_ISR_Nest_level++;
_Thread_Dispatch_disable_level++;
if ( _ISR_Vector_table[ vector ] )
(*_ISR_Vector_table[ vector ])( vector );
--_Thread_Dispatch_disable_level;
--_ISR_Nest_level;
if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level &&
(_Context_Switch_necessary || _ISR_Signals_to_thread_executing ))
_Thread_Dispatch();
return;
}
c/src/exec/score/cpu/a29k/cpu.h
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c/src/exec/score/cpu/a29k/cpu_asm.h
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/*
* cpu_asm.h
*
* Very loose template for an include file for the cpu_asm.? file
* if it is implemented as a ".S" file (preprocessed by cpp) instead
* of a ".s" file (preprocessed by gm4 or gasp).
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*
*/
/* @(#)cpu_asm.h 06/08/96 1.2 */
#ifndef __CPU_ASM_h
#define __CPU_ASM_h
/* pull in the generated offsets */
/* #include <rtems/score/offsets.h> */
/*
* Hardware General Registers
*/
/* put something here */
/*
* Hardware Floating Point Registers
*/
/* put something here */
/*
* Hardware Control Registers
*/
/* put something here */
/*
* Calling Convention
*/
/* put something here */
/*
* Temporary registers
*/
/* put something here */
/*
* Floating Point Registers - SW Conventions
*/
/* put something here */
/*
* Temporary floating point registers
*/
/* put something here */
#endif
/* end of file */
c/src/exec/score/cpu/a29k/cpu_asm.s
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;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
; *
; * Author: Craig Lebakken <craigl@transition.com>
; *
; * COPYRIGHT (c) 1996 by Transition Networks Inc.
; *
; * To anyone who acknowledges that this file is provided "AS IS"
; * without any express or implied warranty:
; * permission to use, copy, modify, and distribute this file
; * for any purpose is hereby granted without fee, provided that
; * the above copyright notice and this notice appears in all
; * copies, and that the name of Transition Networks not be used in
; * advertising or publicity pertaining to distribution of the
; * software without specific, written prior permission.
; * Transition Networks makes no representations about the suitability
; * of this software for any purpose.
; *
; *
; * This file contains the basic algorithms for all assembly code used
; * in an specific CPU port of RTEMS. These algorithms must be implemented
; * in assembly language
; *
; * NOTE: This is supposed to be a .S or .s file NOT a C file.
; *
; * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
; * On-Line Applications Research Corporation (OAR).
; * All rights assigned to U.S. Government, 1994.
; *
; * This material may be reproduced by or for the U.S. Government pursuant
; * to the copyright license under the clause at DFARS 252.227-7013. This
; * notice must appear in all copies of this file and its derivatives.
; *
; * $Id$
; */
;/*
; * This is supposed to be an assembly file. This means that system.h
; * and cpu.h should not be included in a "real" cpu_asm file. An
; * implementation in assembly should include "cpu_asm.h>
; */
;#include <cpu_asm.h>
.include "register.ah"
.include "amd.ah"
.include "pswmacro.ah"
; .extern _bsp_exit
;
; push a register onto the struct
.macro spush, sp, reg
store 0, 0, reg, sp ; push register
add sp, sp, 4 ; adjust stack pointer
.endm
; push a register onto the struct
.macro spushsr, sp, reg, sr
mfsr reg, sr
store 0, 0, reg, sp ; push register
add sp, sp, 4 ; adjust stack pointer
.endm
; pop a register from the struct
.macro spop, reg, sp
load 0, 0, reg, sp
add sp,sp,4
.endm
; pop a special register from the struct
.macro spopsr, sreg, reg, sp
load 0, 0, reg, sp
mtsr sreg, reg
add sp,sp,4
.endm
;
;/*
; * _CPU_Context_save_fp_context
; *
; * This routine is responsible for saving the FP context
; * at *fp_context_ptr. If the point to load the FP context
; * from is changed then the pointer is modified by this routine.
; *
; * Sometimes a macro implementation of this is in cpu.h which dereferences
; * the ** and a similarly named routine in this file is passed something
; * like a (Context_Control_fp *). The general rule on making this decision
; * is to avoid writing assembly language.
; */
;#if 0
;void _CPU_Context_save_fp(
; void **fp_context_ptr
;)
;{
;}
;#endif
.global _CPU_Context_save_fp
_CPU_Context_save_fp:
jmpi lr0
nop
;/*
; * _CPU_Context_restore_fp_context
; *
; * This routine is responsible for restoring the FP context
; * at *fp_context_ptr. If the point to load the FP context
; * from is changed then the pointer is modified by this routine.
; *
; * Sometimes a macro implementation of this is in cpu.h which dereferences
; * the ** and a similarly named routine in this file is passed something
; * like a (Context_Control_fp *). The general rule on making this decision
; * is to avoid writing assembly language.
; */
;#if 0
;void _CPU_Context_restore_fp(
; void **fp_context_ptr
;)
;{
;}
;#endif
.global __CPU_Context_restore_fp
__CPU_Context_restore_fp:
jmpi lr0
nop
;/* _CPU_Context_switch
; *
; * This routine performs a normal non-FP context switch.
; */
;#if 0
;void _CPU_Context_switch(
; Context_Control *run,
; Context_Control *heir
;)
;{
;}
;#endif
.global __CPU_Context_switch
__CPU_Context_switch:
asneq 106, gr1, gr1 ; syscall
jmpi lr0 ;
nop ;
.global _a29k_context_switch_sup
_a29k_context_switch_sup:
add pcb,lr2,0
add kt1,lr3,0 ;move heir pointer to safe location
constn it0,SIG_SYNC
spush pcb,it0
spush pcb,gr1
spush pcb,rab ;push rab
spushsr pcb,it0,pc0 ;push specials
spushsr pcb,it0,pc1
add pcb,pcb,1*4 ;space pc2
spushsr pcb,it0,CHA ;push CHA
spushsr pcb,it0,CHD ;push CHD
spushsr pcb,it0,CHC ;push CHC
add pcb,pcb,1*4 ;space for alu
spushsr pcb,it0,ops ;push OPS
mfsr kt0,cps ;current status
const it1,FZ ;FZ constant
andn it1,kt0,it1 ;clear FZ bit
mtsr cps,it1 ;cps without FZ
add pcb,pcb,1*4 ;space for tav
mtsrim chc,0 ;possible DERR
;
spush pcb,lr1 ;push R-stack
spush pcb,rfb ; support
spush pcb,msp ;push M-stack pnt.
;
add pcb,pcb,3*4 ;space for floating point
; spush pcb,FPStat0 ;floating point
; spush pcb,FPStat1
; spush pcb,FPStat2
;
add pcb,pcb,4*4 ;space for IPA..Q
;
mtsrim cr,29-1
storem 0,0,gr96,pcb ;push gr96-124, optional
add pcb,pcb,29*4 ;space for gr96-124
;
sub it0,rfb,gr1 ;get bytes in cache
srl it0,it0,2 ;adjust to words
sub it0,it0,1
spush pcb,it0
mtsr cr,it0
storem 0,0,lr0,pcb ;save lr0-rfb
;
context_restore:
add pcb,kt1,0 ;pcb=heir
add pcb,pcb,4 ;space for signal num
spop gr1,pcb ;restore freeze registers
add gr1,gr1,0 ;alu op
add pcb,pcb,9*4 ;move past freeze registers
add pcb,pcb,1*4 ;space for tav
spop lr1,pcb
spop rfb,pcb
spop msp,pcb
; spop FPStat0,pcb
; spop FPStat1,pcb
; spop FPStat2,pcb
add pcb,pcb,3*4 ;space for floating point
add pcb,pcb,4*4 ;space for IPA..Q
mtsrim cr,29-1
loadm 0,0,gr96,pcb ;pop gr96-gr124
add pcb,pcb,29*4 ;space for gr96-124
spop it1,pcb ;pop locals count
mtsr cr,it1
loadm 0,0,lr0,pcb ;load locals
add pcb,kt1,0 ;pcb=heir
mtsr cps,kt0 ;cps with FZ
nop
add pcb,pcb,4 ;space for signal num
spop gr1,pcb ;restore freeze registers
add gr1,gr1,0 ;alu op
spop rab,pcb
spopsr pc0,it1,pcb
spopsr pc1,it1,pcb
add pcb,pcb,4 ;space for pc2
spopsr CHA,it1,pcb
spopsr CHD,it1,pcb
spopsr CHC,it1,pcb
add pcb,pcb,4 ;space for alu
spopsr ops,it1,pcb
nop
iret
;/*
; * _CPU_Context_restore
; *
; * This routine is generallu used only to restart self in an
; * efficient manner. It may simply be a label in _CPU_Context_switch.
; *
; * NOTE: May be unnecessary to reload some registers.
; */
;#if 0
;void _CPU_Context_restore(
; Context_Control *new_context
;)
;{
;}
;#endif
.global __CPU_Context_restore
__CPU_Context_restore:
asneq 107, gr1, gr1 ; syscall
jmpi lr0 ;
nop ;
.global _a29k_context_restore_sup
_a29k_context_restore_sup:
add kt1,lr2,0 ;kt1 = restore context
mfsr kt0,cps ;current status
const it1,FZ ;FZ constant
andn it1,kt0,it1 ;clear FZ bit
mtsr cps,it1 ;cps without FZ
jmp context_restore
nop
.global _a29k_context_save_sup
_a29k_context_save_sup:
add pcb,lr2,0
constn it0,SIG_SYNC
spush pcb,it0
spush pcb,gr1
spush pcb,rab ;push rab
spushsr pcb,it0,pc0 ;push specials
spushsr pcb,it0,pc1
add pcb,pcb,1*4 ;space pc2
spushsr pcb,it0,CHA ;push CHA
spushsr pcb,it0,CHD ;push CHD
spushsr pcb,it0,CHC ;push CHC
add pcb,pcb,1*4 ;space for alu
spushsr pcb,it0,ops ;push OPS
mfsr it0,cps ;current status
SaveFZState it1,it2
add pcb,pcb,1*4 ;space for tav
mtsrim chc,0 ;possible DERR
;
spush pcb,lr1 ;push R-stack
spush pcb,rfb ; support
spush pcb,msp ;push M-stack pnt.
;
spush pcb,FPStat0 ;floating point
spush pcb,FPStat1
spush pcb,FPStat2
;
add pcb,pcb,4*4 ;space for IPA..Q
;
mtsrim cr,29-1
storem 0,0,gr96,pcb ;push gr96-124, optional
add pcb,pcb,29*4 ;space for gr96-124
;
sub kt0,rfb,gr1 ;get bytes in cache
srl kt0,kt0,2 ;adjust to words
sub kt0,kt0,1
spush pcb,kt0 ;push number of words
mtsr cr,kt0
storem 0,0,lr0,pcb ;save lr0-rfb
;
mtsr cps,it0 ;cps with FZ
RestoreFZState it1,it2
nop
nop
nop
;
iret
;
.global __CPU_Context_save
__CPU_Context_save:
asneq 108, gr1, gr1 ; syscall
jmpi lr0 ;
nop ;
;/* void __ISR_Handler()
; *
; * This routine provides the RTEMS interrupt management.
; *
; */
;#if 0
;void _ISR_Handler()
;{
; /*
; * This discussion ignores a lot of the ugly details in a real
; * implementation such as saving enough registers/state to be
; * able to do something real. Keep in mind that the goal is
; * to invoke a user's ISR handler which is written in C and
; * uses a certain set of registers.
; *
; * Also note that the exact order is to a large extent flexible.
; * Hardware will dictate a sequence for a certain subset of
; * _ISR_Handler while requirements for setting
; */
; /*
; * At entry to "common" _ISR_Handler, the vector number must be
; * available. On some CPUs the hardware puts either the vector
; * number or the offset into the vector table for this ISR in a
; * known place. If the hardware does not give us this information,
; * then the assembly portion of RTEMS for this port will contain
; * a set of distinct interrupt entry points which somehow place
; * the vector number in a known place (which is safe if another
; * interrupt nests this one) and branches to _ISR_Handler.
; *
; * save some or all context on stack
; * may need to save some special interrupt information for exit
; *
; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
; * if ( _ISR_Nest_level == 0 )
; * switch to software interrupt stack
; * #endif
; *
; * _ISR_Nest_level++;
; *
; * _Thread_Dispatch_disable_level++;
; *
; * (*_ISR_Vector_table[ vector ])( vector );
; *
; * --_ISR_Nest_level;
; *
; * if ( _ISR_Nest_level )
; * goto the label "exit interrupt (simple case)"
; *
; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
; * restore stack
; * #endif
; *
; * if ( !_Context_Switch_necessary )
; * goto the label "exit interrupt (simple case)"
; *
; * if ( !_ISR_Signals_to_thread_executing )
; * goto the label "exit interrupt (simple case)"
; *
; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
; *
; * prepare to get out of interrupt
; * return from interrupt (maybe to _ISR_Dispatch)
; *
; * LABEL "exit interrupt (simple case):
; * prepare to get out of interrupt
; * return from interrupt
; */
;}
;#endif
; .global __ISR_Handler
;__ISR_Handler:
; jmpi lr0
; nop
.global _a29k_disable
_a29k_disable:
asneq 110, gr96, gr96
jmpi lr0
nop
.global _a29k_disable_sup
_a29k_disable_sup:
mfsr kt0, ops
const kt1, (DI | TD)
consth kt1, (DI | TD)
or kt1, kt0, kt1
mtsr ops, kt1
iret
nop
.global _a29k_disable_all
_a29k_disable_all:
asneq 112, gr96, gr96
jmpi lr0
nop
.global _a29k_disable_all_sup
_a29k_disable_all_sup:
mfsr kt0, ops
const kt1, DA
consth kt1, DA
or kt1, kt0, kt1
mtsr ops, kt1
iret
nop
.global _a29k_enable_all
_a29k_enable_all:
asneq 111, gr96, gr96
jmpi lr0
nop
.global _a29k_enable_all_sup
_a29k_enable_all_sup:
mfsr kt0, ops
const kt1, DA
consth kt1, DA
andn kt1, kt0, kt1
mtsr ops, kt1
iret
nop
.global _a29k_enable
_a29k_enable:
asneq 109, gr96, gr96
jmpi lr0
nop
.global _a29k_enable_sup
_a29k_enable_sup:
mfsr kt0, ops
const kt1, (DI | TD)
consth kt1, (DI | TD)
andn kt1, kt0, kt1
mtsr ops, kt1
iret
nop
.global _a29k_halt
_a29k_halt:
halt
jmp _a29k_halt
nop
.global _a29k_super_mode
_a29k_super_mode:
mfsr gr96, ops
or gr96, gr96, 0x10
mtsr ops, gr96
iret
nop
.global _a29k_as70
_a29k_as70:
asneq 70,gr96,gr96
jmpi lr0
nop
c/src/exec/score/cpu/a29k/pswmacro.ah
+442
View File
@@ -0,0 +1,442 @@
; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; macros: Do_install and init_TLB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; /* $Id$ */
;* File information and includes.
.file "macro.ah"
.ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI"
.macro CONST32, RegName, RegValue
const RegName, RegValue
consth RegName, RegValue
.endm
.macro CONSTX, RegName, RegValue
.if (RegValue) <= 0x0000ffff
const RegName, RegValue
.else
const RegName, RegValue
consth RegName, RegValue
.endif
.endm
.macro PRODEV, RegName
srl RegName, RegName, 24
.endm
;
;* MACRO TO INSTALL VECTOR TABLE ENTRIES
;
;* Assumes vector table address in v0
.macro _setvec, trapnum, trapaddr
mfsr v0, vab ;
const v2, trapnum ;
sll v1, v2, 2 ;
add v1, v1, v0 ; v0 has location of vector tab
const v2, trapaddr ;
consth v2, trapaddr ;
store 0, 0, v2, v1 ;
nop ;
.endm
.macro syscall, name
const tav, HIF_@name ;
asneq V_SYSCALL, gr1, gr1 ;
nop ;
nop ;
.endm
;* MACRO TO INSTALL VECTOR TABLE ENTRIES
.macro Do_Install, V_Number, V_Address
const lr4, V_Address
consth lr4, V_Address
const lr3, V_Number * 4
consth lr3, V_Number * 4
call lr0, V_Install
nop
.endm
.macro Do_InstallX, V_Number, V_Address
const lr4, V_Address
consth lr4, V_Address
const lr3, V_Number * 4
consth lr3, V_Number * 4
call lr0, V_InstallX
nop
.endm
; push a register onto the stack
.macro pushreg, reg, sp
sub sp, sp, 4 ; adjust stack pointer
store 0, 0, reg, sp ; push register
.endm
.macro push, sp, reg
sub sp, sp, 4
store 0, 0, reg, sp
.endm
; pop the register from stack
.macro popreg, reg, sp
load 0, 0, reg, sp ; pop register
add sp, sp, 4 ; adjust stack pointer
.endm
.macro pop, reg, sp
load 0, 0, reg, sp
add sp, sp, 4
.endm
; push a special register onto stack
.macro pushspcl, spcl, tmpreg, sp
sub sp, sp, 4 ; adjust stack pointer
mfsr tmpreg, spcl ; get spcl reg
store 0, 0, tmpreg, sp ; push onto stack
.endm
.macro pushsr, sp, reg, sreg
mfsr reg, sreg
sub sp, sp, 4
store 0, 0, reg, sp
.endm
; pop a special register from stack
.macro popspcl, spcl, tmpreg, sp
load 0, 0, tmpreg, sp ; pop from stack
add sp, sp, 4 ; adjust stack pointer
mtsr spcl, tmpreg ; set spcl reg
.endm
.macro popsr, sreg, reg, sp
load 0, 0, reg, sp
add sp, sp, 4
mtsr sreg, reg
.endm
;
; save freeze mode registers on memory stack.
;
.macro SaveFZState, tmp1, tmp2
; save freeze mode registers.
pushspcl pc0, tmp1, msp
pushspcl pc1, tmp1, msp
pushspcl alu, tmp1, msp
pushspcl cha, tmp1, msp
pushspcl chd, tmp1, msp
pushspcl chc, tmp1, msp
pushspcl ops, tmp1, msp
; turn freeze off
const tmp2, FZ
mfsr tmp1, cps
andn tmp1, tmp1, tmp2
mtsr cps, tmp1
.endm
; restore freeze mode registers from memory stack.
.macro RestoreFZState, tmp1, tmp2
; turn freeze on
const tmp2, (FZ|DI|DA)
mfsr tmp1, cps
or tmp1, tmp1, tmp2
mtsr cps, tmp1
; restore freeze mode registers.
popspcl ops, tmp1, msp
popspcl chc, tmp1, msp
popspcl chd, tmp1, msp
popspcl cha, tmp1, msp
popspcl alu, tmp1, msp
popspcl pc1, tmp1, msp
popspcl pc0, tmp1, msp
.endm
;
;*
;
.equ WS, 512 ; window size
.equ RALLOC, 4 * 4 ; stack alloc for C
.equ SIGCTX_UM_SIZE, 40 * 4 ;
.equ SIGCTX_RFB, (38) * 4 ; user mode saved
.equ SIGCTX_SM_SIZE, 12 * 4 ;
.equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ;
.macro sup_sv
add it2, trapreg, 0 ; transfer signal #
sub msp, msp, 4 ;
store 0, 0, it2, msp ; save signal number
sub msp, msp, 4 ; push gr1
store 0, 0, gr1, msp ;
sub msp, msp, 4 ; push rab
store 0, 0, rab, msp ;
const it0, WS ; Window size
sub rab, rfb, it0 ; set rab = rfb-512
pushsr msp, it0, PC0 ; save program counter0
pushsr msp, it0, PC1 ; save program counter1
pushsr msp, it0, PC2 ; save program counter2
pushsr msp, it0, CHA ; save channel address
pushsr msp, it0, CHD ; save channel data
pushsr msp, it0, CHC ; save channel control
pushsr msp, it0, ALU ; save alu
pushsr msp, it0, OPS ; save ops
sub msp, msp, 4 ;
store 0, 0, tav, msp ; push tav
mtsrim chc, 0 ; no loadm/storem
mfsr it0, ops ; get ops value
const it1, (TD | DI) ; disable interrupts
consth it1, (TD | DI) ; disable interrupts
or it0, it0, it1 ; set bits
mtsr ops, it0 ; set new ops
const it0, _sigcode ; signal handler
consth it0, _sigcode ; signal handler
mtsr pc1, it0 ; store pc1
add it1, it0, 4 ; next addr
mtsr pc0, it1 ; store pc1 location
iret ; return
nop ; ALIGN
.endm
.macro sig_return
mfsr it0, cps ; get processor status
const it1, FZ|DA ; Freeze + traps disable
or it0, it0, it1 ; to set FZ+DA
mtsr cps, it0 ; in freeze mode
load 0, 0, tav, msp ; restore tav
add msp, msp, 4 ;
popsr OPS,it0, msp ;
popsr ALU,it0, msp ;
popsr CHC,it0, msp ;
popsr CHD,it0, msp ;
popsr CHA,it0, msp ;
popsr PC2,it0, msp ;
popsr PC1,it0, msp ;
popsr PC0,it0, msp ;
load 0, 0, rab, msp ;
add msp, msp, 4 ;
load 0, 0, it0, msp ;
add gr1, it0, 0 ; pop rsp
add msp, msp, 8 ; discount signal #
iret
.endm
.macro repair_R_stack
add v0, msp, SIGCTX_GR1 ; interrupted gr1
load 0, 0, v2, v0 ;
add v0, msp, SIGCTX_RFB ;
load 0, 0, v3, v0 ; interupted rfb
const v1, WS ;
sub v1, v3, v1 ; rfb-512
cpltu v0, v2, v1 ; test gr1 < rfb-512
jmpf v0, $1 ;
add gr1, rab, 0 ;
add v2, v1, 0 ; set LB = rfb-512
$1:
;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill
;* if no, LB=gr1 interrupted cache < 126 registers
cpleu v0, v2, rfb ; test LB<=rfb
jmpf v0, $2 ;
nop ;
add v2, rfb, 0 ;
$2:
cpeq v0, v3, rfb ; fill rfb->'rfb
jmpt v0, $3 ; if rfb==rfb'
const tav, (0x80<<2) ; prepare for fill
or tav, tav, v2 ;
mtsr IPA, tav ; IPA=LA<<2
sub tav, v3, gr98 ; cache fill LA->rfb
srl tav, tav, 2 ; convert to words
sub tav, tav, 1 ;
mtsr cr, tav ;
loadm 0, 0, gr0, v2 ; fill from LA->rfb
$3:
add rfb, v3, 0 ; move rfb upto 'rfb
sub rab, v1, 0 ; assign rab to rfb-512
add v0, msp, SIGCTX_GR1 ;
load 0, 0, v2, v0 ; v0 = interrupted gr1
add gr1, v2, 0 ; move gr1 upto 'gr1
nop ;
.endm
.macro repair_regs
mtsrim cr, 29 - 1 ; to restore locals
loadm 0, 0, v0, msp ;
add msp, msp, 29*4 ;
popsr Q, tav, msp ;
popsr IPC, tav, msp ;
popsr IPB, tav, msp ;
popsr IPA, tav, msp ;
pop FPStat3, msp ; floating point regs
pop FPStat2, msp ; floating point regs
pop FPStat1, msp ; floating point regs
pop FPStat0, msp ; floating point regs
add msp, msp, 3*4 ; R-stack repaired
.endm
;
;*HIF related...
;
; send the message in bufaddr to Montip.
.macro SendMessageToMontip, bufaddr
const lr2, bufaddr
$1:
call lr0, _msg_send
consth lr2, bufaddr
cpeq gr96, gr96, 0
jmpf gr96, $1
const lr2, bufaddr
.endm
; build a HIF_CALL message in bufaddr to send to montip.
.macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2
const tmp1, bufaddr
consth tmp1, bufaddr
const tmp2, HIF_CALL_MSGCODE
store 0, 0, tmp2, tmp1 ; msg code
add tmp1, tmp1, 4
const tmp2, HIF_CALL_MSGLEN
store 0, 0, tmp2, tmp1 ; msg len
add tmp1, tmp1, 4
store 0, 0, gr121, tmp1 ; service number
add tmp1, tmp1, 4
store 0, 0, lr2, tmp1 ; lr2
add tmp1, tmp1, 4
store 0, 0, lr3, tmp1 ; lr3
add tmp1, tmp1, 4
store 0, 0, lr4, tmp1 ; lr4
.endm
;
;*
;* All the funky AMD style macros go in here...simply for
;* compatility
;
;
.macro IMPORT, symbol
.extern symbol
.endm
.macro GLOBAL, symbol
.global symbol
.endm
.macro USESECT, name, type
.sect name, type
.use name
.endm
.macro SECTION, name, type
.sect name, type
.endm
.macro FUNC, fname, lineno
.global fname
fname:
.endm
.macro ENDFUNC, fname, lineno
.endm
;*************************************LONG
.macro LONG, varname
varname:
.block 4
.endm
;*************************************UNSIGNED LONG
.macro ULONG, varname
varname:
.block 4
.endm
;*************************************SHORT
.macro SHORT, varname
varname:
.block 2
.endm
;*************************************CHAR
.macro CHAR, varname
varname:
.block 1
.endm
;*************************************LONGARRAY
.macro LONGARRAY, name, count
name:
.block count*4
.endm
;*************************************SHORTARRAY
.macro SHORTARRAY, name, count
name:
.block count*2
.endm
;*************************************CHARARRAY
.macro CHARARRAY, name, count
name:
.block count
.endm
;*************************************VOID_FPTR
.macro VOID_FPTR, name
name:
.block 4
.endm
c/src/exec/score/cpu/a29k/rtems.c
+48
View File
@@ -0,0 +1,48 @@
/* rtems.c ===> rtems.S or rtems.s
*
* This file contains the single entry point code for
* the XXX implementation of RTEMS.
*
* NOTE: This is supposed to be a .S or .s file NOT a C file.
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*/
#ifndef lint
static char _sccsid[] = "@(#)rtems.c 04/08/96 1.1\n";
#endif
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" rtems file.
*/
#include <rtems/system.h>
#include <rtems/score/cpu.h>
/* #include "asm.h> */
/*
* RTEMS
*
* This routine jumps to the directive indicated in the
* CPU defined register. This routine is used when RTEMS is
* linked by itself and placed in ROM. This routine is the
* first address in the ROM space for RTEMS. The user "calls"
* this address with the directive arguments in the normal place.
* This routine then jumps indirectly to the correct directive
* preserving the arguments. The directive should not realize
* it has been "wrapped" in this way. The table "_Entry_points"
* is used to look up the directive.
*/
void RTEMS()
{
}
cpukit/score/cpu/a29k/amd.ah
+531
View File
File diff suppressed because it is too large Load Diff
cpukit/score/cpu/a29k/asm.h
+98
View File
@@ -0,0 +1,98 @@
/* asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
* COPYRIGHT (c) 1994.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#ifndef __NO_CPU_ASM_h
#define __NO_CPU_ASM_h
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#define ASM
#include <rtems/score/no_cpu.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .globl SYM (sym)
#define EXTERN(sym) .globl SYM (sym)
#endif
/* end of include file */
cpukit/score/cpu/a29k/cpu.c
+256
View File
@@ -0,0 +1,256 @@
/*
* AMD 29K CPU Dependent Source
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
* $Id$
*/
#ifndef lint
static char _sccsid[] = "@(#)cpu.c 21 Aug 1996 1.6\n";
#endif
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <rtems/score/thread.h>
#include <stdio.h>
#include <stdlib.h>
void a29k_ISR_Handler(unsigned32 vector);
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS:
* cpu_table - CPU table to initialize
* thread_dispatch - address of disptaching routine
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)() /* ignored on this CPU */
)
{
unsigned int i;
/*
* The thread_dispatch argument is the address of the entry point
* for the routine called at the end of an ISR once it has been
* decided a context switch is necessary. On some compilation
* systems it is difficult to call a high-level language routine
* from assembly. This allows us to trick these systems.
*
* If you encounter this problem save the entry point in a CPU
* dependent variable.
*/
_CPU_Thread_dispatch_pointer = thread_dispatch;
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
_CPU_Table = *cpu_table;
for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
{
_ISR_Vector_table[i] = (proc_ptr)NULL;
}
}
/*PAGE
*
* _CPU_ISR_Get_level
*/
unsigned32 _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
*/
return 0;
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*/
extern void intr14( void );
extern void intr3( void );
extern void intr2( void );
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/*
* This is where we install the interrupt handler into the "raw" interrupt
* table used by the CPU to dispatch interrupt handlers.
*/
switch( vector )
{
case 14:
_settrap( vector, intr14 );
break;
case 3:
_settrap( vector, intr3 );
break;
case 2:
_settrap( vector, intr2 );
break;
default:
break;
}
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* If the interrupt vector table is a table of pointer to isr entry
* points, then we need to install the appropriate RTEMS interrupt
* handler for this vector number.
*/
_CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
/*
* We put the actual user ISR address in '_ISR_vector_table'. This will
* be used by the _ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
/*PAGE
*
* _CPU_Install_interrupt_stack
*/
void _CPU_Install_interrupt_stack( void )
{
}
/*PAGE
*
* _CPU_Internal_threads_Idle_thread_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*/
void _CPU_Internal_threads_Idle_thread_body( void )
{
for( ; ; )
{
}
/* insert your "halt" instruction here */ ;
}
void a29k_fatal_error( unsigned32 error )
{
printf("\n\nfatal error %d, rebooting!!!\n",error );
exit(error);
}
/*
* This discussion ignores a lot of the ugly details in a real
* implementation such as saving enough registers/state to be
* able to do something real. Keep in mind that the goal is
* to invoke a user's ISR handler which is written in C and
* uses a certain set of registers.
*
* Also note that the exact order is to a large extent flexible.
* Hardware will dictate a sequence for a certain subset of
* _ISR_Handler while requirements for setting
*/
/*
* At entry to "common" _ISR_Handler, the vector number must be
* available. On some CPUs the hardware puts either the vector
* number or the offset into the vector table for this ISR in a
* known place. If the hardware does not give us this information,
* then the assembly portion of RTEMS for this port will contain
* a set of distinct interrupt entry points which somehow place
* the vector number in a known place (which is safe if another
* interrupt nests this one) and branches to _ISR_Handler.
*
*/
void a29k_ISR_Handler(unsigned32 vector)
{
_ISR_Nest_level++;
_Thread_Dispatch_disable_level++;
if ( _ISR_Vector_table[ vector ] )
(*_ISR_Vector_table[ vector ])( vector );
--_Thread_Dispatch_disable_level;
--_ISR_Nest_level;
if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level &&
(_Context_Switch_necessary || _ISR_Signals_to_thread_executing ))
_Thread_Dispatch();
return;
}
cpukit/score/cpu/a29k/pswmacro.ah
+442
View File
@@ -0,0 +1,442 @@
; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; macros: Do_install and init_TLB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; /* $Id$ */
;* File information and includes.
.file "macro.ah"
.ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI"
.macro CONST32, RegName, RegValue
const RegName, RegValue
consth RegName, RegValue
.endm
.macro CONSTX, RegName, RegValue
.if (RegValue) <= 0x0000ffff
const RegName, RegValue
.else
const RegName, RegValue
consth RegName, RegValue
.endif
.endm
.macro PRODEV, RegName
srl RegName, RegName, 24
.endm
;
;* MACRO TO INSTALL VECTOR TABLE ENTRIES
;
;* Assumes vector table address in v0
.macro _setvec, trapnum, trapaddr
mfsr v0, vab ;
const v2, trapnum ;
sll v1, v2, 2 ;
add v1, v1, v0 ; v0 has location of vector tab
const v2, trapaddr ;
consth v2, trapaddr ;
store 0, 0, v2, v1 ;
nop ;
.endm
.macro syscall, name
const tav, HIF_@name ;
asneq V_SYSCALL, gr1, gr1 ;
nop ;
nop ;
.endm
;* MACRO TO INSTALL VECTOR TABLE ENTRIES
.macro Do_Install, V_Number, V_Address
const lr4, V_Address
consth lr4, V_Address
const lr3, V_Number * 4
consth lr3, V_Number * 4
call lr0, V_Install
nop
.endm
.macro Do_InstallX, V_Number, V_Address
const lr4, V_Address
consth lr4, V_Address
const lr3, V_Number * 4
consth lr3, V_Number * 4
call lr0, V_InstallX
nop
.endm
; push a register onto the stack
.macro pushreg, reg, sp
sub sp, sp, 4 ; adjust stack pointer
store 0, 0, reg, sp ; push register
.endm
.macro push, sp, reg
sub sp, sp, 4
store 0, 0, reg, sp
.endm
; pop the register from stack
.macro popreg, reg, sp
load 0, 0, reg, sp ; pop register
add sp, sp, 4 ; adjust stack pointer
.endm
.macro pop, reg, sp
load 0, 0, reg, sp
add sp, sp, 4
.endm
; push a special register onto stack
.macro pushspcl, spcl, tmpreg, sp
sub sp, sp, 4 ; adjust stack pointer
mfsr tmpreg, spcl ; get spcl reg
store 0, 0, tmpreg, sp ; push onto stack
.endm
.macro pushsr, sp, reg, sreg
mfsr reg, sreg
sub sp, sp, 4
store 0, 0, reg, sp
.endm
; pop a special register from stack
.macro popspcl, spcl, tmpreg, sp
load 0, 0, tmpreg, sp ; pop from stack
add sp, sp, 4 ; adjust stack pointer
mtsr spcl, tmpreg ; set spcl reg
.endm
.macro popsr, sreg, reg, sp
load 0, 0, reg, sp
add sp, sp, 4
mtsr sreg, reg
.endm
;
; save freeze mode registers on memory stack.
;
.macro SaveFZState, tmp1, tmp2
; save freeze mode registers.
pushspcl pc0, tmp1, msp
pushspcl pc1, tmp1, msp
pushspcl alu, tmp1, msp
pushspcl cha, tmp1, msp
pushspcl chd, tmp1, msp
pushspcl chc, tmp1, msp
pushspcl ops, tmp1, msp
; turn freeze off
const tmp2, FZ
mfsr tmp1, cps
andn tmp1, tmp1, tmp2
mtsr cps, tmp1
.endm
; restore freeze mode registers from memory stack.
.macro RestoreFZState, tmp1, tmp2
; turn freeze on
const tmp2, (FZ|DI|DA)
mfsr tmp1, cps
or tmp1, tmp1, tmp2
mtsr cps, tmp1
; restore freeze mode registers.
popspcl ops, tmp1, msp
popspcl chc, tmp1, msp
popspcl chd, tmp1, msp
popspcl cha, tmp1, msp
popspcl alu, tmp1, msp
popspcl pc1, tmp1, msp
popspcl pc0, tmp1, msp
.endm
;
;*
;
.equ WS, 512 ; window size
.equ RALLOC, 4 * 4 ; stack alloc for C
.equ SIGCTX_UM_SIZE, 40 * 4 ;
.equ SIGCTX_RFB, (38) * 4 ; user mode saved
.equ SIGCTX_SM_SIZE, 12 * 4 ;
.equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ;
.equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ;
.macro sup_sv
add it2, trapreg, 0 ; transfer signal #
sub msp, msp, 4 ;
store 0, 0, it2, msp ; save signal number
sub msp, msp, 4 ; push gr1
store 0, 0, gr1, msp ;
sub msp, msp, 4 ; push rab
store 0, 0, rab, msp ;
const it0, WS ; Window size
sub rab, rfb, it0 ; set rab = rfb-512
pushsr msp, it0, PC0 ; save program counter0
pushsr msp, it0, PC1 ; save program counter1
pushsr msp, it0, PC2 ; save program counter2
pushsr msp, it0, CHA ; save channel address
pushsr msp, it0, CHD ; save channel data
pushsr msp, it0, CHC ; save channel control
pushsr msp, it0, ALU ; save alu
pushsr msp, it0, OPS ; save ops
sub msp, msp, 4 ;
store 0, 0, tav, msp ; push tav
mtsrim chc, 0 ; no loadm/storem
mfsr it0, ops ; get ops value
const it1, (TD | DI) ; disable interrupts
consth it1, (TD | DI) ; disable interrupts
or it0, it0, it1 ; set bits
mtsr ops, it0 ; set new ops
const it0, _sigcode ; signal handler
consth it0, _sigcode ; signal handler
mtsr pc1, it0 ; store pc1
add it1, it0, 4 ; next addr
mtsr pc0, it1 ; store pc1 location
iret ; return
nop ; ALIGN
.endm
.macro sig_return
mfsr it0, cps ; get processor status
const it1, FZ|DA ; Freeze + traps disable
or it0, it0, it1 ; to set FZ+DA
mtsr cps, it0 ; in freeze mode
load 0, 0, tav, msp ; restore tav
add msp, msp, 4 ;
popsr OPS,it0, msp ;
popsr ALU,it0, msp ;
popsr CHC,it0, msp ;
popsr CHD,it0, msp ;
popsr CHA,it0, msp ;
popsr PC2,it0, msp ;
popsr PC1,it0, msp ;
popsr PC0,it0, msp ;
load 0, 0, rab, msp ;
add msp, msp, 4 ;
load 0, 0, it0, msp ;
add gr1, it0, 0 ; pop rsp
add msp, msp, 8 ; discount signal #
iret
.endm
.macro repair_R_stack
add v0, msp, SIGCTX_GR1 ; interrupted gr1
load 0, 0, v2, v0 ;
add v0, msp, SIGCTX_RFB ;
load 0, 0, v3, v0 ; interupted rfb
const v1, WS ;
sub v1, v3, v1 ; rfb-512
cpltu v0, v2, v1 ; test gr1 < rfb-512
jmpf v0, $1 ;
add gr1, rab, 0 ;
add v2, v1, 0 ; set LB = rfb-512
$1:
;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill
;* if no, LB=gr1 interrupted cache < 126 registers
cpleu v0, v2, rfb ; test LB<=rfb
jmpf v0, $2 ;
nop ;
add v2, rfb, 0 ;
$2:
cpeq v0, v3, rfb ; fill rfb->'rfb
jmpt v0, $3 ; if rfb==rfb'
const tav, (0x80<<2) ; prepare for fill
or tav, tav, v2 ;
mtsr IPA, tav ; IPA=LA<<2
sub tav, v3, gr98 ; cache fill LA->rfb
srl tav, tav, 2 ; convert to words
sub tav, tav, 1 ;
mtsr cr, tav ;
loadm 0, 0, gr0, v2 ; fill from LA->rfb
$3:
add rfb, v3, 0 ; move rfb upto 'rfb
sub rab, v1, 0 ; assign rab to rfb-512
add v0, msp, SIGCTX_GR1 ;
load 0, 0, v2, v0 ; v0 = interrupted gr1
add gr1, v2, 0 ; move gr1 upto 'gr1
nop ;
.endm
.macro repair_regs
mtsrim cr, 29 - 1 ; to restore locals
loadm 0, 0, v0, msp ;
add msp, msp, 29*4 ;
popsr Q, tav, msp ;
popsr IPC, tav, msp ;
popsr IPB, tav, msp ;
popsr IPA, tav, msp ;
pop FPStat3, msp ; floating point regs
pop FPStat2, msp ; floating point regs
pop FPStat1, msp ; floating point regs
pop FPStat0, msp ; floating point regs
add msp, msp, 3*4 ; R-stack repaired
.endm
;
;*HIF related...
;
; send the message in bufaddr to Montip.
.macro SendMessageToMontip, bufaddr
const lr2, bufaddr
$1:
call lr0, _msg_send
consth lr2, bufaddr
cpeq gr96, gr96, 0
jmpf gr96, $1
const lr2, bufaddr
.endm
; build a HIF_CALL message in bufaddr to send to montip.
.macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2
const tmp1, bufaddr
consth tmp1, bufaddr
const tmp2, HIF_CALL_MSGCODE
store 0, 0, tmp2, tmp1 ; msg code
add tmp1, tmp1, 4
const tmp2, HIF_CALL_MSGLEN
store 0, 0, tmp2, tmp1 ; msg len
add tmp1, tmp1, 4
store 0, 0, gr121, tmp1 ; service number
add tmp1, tmp1, 4
store 0, 0, lr2, tmp1 ; lr2
add tmp1, tmp1, 4
store 0, 0, lr3, tmp1 ; lr3
add tmp1, tmp1, 4
store 0, 0, lr4, tmp1 ; lr4
.endm
;
;*
;* All the funky AMD style macros go in here...simply for
;* compatility
;
;
.macro IMPORT, symbol
.extern symbol
.endm
.macro GLOBAL, symbol
.global symbol
.endm
.macro USESECT, name, type
.sect name, type
.use name
.endm
.macro SECTION, name, type
.sect name, type
.endm
.macro FUNC, fname, lineno
.global fname
fname:
.endm
.macro ENDFUNC, fname, lineno
.endm
;*************************************LONG
.macro LONG, varname
varname:
.block 4
.endm
;*************************************UNSIGNED LONG
.macro ULONG, varname
varname:
.block 4
.endm
;*************************************SHORT
.macro SHORT, varname
varname:
.block 2
.endm
;*************************************CHAR
.macro CHAR, varname
varname:
.block 1
.endm
;*************************************LONGARRAY
.macro LONGARRAY, name, count
name:
.block count*4
.endm
;*************************************SHORTARRAY
.macro SHORTARRAY, name, count
name:
.block count*2
.endm
;*************************************CHARARRAY
.macro CHARARRAY, name, count
name:
.block count
.endm
;*************************************VOID_FPTR
.macro VOID_FPTR, name
name:
.block 4
.endm