mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-21 04:07:33 +08:00
2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
* clock/clock-config.c: Fixes to pass psnsext01. * startup/bspstart.c: Workaround for GCC 4.6 bug. * include/smsc9218i.h, network/smsc9218i.c, Makefile.am: Changes throughout.
This commit is contained in:
Sebastian Huber
@@ -1,3 +1,10 @@
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2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* clock/clock-config.c: Fixes to pass psnsext01.
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* startup/bspstart.c: Workaround for GCC 4.6 bug.
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* include/smsc9218i.h, network/smsc9218i.c, Makefile.am: Changes
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throughout.
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2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
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* network/smsc9218i.c, startup/bspstart.c:
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@@ -70,10 +70,7 @@ libbsp_a_SOURCES += i2c/i2c_init.c \
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# Network
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if HAS_NETWORKING
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noinst_PROGRAMS += network.rel
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network_rel_SOURCES = network/smsc9218i.c
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network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
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network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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libbsp_a_SOURCES += network/smsc9218i.c
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endif
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# BSP library
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@@ -91,9 +88,6 @@ libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
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../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
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../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
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../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel
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if HAS_NETWORKING
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libbsp_a_LIBADD += network.rel
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endif
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/../../../../automake/local.am
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@@ -43,7 +43,9 @@ rtems_isr Clock_isr( rtems_vector_number vector);
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EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.R = csr.R; \
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} while (0)
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static void mpc55xx_clock_handler_install( rtems_isr_entry isr,
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static uint64_t mpc55xx_clock_factor;
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static void mpc55xx_clock_handler_install( rtems_isr_entry isr,
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rtems_isr_entry *old_isr)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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@@ -69,6 +71,8 @@ static void mpc55xx_clock_initialize( void)
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uint64_t interval = ((uint64_t) bsp_clock_speed
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* (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000;
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mpc55xx_clock_factor = (1000000000ULL << 32) / bsp_clock_speed;
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/* Apply prescaler */
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if (prescaler > 0) {
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interval /= (uint64_t) prescaler;
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@@ -131,11 +135,16 @@ static void mpc55xx_clock_cleanup( void)
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static uint32_t mpc55xx_clock_nanoseconds_since_last_tick( void)
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{
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uint64_t clicks = EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CCNTR.R;
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uint64_t clock = bsp_clock_speed;
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uint64_t ns = (clicks * 1000000000) / clock;
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volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
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uint64_t c = regs->CCNTR.R;
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union EMIOS_CSR_tag csr = { .R = regs->CSR.R };
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uint64_t k = mpc55xx_clock_factor;
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return (uint32_t) ns;
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if (csr.B.FLAG != 0) {
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c = regs->CCNTR.R + regs->CADR.R + 1;
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}
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return (uint32_t) ((c * k) >> 32);
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}
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#define Clock_driver_support_initialize_hardware() mpc55xx_clock_initialize()
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@@ -189,62 +189,32 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
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/** @} */
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/**
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* @name Interrupt Status
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* @name Interrupt Enable and Status
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* @{
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*/
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#define SMSC9218I_INT_STS_SW SMSC9218I_FLAG(31)
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#define SMSC9218I_INT_STS_TXSTOP SMSC9218I_FLAG(25)
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#define SMSC9218I_INT_STS_RXSTOP SMSC9218I_FLAG(24)
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#define SMSC9218I_INT_STS_RXDFH SMSC9218I_FLAG(23)
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#define SMSC9218I_INT_STS_TIOC SMSC9218I_FLAG(21)
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#define SMSC9218I_INT_STS_RXD SMSC9218I_FLAG(20)
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#define SMSC9218I_INT_STS_GPT SMSC9218I_FLAG(19)
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#define SMSC9218I_INT_STS_PHY SMSC9218I_FLAG(18)
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#define SMSC9218I_INT_STS_PME SMSC9218I_FLAG(17)
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#define SMSC9218I_INT_STS_TXSO SMSC9218I_FLAG(16)
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#define SMSC9218I_INT_STS_RWT SMSC9218I_FLAG(15)
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#define SMSC9218I_INT_STS_RXE SMSC9218I_FLAG(14)
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#define SMSC9218I_INT_STS_TXE SMSC9218I_FLAG(13)
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#define SMSC9218I_INT_STS_TDFO SMSC9218I_FLAG(10)
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#define SMSC9218I_INT_STS_TDFA SMSC9218I_FLAG(9)
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#define SMSC9218I_INT_STS_TSFF SMSC9218I_FLAG(8)
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#define SMSC9218I_INT_STS_TSFL SMSC9218I_FLAG(7)
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#define SMSC9218I_INT_STS_RSFF SMSC9218I_FLAG(4)
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#define SMSC9218I_INT_STS_RSFL SMSC9218I_FLAG(3)
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#define SMSC9218I_INT_STS_GPIO2 SMSC9218I_FLAG(2)
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#define SMSC9218I_INT_STS_GPIO1 SMSC9218I_FLAG(1)
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#define SMSC9218I_INT_STS_GPIO0 SMSC9218I_FLAG(0)
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/** @} */
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/**
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* @name Interrupt Enable
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* @{
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*/
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#define SMSC9218I_INT_EN_SW SMSC9218I_FLAG(31)
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#define SMSC9218I_INT_EN_TXSTOP SMSC9218I_FLAG(25)
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#define SMSC9218I_INT_EN_RXSTOP SMSC9218I_FLAG(24)
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#define SMSC9218I_INT_EN_RXDFH SMSC9218I_FLAG(23)
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#define SMSC9218I_INT_EN_TIOC SMSC9218I_FLAG(21)
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#define SMSC9218I_INT_EN_RXD SMSC9218I_FLAG(20)
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#define SMSC9218I_INT_EN_GPT SMSC9218I_FLAG(19)
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#define SMSC9218I_INT_EN_PHY SMSC9218I_FLAG(18)
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#define SMSC9218I_INT_EN_PME SMSC9218I_FLAG(17)
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#define SMSC9218I_INT_EN_TXSO SMSC9218I_FLAG(16)
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#define SMSC9218I_INT_EN_RWT SMSC9218I_FLAG(15)
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#define SMSC9218I_INT_EN_RXE SMSC9218I_FLAG(14)
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#define SMSC9218I_INT_EN_TXE SMSC9218I_FLAG(13)
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#define SMSC9218I_INT_EN_TDFO SMSC9218I_FLAG(10)
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#define SMSC9218I_INT_EN_TDFA SMSC9218I_FLAG(9)
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#define SMSC9218I_INT_EN_TSFF SMSC9218I_FLAG(8)
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#define SMSC9218I_INT_EN_TSFL SMSC9218I_FLAG(7)
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#define SMSC9218I_INT_EN_RSFF SMSC9218I_FLAG(4)
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#define SMSC9218I_INT_EN_RSFL SMSC9218I_FLAG(3)
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#define SMSC9218I_INT_EN_GPIO2 SMSC9218I_FLAG(2)
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#define SMSC9218I_INT_EN_GPIO1 SMSC9218I_FLAG(1)
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#define SMSC9218I_INT_EN_GPIO0 SMSC9218I_FLAG(0)
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#define SMSC9218I_INT_SW SMSC9218I_FLAG(31)
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#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25)
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#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24)
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#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23)
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#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21)
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#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20)
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#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19)
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#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18)
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#define SMSC9218I_INT_PME SMSC9218I_FLAG(17)
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#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16)
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#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15)
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#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14)
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#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13)
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#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10)
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#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9)
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#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8)
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#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7)
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#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4)
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#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3)
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#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2)
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#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1)
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#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0)
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/** @} */
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@@ -438,6 +408,15 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
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/** @} */
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/**
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* @name EEPROM Command Register
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* @{
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*/
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#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31)
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/** @} */
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/**
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* @name MAC Control and Status Synchronizer Command
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* @{
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@@ -598,52 +577,12 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
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/** @} */
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/**
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* @name Basic Control
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* @{
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*/
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#define SMSC9218I_PHY_BCR 0x00000000U
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#define SMSC9218I_PHY_BCR_RST 0x00008000U
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#define SMSC9218I_PHY_BCR_LOOPBK 0x00004000U
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#define SMSC9218I_PHY_BCR_SS 0x00002000U
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#define SMSC9218I_PHY_BCR_ANE 0x00001000U
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#define SMSC9218I_PHY_BCR_PWRDN 0x00000800U
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#define SMSC9218I_PHY_BCR_RSTAN 0x00000200U
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#define SMSC9218I_PHY_BCR_FDPLX 0x00000100U
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#define SMSC9218I_PHY_BCR_COLLTST 0x00000080U
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/** @} */
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/**
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* @name Basic Status
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* @{
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*/
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#define SMSC9218I_PHY_BSR 0x00000001U
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#define SMSC9218I_PHY_BSR_100_T4_ABLE 0x00008000U
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#define SMSC9218I_PHY_BSR_100_TX_FDPLX 0x00004000U
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#define SMSC9218I_PHY_BSR_100_TX_HDPLX 0x00002000U
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#define SMSC9218I_PHY_BSR_10_FDPLX 0x00001000U
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#define SMSC9218I_PHY_BSR_10_HDPLX 0x00000800U
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#define SMSC9218I_PHY_BSR_ANC 0x00000020U
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#define SMSC9218I_PHY_BSR_REM_FAULT 0x00000010U
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#define SMSC9218I_PHY_BSR_AN_ABLE 0x00000008U
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#define SMSC9218I_PHY_BSR_LINK_STATUS 0x00000004U
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#define SMSC9218I_PHY_BSR_JAB_DET 0x00000002U
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#define SMSC9218I_PHY_BSR_EXT_CAP 0x00000001U
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/** @} */
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/**
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* @name PHY Identifier 1
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* @{
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*/
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#define SMSC9218I_PHY_ID1 0x00000002U
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#define SMSC9218I_PHY_ID1_MASK 0x0000ffffU
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#define SMSC9218I_PHY_ID1_LAN9118 0x00000007U
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#define SMSC9218I_PHY_ID1_LAN9218 (PHY_ID1_LAN9118)
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#define SMSC9218I_PHY_ID1_LAN9118 0x7
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/** @} */
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@@ -652,65 +591,7 @@ volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *)
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* @{
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*/
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#define SMSC9218I_PHY_ID2 0x00000003U
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#define SMSC9218I_PHY_ID2_MASK 0x0000ffffU
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#define SMSC9218I_PHY_ID2_MODEL_MASK 0x000003f0U
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#define SMSC9218I_PHY_ID2_REV_MASK 0x0000000fU
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#define SMSC9218I_PHY_ID2_LAN9118 0x0000c0d1U
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#define SMSC9218I_PHY_ID2_LAN9218 0x0000c0c3U
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/** @} */
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/**
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* @name Auto-negotiation Advertisment
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* @{
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*/
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#define SMSC9218I_PHY_ANAR 0x00000004U
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#define SMSC9218I_PHY_ANAR_NXTPG_CAP 0x00008000U
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#define SMSC9218I_PHY_ANAR_REM_FAULT 0x00002000U
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#define SMSC9218I_PHY_ANAR_PAUSE_OP_MASK 0x00000c00U
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#define SMSC9218I_PHY_ANAR_PAUSE_OP_NONE 0x00000000U
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#define SMSC9218I_PHY_ANAR_PAUSE_OP_ASLP 0x00000400U
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#define SMSC9218I_PHY_ANAR_PAUSE_OP_SLP 0x00000800U
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#define SMSC9218I_PHY_ANAR_PAUSE_OP_BOTH 0x00000c00U
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#define SMSC9218I_PHY_ANAR_100_T4_ABLE 0x00000200U
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#define SMSC9218I_PHY_ANAR_100_TX_FDPLX 0x00000100U
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#define SMSC9218I_PHY_ANAR_100_TX_ABLE 0x00000080U
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#define SMSC9218I_PHY_ANAR_10_FDPLX 0x00000040U
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#define SMSC9218I_PHY_ANAR_10_ABLE 0x00000020U
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/** @} */
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/**
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* @name Auto-negotiation Link Partner Ability
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* @{
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*/
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#define SMSC9218I_PHY_ANLPAR 0x00000005U
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#define SMSC9218I_PHY_ANLPAR_NXTPG_CAP 0x00008000U
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#define SMSC9218I_PHY_ANLPAR_ACK 0x00004000U
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#define SMSC9218I_PHY_ANLPAR_REM_FAULT 0x00002000U
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#define SMSC9218I_PHY_ANLPAR_PAUSE_CAP 0x00000400U
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#define SMSC9218I_PHY_ANLPAR_100_T4_ABLE 0x00000200U
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#define SMSC9218I_PHY_ANLPAR_100_TX_FDPLX 0x00000100U
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#define SMSC9218I_PHY_ANLPAR_100_TX_ABLE 0x00000080U
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#define SMSC9218I_PHY_ANLPAR_10_FDPLX 0x00000040U
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#define SMSC9218I_PHY_ANLPAR_10_ABLE 0x00000020U
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/** @} */
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/**
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* @name Auto-negotiation Expansion
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* @{
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*/
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#define SMSC9218I_PHY_ANEXPR 0x00000006U
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#define SMSC9218I_PHY_ANEXPR_PARDET_FAULT 0x00000010U
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#define SMSC9218I_PHY_ANEXPR_LP_NXTPG_CAP 0x00000008U
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#define SMSC9218I_PHY_ANEXPR_NXTPG_CAP 0x00000004U
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#define SMSC9218I_PHY_ANEXPR_NEWPG_REC 0x00000002U
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#define SMSC9218I_PHY_ANEXPR_LP_AN_ABLE 0x00000001U
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#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3
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/** @} */
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File diff suppressed because it is too large
Load Diff
@@ -478,27 +478,10 @@ static const struct MMU_tag mmu_setup[] = {
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#else /* default, MPC55xxEVB */
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{
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/* External Ethernet Controller (3 wait states, 64kB) */
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{
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.B.TLBSEL = 1, /* MAS0 */
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.B.ESEL = 5
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},
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{
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.B.VALID = 1, /* MAS1 */
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.B.IPROT = 1,
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.B.TSIZ = 1
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},
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{
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.B.EPN = 0x3fff8, /* MAS2 */
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.B.I = 1,
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.B.G = 1
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},
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{
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.B.RPN = 0x3fff8, /* MAS3 */
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.B.UW = 1,
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.B.SW = 1,
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.B.UR = 1,
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.B.SR = 1
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}
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.MAS0 = { .R = 0x10050000 },
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.MAS1 = { .R = 0xc0000100 },
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.MAS2 = { .R = 0x3fff800a },
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.MAS3 = { .R = 0x3fff800f }
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}
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#endif /* MMU setup */
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};
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