mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-11-09 08:37:58 +08:00
Alexander Krutwig authored and 
Sebastian Huber committed
1 parent
e34fe384cb
commit
9edc73013b
6 files changed
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@@ -15,6 +15,10 @@ include_dev_spidir = $(includedir)/dev/spi
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include_dev_spi_HEADERS =
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include_dev_spi_HEADERS += include/dev/spi/spi.h
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include_dev_serialdir = $(includedir)/dev/serial
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include_dev_serial_HEADERS =
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include_dev_serial_HEADERS += include/dev/serial/sc16is752.h
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include_linuxdir = $(includedir)/linux
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include_linux_HEADERS =
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include_linux_HEADERS += include/linux/i2c.h
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@@ -33,6 +37,9 @@ libdev_a_SOURCES += i2c/i2c-bus.c
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libdev_a_SOURCES += i2c/i2c-dev.c
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libdev_a_SOURCES += i2c/switch-nxp-pca9548a.c
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libdev_a_SOURCES += spi/spi-bus.c
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libdev_a_SOURCES += serial/sc16is752.c
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libdev_a_SOURCES += serial/sc16is752-spi.c
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libdev_a_SOURCES += serial/sc16is752-regs.h
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/automake/local.am
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@@ -48,6 +48,15 @@ $(PROJECT_INCLUDE)/dev/spi/spi.h: include/dev/spi/spi.h $(PROJECT_INCLUDE)/dev/s
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/dev/spi/spi.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/dev/spi/spi.h
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$(PROJECT_INCLUDE)/dev/serial/$(dirstamp):
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@$(MKDIR_P) $(PROJECT_INCLUDE)/dev/serial
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@: > $(PROJECT_INCLUDE)/dev/serial/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/dev/serial/$(dirstamp)
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$(PROJECT_INCLUDE)/dev/serial/sc16is752.h: include/dev/serial/sc16is752.h $(PROJECT_INCLUDE)/dev/serial/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/dev/serial/sc16is752.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/dev/serial/sc16is752.h
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$(PROJECT_INCLUDE)/linux/$(dirstamp):
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@$(MKDIR_P) $(PROJECT_INCLUDE)/linux
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@: > $(PROJECT_INCLUDE)/linux/$(dirstamp)
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@@ -0,0 +1,116 @@
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/*
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* Copyright (c) 2016 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_ATSAM_SC16IS752_H
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#define LIBBSP_ARM_ATSAM_SC16IS752_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* General register set */
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#define SC16IS752_RHR 0x0
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#define SC16IS752_THR 0x0
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#define SC16IS752_IER 0x1
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#define SC16IS752_FCR 0x2
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#define SC16IS752_IIR 0x2
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#define SC16IS752_LCR 0x3
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#define SC16IS752_MCR 0x4
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#define SC16IS752_LSR 0x5
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#define SC16IS752_MSR 0x6
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#define SC16IS752_TCR 0x6
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#define SC16IS752_SPR 0x7
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#define SC16IS752_TLR 0x7
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#define SC16IS752_TXLVL 0x8
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#define SC16IS752_RXLVL 0x9
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#define SC16IS752_IODIR 0xA
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#define SC16IS752_IOSTATE 0xB
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#define SC16IS752_IOINTENA 0xC
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#define SC16IS752_IOCONTROL 0xE
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#define SC16IS752_EFCR 0xF
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/* Special register set */
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#define SC16IS752_DLL 0x0
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#define SC16IS752_DLH 0x1
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/* Enhanced register set */
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#define SC16IS752_EFR 0x2
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#define SC16IS752_XON1 0x4
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#define SC16IS752_XON2 0x5
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#define SC16IS752_XOFF1 0x6
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#define SC16IS752_XOFF2 0x7
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/* FCR */
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#define FCR_FIFO_EN 0x01
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#define FCR_RX_FIFO_RST 0x02
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#define FCR_TX_FIFO_RST 0x04
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#define FCR_TX_FIFO_TRG_8 0x00
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#define FCR_TX_FIFO_TRG_16 0x10
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#define FCR_TX_FIFO_TRG_32 0x20
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#define FCR_TX_FIFO_TRG_56 0x30
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#define FCR_RX_FIFO_TRG_8 0x00
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#define FCR_RX_FIFO_TRG_16 0x40
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#define FCR_RX_FIFO_TRG_56 0x80
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#define FCR_RX_FIFO_TRG_60 0xc0
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/* EFCR */
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#define EFCR_RS485_ENABLE (1u << 0)
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#define EFCR_RX_DISABLE (1u << 1)
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#define EFCR_TX_DISABLE (1u << 2)
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/* IER */
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#define IER_RHR (1u << 0)
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#define IER_THR (1u << 1)
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#define IER_RECEIVE_LINE_STATUS (1u << 2)
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#define IER_MODEM_STATUS (1u << 3)
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#define IER_SLEEP_MODE (1u << 4)
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#define IER_XOFF (1u << 5)
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#define IER_RTS (1u << 6)
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#define IER_CTS (1u << 7)
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/* IIR */
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#define IIR_TX_INTERRUPT (1u << 1)
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#define IIR_RX_INTERRUPT (1u << 2)
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/* LCR */
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#define LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
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#define LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
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#define LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
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#define LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
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#define LCR_2_STOP_BIT (1u << 2)
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#define LCR_SET_PARITY (1u << 3)
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#define LCR_EVEN_PARITY (1u << 4)
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#define LCR_ENABLE_DIVISOR (1u << 7)
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/* LSR */
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#define LSR_TXEMPTY (1u << 5)
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#define LSR_RXRDY (1u << 0)
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#define LSR_ERROR_BITS (7u << 2)
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/* MCR */
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#define MCR_PRESCALE_NEEDED (1u << 0)
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/* EFR */
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#define EFR_ENHANCED_FUNC_ENABLE (1u << 4)
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#define EFR_SPECIAL_CHAR_DETECT (1u << 5)
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#define EFR_RTS_FLOW_CTRL_EN (1u << 6)
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#define EFR_CTS_FLOW_CTRL_EN (1u << 7)
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#define SC16IS752_FIFO_DEPTH 64
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_ATSAM_SC16IS752_H */
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@@ -0,0 +1,151 @@
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/*
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* Copyright (c) 2016 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <dev/serial/sc16is752.h>
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#include <assert.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include <dev/spi/spi.h>
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#include "sc16is752-regs.h"
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static void msg_init(
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struct spi_ioc_transfer *msg,
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uint8_t cs,
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uint32_t speed,
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size_t len,
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uint8_t *rx_buf,
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const uint8_t *tx_buf
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)
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{
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msg->rx_buf = rx_buf;
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msg->tx_buf = tx_buf;
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msg->len = len;
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msg->speed_hz = speed;
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msg->delay_usecs = 1;
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msg->bits_per_word = 8;
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msg->cs_change = 0;
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msg->rx_nbits = 0;
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msg->tx_nbits = 0;
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msg->mode = 0;
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msg->cs = cs;
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}
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static int sc16is752_spi_write_reg(
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sc16is752_context *base,
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uint8_t addr,
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const uint8_t *data,
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size_t len
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)
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{
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sc16is752_spi_context *ctx = (sc16is752_spi_context *) base;
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spi_ioc_transfer msg[2];
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uint8_t unused[SC16IS752_FIFO_DEPTH];
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uint8_t tx_cmd;
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_Assert(len < RTEMS_ARRAY_SIZE(unused));
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msg_init(&msg[0], ctx->cs, ctx->speed_hz, 1, &unused[0], &tx_cmd);
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msg_init(&msg[1], ctx->cs, ctx->speed_hz, len, &unused[0], &data[0]);
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tx_cmd = addr << 3;
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msg[1].cs_change = 1;
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return ioctl(ctx->fd, SPI_IOC_MESSAGE(2), &msg[0]);
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}
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static int sc16is752_spi_read_reg(
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sc16is752_context *base,
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uint8_t addr,
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uint8_t *data,
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size_t len
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)
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{
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sc16is752_spi_context *ctx = (sc16is752_spi_context *) base;
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spi_ioc_transfer msg[2];
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uint8_t unused;
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uint8_t tx_cmd;
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uint8_t tx_buf[SC16IS752_FIFO_DEPTH];
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_Assert(len < RTEMS_ARRAY_SIZE(tx_buf));
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msg_init(&msg[0], ctx->cs, ctx->speed_hz, 1, &unused, &tx_cmd);
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msg_init(&msg[1], ctx->cs, ctx->speed_hz, len, &data[0], &tx_buf[0]);
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tx_cmd = 0x80 | (addr << 3);
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msg[1].cs_change = 1;
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return ioctl(ctx->fd, SPI_IOC_MESSAGE(2), &msg[0]);
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}
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static int sc16is752_spi_read_2_reg(
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sc16is752_context *base,
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uint8_t addr_0,
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uint8_t addr_1,
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uint8_t data[2]
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)
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{
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sc16is752_spi_context *ctx = (sc16is752_spi_context *) base;
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spi_ioc_transfer msg[4];
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uint8_t unused;
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uint8_t tx_cmd_0;
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uint8_t tx_cmd_1;
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msg_init(&msg[0], ctx->cs, ctx->speed_hz, 1, &unused, &tx_cmd_0);
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msg_init(&msg[1], ctx->cs, ctx->speed_hz, 1, &data[0], &unused);
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msg_init(&msg[2], ctx->cs, ctx->speed_hz, 1, &unused, &tx_cmd_1);
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msg_init(&msg[3], ctx->cs, ctx->speed_hz, 1, &data[1], &unused);
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tx_cmd_0 = 0x80 | (addr_0 << 3);
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tx_cmd_1 = 0x80 | (addr_1 << 3);
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msg[1].cs_change = 1;
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msg[3].cs_change = 1;
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return ioctl(ctx->fd, SPI_IOC_MESSAGE(4), &msg[0]);
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}
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static bool sc16is752_spi_first_open(sc16is752_context *base)
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{
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sc16is752_spi_context *ctx = (sc16is752_spi_context *) base;
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ctx->fd = open(ctx->spi_path, O_RDWR);
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return ctx->fd >= 0;
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}
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static void sc16is752_spi_last_close(sc16is752_context *base)
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{
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sc16is752_spi_context *ctx = (sc16is752_spi_context *) base;
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close(ctx->fd);
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}
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rtems_status_code sc16is752_spi_create(
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sc16is752_spi_context *ctx,
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const char *device_path
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)
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{
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ctx->base.write_reg = sc16is752_spi_write_reg;
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ctx->base.read_reg = sc16is752_spi_read_reg;
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ctx->base.read_2_reg = sc16is752_spi_read_2_reg;
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ctx->base.first_open = sc16is752_spi_first_open;
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ctx->base.last_close = sc16is752_spi_last_close;
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return rtems_termios_device_install(
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device_path,
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&sc16is752_termios_handler,
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NULL,
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&ctx->base.base
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);
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}
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