mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-23 16:02:05 +08:00
riscv: add bsp for beagle v fire
Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
This commit is contained in:
Francescodario Cuzzocrea
committed by
Gedare Bloom
Gedare Bloom
parent
0e3792edbf
commit
9d45cf1b44
@@ -0,0 +1,9 @@
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include $(RTEMS_ROOT)/make/custom/default.cfg
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RTEMS_CPU = riscv
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CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
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LDFLAGS = -Wl,--gc-sections
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CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
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@@ -0,0 +1,364 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) Francescodario Cuzzocrea <bosconovic@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "BeagleBoard BeagleV-Fire";
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compatible = "beagle,beaglev-fire", "microchip,mpfs";
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aliases {
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serial0 = &uart0;
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ethernet0 = &emac1;
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};
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chosen {
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stdout-path = "serial0";
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};
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cpucomplex: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu0: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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cpu0intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu1intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu2intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu3intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu4intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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clock-output-names = "msspllclk";
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};
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ddr: memory@1000000000 {
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device_type = "memory";
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reg = <0x00000010 0x00000000 0x00000000 0x10000000>;
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};
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "microchip,mpfs-soc", "simple-bus";
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ranges;
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clint0: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&cpu0intc 3 &cpu0intc 7
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&cpu1intc 3 &cpu1intc 7
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&cpu2intc 3 &cpu2intc 7
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&cpu3intc 3 &cpu3intc 7
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&cpu4intc 3 &cpu4intc 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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reg-names = "control";
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clock-frequency = <1000000>;
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};
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cachecontroller: cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <1 2 3>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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};
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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riscv,max-priority = <7>;
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riscv,ndev = <186>;
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interrupt-controller;
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interrupts-extended = <
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&cpu0intc 11
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&cpu1intc 11 &cpu1intc 9
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&cpu2intc 11 &cpu2intc 9
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&cpu3intc 11 &cpu3intc 9
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&cpu4intc 11 &cpu4intc 9>;
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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reg-names = "mss_sysreg";
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clocks = <&refclk>;
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#clock-cells = <1>;
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clock-output-names = "cpu", "axi", "ahb", "envm",
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"mac0", "mac1", "mmc", "timer",
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"mmuart0", "mmuart1", "mmuart2",
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"mmuart3", "mmuart4", "spi0", "spi1",
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"i2c0", "i2c1", "can0", "can1", "usb",
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"reserved", "rtc", "qspi", "gpio0",
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"gpio1", "gpio2", "ddrc", "fic0",
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"fic1", "fic2", "fic3", "athena",
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"cfm";
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};
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/* Common node entry for eMMC/SD */
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mmc: mmc@20008000 {
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compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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clocks = <&clkcfg 6>;
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interrupt-parent = <&plic>;
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interrupts = <88 89>;
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max-frequency = <200000000>;
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bus-width = <4>;
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disable-wp;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "disabled";
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};
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uart0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <90>;
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clock-frequency = <150000000>;
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clocks = <&clkcfg 8>;
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status = "okay";
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};
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spi0: spi@20108000 {
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compatible = "microchip,mpfs-spi";
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reg = <0x0 0x20108000 0x0 0x1000>;
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clocks = <&clkcfg 13>;
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interrupt-parent = <&plic>;
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interrupts = <54>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@2010b000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,mpfs-i2c";
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reg = <0x0 0x2010b000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <61>;
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clocks = <&clkcfg 16>;
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clock-frequency = <100000>;
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status = "okay";
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pac193x@10 {
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compatible = "microchip,pac1934";
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reg = <0x10>;
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samp-rate = <64>;
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status = "disabled";
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ch1: channel0 {
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uohms-shunt-res = <10000>;
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rail-name = "VDD";
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channel_enabled;
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};
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ch2: channel1 {
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uohms-shunt-res = <10000>;
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rail-name = "VDDA25";
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channel_enabled;
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};
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ch3: channel2 {
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uohms-shunt-res = <10000>;
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rail-name = "VDD25";
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channel_enabled;
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};
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ch4: channel3 {
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uohms-shunt-res = <10000>;
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rail-name = "VDDA";
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channel_enabled;
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};
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};
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};
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emac1: ethernet@20112000 {
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compatible = "microchip,mpfs-macb","cdns,gem";
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reg = <0x0 0x20112000 0x0 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <70 71 72 73>;
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local-mac-address = [00 04 A3 00 00 02];
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phy-mode = "sgmii";
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clocks = <&clkcfg 5>, <&clkcfg 1>;
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clock-names = "pclk", "hclk";
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clock-frequency = <150000000>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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phy-handle = <&phy1>;
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phy1: ethernet-phy@9 {
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reg = <9>;
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};
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};
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gpio: gpio@20122000 {
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compatible = "microchip,mpfs-gpio";
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interrupt-parent = <&plic>;
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interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
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27 28 29 30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44>;
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gpio-controller;
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clocks = <&clkcfg 25>;
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reg = <0x00 0x20122000 0x0 0x1000>;
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reg-names = "control";
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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};
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File diff suppressed because it is too large
Load Diff
@@ -7,6 +7,7 @@ copyrights:
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- Copyright (C) 2020 embedded brains GmbH & Co. KG
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default:
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- enabled-by:
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- riscv/bvf
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- riscv/mpfs64imafdc
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- riscv/kendrytek210
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value: true
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@@ -6,6 +6,8 @@ build-type: option
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copyrights:
|
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- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
|
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default:
|
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- enabled-by: riscv/bvf
|
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value: bsp/bvf.h
|
||||
- enabled-by: riscv/mpfs64imafdc
|
||||
value: bsp/mpfs-dtb.h
|
||||
- enabled-by: riscv/kendrytek210
|
||||
|
||||
@@ -6,6 +6,8 @@ build-type: option
|
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copyrights:
|
||||
- Copyright (C) 2020 embedded brains GmbH & Co. KG
|
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default:
|
||||
- enabled-by: riscv/bvf
|
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value: 187
|
||||
- enabled-by: riscv/mpfs64imafdc
|
||||
value: 187
|
||||
- enabled-by: true
|
||||
|
||||
@@ -18,6 +18,8 @@ default:
|
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value: 0x00000000
|
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- enabled-by: riscv/griscv
|
||||
value: 0x40000000
|
||||
- enabled-by: riscv/bvf
|
||||
value: 0x1000000000
|
||||
- enabled-by: riscv/mpfs64imafdc
|
||||
value: 0x1000000000
|
||||
- enabled-by: true
|
||||
|
||||
@@ -10,6 +10,7 @@ copyrights:
|
||||
- Copyright (C) 2020 embedded brains GmbH & Co. KG
|
||||
default:
|
||||
- enabled-by:
|
||||
- riscv/bvf
|
||||
- riscv/frdme310arty
|
||||
- riscv/mpfs64imafdc
|
||||
value: 0x10000000
|
||||
|
||||
@@ -8,6 +8,7 @@ copyrights:
|
||||
- Copyright (C) 2020 embedded brains GmbH & Co. KG
|
||||
default:
|
||||
- enabled-by:
|
||||
- riscv/bvf
|
||||
- riscv/mpfs64imafdc
|
||||
- riscv/rv64imafdc
|
||||
- riscv/kendrytek210
|
||||
|
||||
@@ -0,0 +1,19 @@
|
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SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
|
||||
arch: riscv
|
||||
bsp: bvf
|
||||
build-type: bsp
|
||||
cflags: []
|
||||
copyrights:
|
||||
- Copyright (C) 2020 embedded brains GmbH & Co. KG
|
||||
cppflags: []
|
||||
enabled-by: true
|
||||
family: riscv
|
||||
includes: []
|
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install: []
|
||||
links:
|
||||
- role: build-dependency
|
||||
uid: ../../opto2
|
||||
- role: build-dependency
|
||||
uid: grp
|
||||
source: []
|
||||
type: build
|
||||
@@ -6,6 +6,8 @@ build-type: option
|
||||
copyrights:
|
||||
- Copyright (C) 2020 embedded brains GmbH & Co. KG
|
||||
default:
|
||||
- enabled-by: riscv/bvf
|
||||
value: true
|
||||
- enabled-by: riscv/mpfs64imafdc
|
||||
value: true
|
||||
- enabled-by: true
|
||||
|
||||
@@ -10,6 +10,8 @@ default:
|
||||
- riscv/frdme310arty
|
||||
- riscv/kendrytek210
|
||||
value: null
|
||||
- enabled-by: riscv/bvf
|
||||
value: 1
|
||||
- enabled-by: riscv/mpfs64imafdc
|
||||
value: 1
|
||||
- enabled-by: true
|
||||
|
||||
@@ -8,6 +8,7 @@ copyrights:
|
||||
- Copyright (C) 2020 Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk>
|
||||
default:
|
||||
- enabled-by:
|
||||
- riscv/bvf
|
||||
- riscv/mpfs64imafdc
|
||||
- riscv/noel64imac
|
||||
- riscv/noel64imafd
|
||||
|
||||
@@ -6,6 +6,8 @@ build-type: option
|
||||
copyrights:
|
||||
- Copyright (C) 2020 embedded brains GmbH & Co. KG
|
||||
default:
|
||||
- enabled-by: riscv/bvf
|
||||
value: 1
|
||||
- enabled-by: riscv/mpfs64imafdc
|
||||
value: 1
|
||||
- enabled-by: true
|
||||
|
||||
@@ -28,6 +28,7 @@ enabled-by:
|
||||
- powerpc/qoriq_e500
|
||||
- powerpc/qoriq_e6500_32
|
||||
- powerpc/qoriq_e6500_64
|
||||
- riscv/bvf
|
||||
- riscv/griscv
|
||||
- riscv/grv32imac
|
||||
- riscv/grv32imafdc
|
||||
|
||||
Reference in New Issue
Block a user