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Add the i2c driver for Beaglebone Black
Update ticket #2891 and my GSOC project add c/src/lib/libbsp/arm/beagle/i2c/bbb-i2c.c modify c/src/lib/libbsp/arm/beagle/include/i2c.h modify c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h modify c/src/lib/libcpu/arm/shared/include/am335x.h modify c/src/lib/libbsp/arm/beagle/Makefile.am Now can read the EEPROM by i2c, the test application link is: https://github.com/hahchenchen/GSOC-test-application
This commit is contained in:
Sichen Zhao authored and 
Joel Sherrill committed
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commit
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5 files changed
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-128
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@@ -114,6 +114,7 @@ libbsp_a_SOURCES += ../../shared/console.c \
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../../shared/console_control.c
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# I2C
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libbsp_a_SOURCES += i2c/bbb-i2c.c
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# GPIO
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libbsp_a_SOURCES += gpio/bbb-gpio.c
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@@ -35,9 +35,11 @@ extern "C" {
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#define BBB_PU_EN (1 << 4)
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#define BBB_PD_EN ~BBB_PU_EN
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#define BBB_MUXMODE(X) (X & 0x7)
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#define BBB_RXACTIVE (1 << 5)
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#define BBB_SLEWCTRL (1 << 6)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */
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#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */
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@@ -563,3 +563,139 @@
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/* I2C registers */
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#define AM335X_I2C0_BASE 0x44e0b000
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/* I2C0 base address */
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#define AM335X_I2C1_BASE 0x4802a000
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/* I2C1 base address */
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#define AM335X_I2C2_BASE 0x4819c000
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/* I2C2 base address */
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#define AM335X_I2C_REVNB_LO 0x00
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/* Module Revision Register (low bytes) */
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#define AM335X_I2C_REVNB_HI 0x04
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/* Module Revision Register (high bytes) */
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#define AM335X_I2C_SYSC 0x10
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/* System Configuration Register */
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#define AM335X_I2C_IRQSTATUS_RAW 0x24
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/* I2C Status Raw Register */
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#define AM335X_I2C_IRQSTATUS 0x28
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/* I2C Status Register */
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#define AM335X_I2C_IRQENABLE_SET 0x2c
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/* I2C Interrupt Enable Set Register */
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#define AM335X_I2C_IRQENABLE_CLR 0x30
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/* I2C Interrupt Enable Clear Register */
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#define AM335X_I2C_WE 0x34
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/* I2C Wakeup Enable Register */
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#define AM335X_I2C_DMARXENABLE_SET 0x38
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/* Receive DMA Enable Set Register */
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#define AM335X_I2C_DMATXENABLE_SET 0x3c
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/* Transmit DMA Enable Set Register */
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#define AM335X_I2C_DMARXENABLE_CLR 0x40
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/* Receive DMA Enable Clear Register */
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#define AM335X_I2C_DMATXENABLE_CLR 0x44
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/* Transmit DMA Enable Clear Register */
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#define AM335X_I2C_DMARXWAKE_EN 0x48
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/* Receive DMA Wakeup Register */
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#define AM335X_I2C_DMATXWAKE_EN 0x4c
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/* Transmit DMA Wakeup Register */
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#define AM335X_I2C_SYSS 0x90
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/* System Status Register */
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#define AM335X_I2C_BUF 0x94
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/* Buffer Configuration Register */
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#define AM335X_I2C_CNT 0x98
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/* Data Counter Register */
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#define AM335X_I2C_DATA 0x9c
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/* Data Access Register */
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#define AM335X_I2C_CON 0xa4
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/* I2C Configuration Register */
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#define AM335X_I2C_OA 0xa8
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/* I2C Own Address Register */
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#define AM335X_I2C_SA 0xac
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/* I2C Slave Address Register */
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#define AM335X_I2C_PSC 0xb0
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/* I2C Clock Prescaler Register */
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#define AM335X_I2C_SCLL 0xb4
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/* I2C SCL Low Time Register */
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#define AM335X_I2C_SCLH 0xb8
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/* I2C SCL High Time Register */
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#define AM335X_I2C_SYSTEST 0xbc
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/* System Test Register */
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#define AM335X_I2C_BUFSTAT 0xc0
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/* I2C Buffer Status Register */
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#define AM335X_I2C_OA1 0xc4
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/* I2C Own Address 1 Register */
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#define AM335X_I2C_OA2 0xc8
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/* I2C Own Address 2 Register */
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#define AM335X_I2C_OA3 0xcc
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/* I2C Own Address 3 Register */
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#define AM335X_I2C_ACTOA 0xd0
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/* Active Own Address Register */
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#define AM335X_I2C_SBLOCK 0xd4
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/* I2C Clock Blocking Enable Register */
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#define AM335X_CM_PER_L4LS_CLKSTCTRL (0x0)
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#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
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#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x00000003u)
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#define AM335X_CM_PER_L4LS_CLKCTRL (0x60)
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#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_PER_I2C1_CLKCTRL (0x48)
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#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_PER_I2C2_CLKCTRL (0x44)
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#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
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#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
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#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_I2C_CON_XSA (0x00000100u)
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#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR AM335X_I2C_CON_XSA
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#define AM335X_I2C_CON_XSA_SHIFT (0x00000008u)
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#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR (0 << AM335X_I2C_CON_XSA_SHIFT)
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#define AM335X_I2C_CON_I2C_EN (0x00008000u)
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#define AM335X_I2C_CON_TRX (0x00000200u)
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#define AM335X_I2C_CON_MST (0x00000400u)
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#define AM335X_I2C_CON_STB (0x00000800u)
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#define AM335X_I2C_SYSC_AUTOIDLE (0x00000001u)
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/*I2C0 module clock registers*/
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#define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4)
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#define AM335X_CM_WKUP_CLKSTCTRL (0x0)
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#define AM335X_CM_WKUP_I2C0_CLKCTRL (0xb8)
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#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC (0x0u)
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#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT (0x00000010u)
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#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST (0x00030000u)
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#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK (0x00000800u)
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#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC (0x0u)
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#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
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#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST (0x00030000u)
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#define AM335X_SOC_CM_WKUP_REGS (AM335X_CM_PER_ADDR + 0x400)
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/* I2C status Register */
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#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
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#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
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#define AM335X_I2C_IRQSTATUS_AL (1<<0)
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#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
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#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
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#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
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#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
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#define AM335X_I2C_BUF_TXFIFO_CLR (0x00000040u)
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#define AM335X_I2C_BUF_RXFIFO_CLR (0x00004000u)
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#define AM335X_I2C_IRQSTATUS_AAS (1 << 9)
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#define AM335X_I2C_IRQSTATUS_BF (1 << 8)
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#define AM335X_I2C_IRQSTATUS_STC (1 << 6)
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#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
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#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
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#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
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#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
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#define AM335X_I2C_CON_STOP (0x00000002u)
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#define AM335X_I2C_CON_START (0x00000001u)
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#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
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#define AM335X_I2C_CFG_MST_TX (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
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#define AM335X_I2C_IRQSTATUS_RAW_BB (0x00001000u)
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#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
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#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
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