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Patch rtems-rc-19991203-5.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>

Browse Source 
which cleans up and merges some Hitachi SH-2 modifications from
John Mills <jmills@tga.com>.
This commit is contained in:
Joel Sherrill
1999-12-21 14:27:52 +00:00
parent 3ad7602ef2
commit 8b9128277d
8 changed files with 253 additions and 171 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/exec/score/cpu/sh/rtems/score/iosh7045.h
+1 -1
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@@ -307,7 +307,7 @@
#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
/*Compare/Match Timer*/
#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
c/src/lib/libbsp/sh/gensh2/startup/bspstart.c
+4
View File
@@ -91,7 +91,11 @@ void bsp_start(void)
Depending on the board this can ether be done from inside the rom
startup code, rtems startup code or here.
*/
#ifndef START_HW_INIT
/* board hardware setup here, or from 'start.S' */
hw_initialize();
#endif
/*
* Allocate the memory for the RTEMS Work Space. This can come from
c/src/lib/libbsp/sh/gensh2/startup/hw_init.c
+8 -35
View File
@@ -1,5 +1,7 @@
/*
* hw_init.c: set up sh7045F internal subunits
* Pin and memory assignments assume
* target is Hitachi SH7045F EVB ("lcevb")
*
* Author: John M. Mills (jmills@tga.com)
* COPYRIGHT(c) 1999, TGA Technologies, Inc
@@ -69,6 +71,8 @@ void hw_initialize (void)
unsigned16 temp16;
#ifdef STANDALONE_EVB
/* FIXME: replace 'magic numbers' */
write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */
write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/
write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */
@@ -89,22 +93,11 @@ void hw_initialize (void)
write16(0x0000, PFC_IFCR); /* Pin function controller - default */
write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */
/* SCI0 */
/* FIXME: This doesn't belong here */
write8(0x00, SCI_SCR0); /* Clear SCR */
write8(0x00, SCI_SMR0); /* Clear SMR */
write8(0x5F, SCI_BRR0); /* Default 9600 baud rate */
#if 0
write8(0x1F, SCI_BRR0); /* 28800 baud */
#endif
/* FIXME: Will get optimized away */
for(a=0;a<00000L;a++); /* One bit delay */
write8(0x30, SCI_SCR0); /* Enable clock output */
temp8 = read8(SCI_RDR0); /* Clear out old input */
write16(0x00, PFC_PACRL2); /* default disconnects all I/O */
/* pins; connected by DEVICE_open() */
#endif
/* default hardware setup */
/* default hardware setup for SH7045F EVB */
/* PFC: General I/O except pin 13 (reset): */
temp16 = read16(PFC_PECR1) | 0x0800;
@@ -113,28 +106,8 @@ void hw_initialize (void)
/* All I/O lines bits 7-0: */
write16(0x00, PFC_PECR2);
/* P5 out, all other pins in: */
/* P5 (LED) out, all other pins in: */
temp16 = read16(PFC_PEIOR) | 0x0020;
write16(temp16, PFC_PEIOR);
/* PFC - pins for Tx0-1, Rx0-1: */
temp16 = read16(PFC_PACRL2) | 0x0145;
write16(temp16, PFC_PACRL2);
/* SCI1 - Default RTEMS console */
#if FIXME
/* write8(0x00, SCI_SCR1); /* Clear SCR */
/* write8(0x00, SCI_SMR1); /* Clear SMR */
/* write8(0x5F, SCI_BRR1); /* Default 9600 baud rate */
/* write8(0x1F, SCI_BRR1); /* 28800 baud */
/* FIXME: Will get optimized away */
/* for(a=0;a<10000L;a++); /* One bit delay */
/* write8(0x30, SCI_SCR1); /* Enable clock output */
/* temp8 = read8(SCI_RDR1); /* Clear out old input */
/* INTC setup */
/* set_interrupt_mask(0); /* enable interrupts */
/* INTC_IPRF &= ~(SCI1_IPMSK); /* set SIO1 priority at INTC */
/* INTC_IPRF |= SCI1_LOWIP; */
#endif
}
c/src/lib/libcpu/sh/sh7045/include/io_types.h
+15 -15
View File
@@ -16,15 +16,15 @@
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
* $Id$
*
@@ -43,13 +43,13 @@ typedef enum {one, two} stopBits;
typedef enum {even, odd} parity;
typedef struct {
portNo line;
int speed_ix;
dataBits dBits;
int parEn;
parity par;
int mulPro;
stopBits sBits;
portNo line;
int speed_ix;
dataBits dBits;
int parEn;
parity par;
int mulPro;
stopBits sBits;
} sci_setup_t;
typedef union{
c/src/lib/libcpu/sh/sh7045/include/iosh7045.h
+1 -1
View File
@@ -307,7 +307,7 @@
#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
/*Compare/Match Timer*/
#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h
+158 -71
View File
@@ -29,90 +29,177 @@
#include <rtems/score/iosh7045.h>
/*
* Port A IO Registers (PAIORH, PAIORL)
* 1 => OUTPUT
* 0 => INPUT
*/
#define PAIORH PFC_PAIORH
#define PAIORL PFC_PAIORL
/* PAIORH */
#define PA23IOR 0x0080
#define PA22IOR 0x0040
#define PA21IOR 0x0020
#define PA20IOR 0x0010
#define PA19IOR 0x0008
#define PA18IOR 0x0004
#define PA17IOR 0x0002
#define PA16IOR 0x0001
/* PAIORL */
#define PA15IOR 0x8000
#define PA14IOR 0x4000
#define PA13IOR 0x2000
#define PA12IOR 0x1000
#define PA11IOR 0x0800
#define PA10IOR 0x0400
#define PA9IOR 0x0200
#define PA8IOR 0x0100
#define PA7IOR 0x0080
#define PA6IOR 0x0040
#define PA5IOR 0x0020
#define PA4IOR 0x0010
#define PA3IOR 0x0008
#define PA2IOR 0x0004
#define PA1IOR 0x0002
#define PA0IOR 0x0001
/*
* Port A Control Registers (PACRH, PACRL1, PACRL2)
* and mode bits
*/
#define PACRH PFC_PACRH
#define PACRL1 PFC_PACRL1
#define PACRL2 PFC_PACRL2
/* PACRH */
#define PA23MD0 0x4000
#define PA22MD0 0x1000
#define PA21MD0 0x0400
#define PA20MD0 0x0100
#define PA19MD1 0x0080
#define PA19MD0 0x0040
#define PA18MD1 0x0020
#define PA18MD0 0x0010
#define PA17MD0 0x0004
#define PA16MD0 0x0001
/* PACRL1 */
#define PA15MD0 0x4000
#define PA14MD0 0x1000
#define PA13MD0 0x0400
#define PA12MD0 0x0100
#define PA11MD0 0x0040
#define PA10MD0 0x0010
#define PA9MD1 0x0008
#define PA9MD0 0x0004
#define PA8MD1 0x0002
#define PA8MD0 0x0001
/* PACRL2 */
#define PA7MD1 0x8000
#define PA7MD0 0x4000
#define PA6MD1 0x2000
#define PA6MD0 0x1000
#define PA5MD1 0x0800
#define PA5MD0 0x0400
#define PA4MD0 0x0100
#define PA3MD0 0x0040
#define PA2MD1 0x0020
#define PA2MD0 0x0010
#define PA1MD0 0x0004
#define PA0MD0 0x0001
#define PA_TXD1 PA4MD0
#define PA_RXD1 PA3MD0
#define PA_TXD0 PA1MD0
#define PA_RXD0 PA0MD0
/*
* Port B IO Register (PBIOR)
*/
#define PBIOR PFC_PBIOR
#define PB15IOR 0x8000
#define PB14IOR 0x4000
#define PB13IOR 0x2000
#define PB12IOR 0x1000
#define PB11IOR 0x0800
#define PB10IOR 0x0400
#define PB9IOR 0x0200
#define PB8IOR 0x0100
#define PB7IOR 0x0080
#define PB6IOR 0x0040
#define PB5IOR 0x0020
#define PB4IOR 0x0010
#define PB3IOR 0x0008
#define PB2IOR 0x0004
#define PB1IOR 0x0002
#define PB0IOR 0x0001
#define PBIOR PFC_PBIOR
#define PB15IOR 0x8000
#define PB14IOR 0x4000
#define PB13IOR 0x2000
#define PB12IOR 0x1000
#define PB11IOR 0x0800
#define PB10IOR 0x0400
#define PB9IOR 0x0200
#define PB8IOR 0x0100
#define PB7IOR 0x0080
#define PB6IOR 0x0040
#define PB5IOR 0x0020
#define PB4IOR 0x0010
#define PB3IOR 0x0008
#define PB2IOR 0x0004
#define PB1IOR 0x0002
#define PB0IOR 0x0001
/*
* Port B Control Register (PBCR1)
*/
#define PBCR1 PFC_PBCR1
#define PB15MD1 0x8000
#define PB15MD0 0x4000
#define PB14MD1 0x2000
#define PB14MD0 0x1000
#define PB13MD1 0x0800
#define PB13MD0 0x0400
#define PB12MD1 0x0200
#define PB12MD0 0x0100
#define PB11MD1 0x0080
#define PB11MD0 0x0040
#define PB10MD1 0x0020
#define PB10MD0 0x0010
#define PB9MD1 0x0008
#define PB9MD0 0x0004
#define PB8MD1 0x0002
#define PB8MD0 0x0001
#define PBCR1 PFC_PBCR1
#define PB15MD1 0x8000
#define PB15MD0 0x4000
#define PB14MD1 0x2000
#define PB14MD0 0x1000
#define PB13MD1 0x0800
#define PB13MD0 0x0400
#define PB12MD1 0x0200
#define PB12MD0 0x0100
#define PB11MD1 0x0080
#define PB11MD0 0x0040
#define PB10MD1 0x0020
#define PB10MD0 0x0010
#define PB9MD1 0x0008
#define PB9MD0 0x0004
#define PB8MD1 0x0002
#define PB8MD0 0x0001
#define PB15MD PB15MD1|PB14MD0
#define PB14MD PB14MD1|PB14MD0
#define PB13MD PB13MD1|PB13MD0
#define PB12MD PB12MD1|PB12MD0
#define PB11MD PB11MD1|PB11MD0
#define PB10MD PB10MD1|PB10MD0
#define PB9MD PB9MD1|PB9MD0
#define PB8MD PB8MD1|PB8MD0
#define PB15MD PB15MD1|PB14MD0
#define PB14MD PB14MD1|PB14MD0
#define PB13MD PB13MD1|PB13MD0
#define PB12MD PB12MD1|PB12MD0
#define PB11MD PB11MD1|PB11MD0
#define PB10MD PB10MD1|PB10MD0
#define PB9MD PB9MD1|PB9MD0
#define PB8MD PB8MD1|PB8MD0
#define PB_TXD1 PB11MD1
#define PB_RXD1 PB10MD1
#define PB_TXD0 PB9MD1
#define PB_RXD0 PB8MD1
#define PB_TXD1 PB11MD1
#define PB_RXD1 PB10MD1
#define PB_TXD0 PB9MD1
#define PB_RXD0 PB8MD1
/*
* Port B Control Register (PBCR2)
*/
#define PBCR2 PFC_PBCR2
#define PB7MD1 0x8000
#define PB7MD0 0x4000
#define PB6MD1 0x2000
#define PB6MD0 0x1000
#define PB5MD1 0x0800
#define PB5MD0 0x0400
#define PB4MD1 0x0200
#define PB4MD0 0x0100
#define PB3MD1 0x0080
#define PB3MD0 0x0040
#define PB2MD1 0x0020
#define PB2MD0 0x0010
#define PB1MD1 0x0008
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PBCR2 PFC_PBCR2
#define PB7MD1 0x8000
#define PB7MD0 0x4000
#define PB6MD1 0x2000
#define PB6MD0 0x1000
#define PB5MD1 0x0800
#define PB5MD0 0x0400
#define PB4MD1 0x0200
#define PB4MD0 0x0100
#define PB3MD1 0x0080
#define PB3MD0 0x0040
#define PB2MD1 0x0020
#define PB2MD0 0x0010
#define PB1MD1 0x0008
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
#define PB4MD PB4MD1|PB4MD0
#define PB3MD PB3MD1|PB3MD0
#define PB2MD PB2MD1|PB2MD0
#define PB1MD PB1MD1|PB1MD0
#define PB0MD PB0MD1|PB0MD0
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
#define PB4MD PB4MD1|PB4MD0
#define PB3MD PB3MD1|PB3MD0
#define PB2MD PB2MD1|PB2MD0
#define PB1MD PB1MD1|PB1MD0
#define PB0MD PB0MD1|PB0MD0
#endif /* _sh7_pfc_h */
c/src/lib/libcpu/sh/sh7045/sci/sci.c
+60 -48
View File
@@ -119,7 +119,9 @@ void sh_sci_outbyte_polled(
while (wrtSCI1(ch) != TRUE); /* SCI1*/
} /* sh_sci_outbyte_polled */
/* Initial version calls polled output driver and blocks */
/*
* Initial version calls polled output driver and blocks
*/
void outbyte(
rtems_device_minor_number minor,
char ch)
@@ -186,13 +188,16 @@ char inbyte(
/* sh_sci_initialize
*
* This routine initializes the sh_sci IO driver.
* This routine initializes (registers) the sh_sci IO drivers.
*
* Input parameters: NONE
* Input parameters: ignored
*
* Output parameters: NONE
*
* Return values:
* Return values: RTEMS_SUCCESSFUL
* if all sci[...] register, else calls
* rtems_fatal_error_occurred(status)
*
*/
rtems_device_driver sh_sci_initialize(
@@ -200,39 +205,34 @@ rtems_device_driver sh_sci_initialize(
rtems_device_minor_number minor,
void *arg )
{
int a;
unsigned16 temp16;
rtems_device_driver status ;
rtems_device_minor_number i;
/*
* register all possible devices.
* the initialization of the hardware is done by sci_open
*/
/* register devices */
for ( a = 0 ; a < 2 ; a++ )
for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ )
{
status = rtems_io_register_name(
sci_device[a].name,
sci_device[i].name,
major,
sci_device[a].minor );
sci_device[i].minor );
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
}
/* default hardware setup */
/* non-default hardware setup occurs in sh_sci_open() */
/* general setup */
temp16 = read16(PFC_PECR1) | 0x0800; /* General I/O except pin 13 (reset) */
write16(temp16, PFC_PECR1);
write16(0x00, PFC_PECR2); /* All I/O lines bits 7-0 */
temp16 = read16(PFC_PEIOR) | 0x0020; /* P5 to out, all other pins in */
write16(temp16, PFC_PEIOR);
temp16 = read16(PFC_PACRL2) | 0x0145; /* PFC - pins for Tx0-1, Rx0-1 */
write16(temp16, PFC_PACRL2);
return RTEMS_SUCCESSFUL;
}
/*
* Open entry point
* Sets up port and pins for selected sci.
* SCI0 setup is conditional on STANDALONE_EVB == 1
*/
rtems_device_driver sh_sci_open(
@@ -241,46 +241,58 @@ rtems_device_driver sh_sci_open(
void * arg )
{
unsigned8 temp8;
unsigned16 temp16;
unsigned char smr ;
unsigned char brr ;
unsigned a ;
/* check for valid minor number */
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
/* retrieve brr and smr values */
_sci_get_brparms( sci_device[minor].cflags, &smr, &brr );
if (minor == 0) {
write8(0x00, SCI_SCR0); /* Clear SCR */
write8(smr, SCI_SMR0); /* Clear SMR */
write8(brr, SCI_BRR0); /* Default 9600 baud rate */
#if 0
write8(0x1F, SCI_BRR0); /* 28800 baud */
#endif
/* FIXME: Will get optimized away */
for(a=0;a<10000L;a++); /* One bit delay */
write8(0x30, SCI_SCR0); /* Enable clock output */
temp8 = read8(SCI_RDR0); /* Clear out old input */
/* enable I/O pins */
} else {
write8(0x00, SCI_SCR1); /* Clear SCR */
write8(smr, SCI_SMR1); /* Clear SMR */
write8(brr, SCI_BRR1); /* Default 9600 baud rate */
#if 0
write8(0x1F, SCI_BRR1); /* 28800 baud */
#endif
/* FIXME: Will get optimized away */
for(a=0;a<10000L;a++); /* One bit delay */
write8(0x30, SCI_SCR1); /* Enable clock output */
temp8 = read8(SCI_RDR1); /* Clear out old input */
}
if ((minor == 0) && (STANDALONE_EVB == 1)) {
temp16 = read16(PFC_PACRL2) & /* disable SCK0, Tx0, Rx0 */
~(PA2MD1 | PA2MD0 | PA1MD0 | PA0MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* assign pins for Tx0, Rx0 */
write16(temp16, PFC_PACRL2);
} else if (minor == 1) {
temp16 = read16(PFC_PACRL2) & /* disable SCK1, Tx1, Rx1 */
~(PA5MD1 | PA5MD0 | PA4MD0 | PA3MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* assign pins for Tx1, Rx1 */
write16(temp16, PFC_PACRL2);
} /* add other devices and pins as req'd. */
/* set up SCI registers */
if ((minor != 0) || (STANDALONE_EVB == 1)) {
write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
/* set SCR and BRR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
for(a=0; a < 10000L; a++) { /* One-bit delay */
asm volatile ("nop");
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
sci_device[minor].addr + SCI_SCR);
temp8 = read8(sci_device[minor].addr + SCI_RDR); /* flush input */
/* add interrupt setup if required */
}
sci_device[minor].opened++ ;
make/custom/gensh2.cfg
+6
View File
@@ -29,6 +29,7 @@ BSP_CPPFLAGS=-DHZ=$(HZ)
CPU_CFLAGS= -m2
# debug flags: typically none, but we use -O1 as it produces better code
CFLAGS_DEBUG_V = -O1
# optimize flag: typically -0, could use -O4 or -fast
@@ -50,12 +51,17 @@ CFLAGS_OPTIMIZE_V = -O4
# STANDALONE_EVB
# This switch compiles code to jump-start from FLASH, without a monitor
#
# START_HW_INIT
# This switch selects whether 'hw_initialize()' is called from
# 'start.S' or from 'bsp_start()'
#
define make-target-options
@echo "/* #define NDEBUG 1 */ " >>$@
@echo "#define RTEMS_TEST_NO_PAUSE 1" >>$@
@echo "#define RTEMS_TEST_IO_STREAM 1" >>$@
@echo "/* #define STANDALONE_EVB 1 */" >>$@
@echo "/* #define START_HW_INIT 1 */" >>$@
@echo "/* #define RTEMS_DEBUG 1 */" >>$@
endef