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2011-07-18 Joel Sherrill <joel.sherrill@oarcorp.com>

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* shared/irq/apic.h, shared/smp/smp-imps.c, shared/smp/smp-imps.h:
	Reformat to be more compliant with RTEMS style.
This commit is contained in:
Joel Sherrill
2011-07-18 16:33:30 +00:00
parent 2682dc9cac
commit 894a2c910a
4 changed files with 508 additions and 520 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libbsp/i386/ChangeLog
+5
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@@ -1,3 +1,8 @@
2011-07-18 Joel Sherrill <joel.sherrill@oarcorp.com>
* shared/irq/apic.h, shared/smp/smp-imps.c, shared/smp/smp-imps.h:
Reformat to be more compliant with RTEMS style.
2011-07-15 Joel Sherrill <joel.sherrill@oarcorp.com>
* shared/irq/apic.h, shared/smp/smp-imps.c, shared/smp/smp-imps.h: Per
c/src/lib/libbsp/i386/shared/irq/apic.h
+45 -46
View File
@@ -49,7 +49,7 @@
* it is DIFFERENT (0xF) for Pentium and P6, but not on the same APIC
* version for AMD Opteron.
*/
#define APIC_BCAST_ID 0xFF
#define APIC_BCAST_ID 0xFF
/*
* APIC register definitions
@@ -59,53 +59,52 @@
* Shared defines for I/O and local APIC definitions
*/
/* APIC version register */
#define APIC_VERSION(x) ((x) & 0xFF)
#define APIC_MAXREDIR(x) (((x) >> 16) & 0xFF)
#define APIC_VERSION(x) ((x) & 0xFF)
#define APIC_MAXREDIR(x) (((x) >> 16) & 0xFF)
/* APIC id register */
#define APIC_ID(x) ((x) >> 24)
#define APIC_VER_NEW 0x10
#define APIC_ID(x) ((x) >> 24)
#define APIC_VER_NEW 0x10
#define IOAPIC_REGSEL 0
#define IOAPIC_RW 0x10
#define IOAPIC_ID 0
#define IOAPIC_VER 1
#define IOAPIC_REDIR 0x10
#define IOAPIC_REGSEL 0
#define IOAPIC_RW 0x10
#define IOAPIC_ID 0
#define IOAPIC_VER 1
#define IOAPIC_REDIR 0x10
#define LAPIC_ID 0x20
#define LAPIC_VER 0x30
#define LAPIC_TPR 0x80
#define LAPIC_APR 0x90
#define LAPIC_PPR 0xA0
#define LAPIC_EOI 0xB0
#define LAPIC_LDR 0xD0
#define LAPIC_DFR 0xE0
#define LAPIC_SPIV 0xF0
#define LAPIC_SPIV_ENABLE_APIC 0x100
#define LAPIC_ISR 0x100
#define LAPIC_TMR 0x180
#define LAPIC_IRR 0x200
#define LAPIC_ESR 0x280
#define LAPIC_ICR 0x300
#define LAPIC_ICR_DS_SELF 0x40000
#define LAPIC_ICR_DS_ALLINC 0x80000
#define LAPIC_ICR_DS_ALLEX 0xC0000
#define LAPIC_ICR_TM_LEVEL 0x8000
#define LAPIC_ICR_LEVELASSERT 0x4000
#define LAPIC_ICR_STATUS_PEND 0x1000
#define LAPIC_ICR_DM_LOGICAL 0x800
#define LAPIC_ICR_DM_LOWPRI 0x100
#define LAPIC_ICR_DM_SMI 0x200
#define LAPIC_ICR_DM_NMI 0x400
#define LAPIC_ICR_DM_INIT 0x500
#define LAPIC_ICR_DM_SIPI 0x600
#define LAPIC_LVTT 0x320
#define LAPIC_LVTPC 0x340
#define LAPIC_LVT0 0x350
#define LAPIC_LVT1 0x360
#define LAPIC_LVTE 0x370
#define LAPIC_TICR 0x380
#define LAPIC_TCCR 0x390
#define LAPIC_TDCR 0x3E0
#define LAPIC_ID 0x20
#define LAPIC_VER 0x30
#define LAPIC_TPR 0x80
#define LAPIC_APR 0x90
#define LAPIC_PPR 0xA0
#define LAPIC_EOI 0xB0
#define LAPIC_LDR 0xD0
#define LAPIC_DFR 0xE0
#define LAPIC_SPIV 0xF0
#define LAPIC_SPIV_ENABLE_APIC 0x100
#define LAPIC_ISR 0x100
#define LAPIC_TMR 0x180
#define LAPIC_IRR 0x200
#define LAPIC_ESR 0x280
#define LAPIC_ICR 0x300
#define LAPIC_ICR_DS_SELF 0x40000
#define LAPIC_ICR_DS_ALLINC 0x80000
#define LAPIC_ICR_DS_ALLEX 0xC0000
#define LAPIC_ICR_TM_LEVEL 0x8000
#define LAPIC_ICR_LEVELASSERT 0x4000
#define LAPIC_ICR_STATUS_PEND 0x1000
#define LAPIC_ICR_DM_LOGICAL 0x800
#define LAPIC_ICR_DM_LOWPRI 0x100
#define LAPIC_ICR_DM_SMI 0x200
#define LAPIC_ICR_DM_NMI 0x400
#define LAPIC_ICR_DM_INIT 0x500
#define LAPIC_ICR_DM_SIPI 0x600
#define LAPIC_LVTT 0x320
#define LAPIC_LVTPC 0x340
#define LAPIC_LVT0 0x350
#define LAPIC_LVT1 0x360
#define LAPIC_LVTE 0x370
#define LAPIC_TICR 0x380
#define LAPIC_TCCR 0x390
#define LAPIC_TDCR 0x3E0
#endif /* _APIC_H */
c/src/lib/libbsp/i386/shared/smp/smp-imps.c
+396 -407
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File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/i386/shared/smp/smp-imps.h
+62 -67
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@@ -42,15 +42,15 @@
/* make sure "apic.h" is included */
#ifndef _APIC_H
#error Must include "apic.h" before "smp-imps.h"
#error Must include "apic.h" before "smp-imps.h"
#endif /* !_APIC_H */
/*
* Defines used.
*/
#define IMPS_READ(x) (*((volatile unsigned *) (x)))
#define IMPS_WRITE(x,y) (*((volatile unsigned *) (x)) = (y))
#define IMPS_READ(x) (*((volatile unsigned *) (x)))
#define IMPS_WRITE(x,y) (*((volatile unsigned *) (x)) = (y))
#ifdef IMPS_DEBUG
#define IMPS_DEBUG_PRINT(x) KERNEL_PRINT(x)
@@ -58,44 +58,44 @@
#define IMPS_DEBUG_PRINT(x)
#endif /* !IMPS_DEBUG */
#define IMPS_MAX_CPUS APIC_BCAST_ID
#define IMPS_MAX_CPUS APIC_BCAST_ID
/*
* This is the value that must be in the "sig" member of the MP
* Floating Pointer Structure.
*/
#define IMPS_FPS_SIGNATURE ('_' | ('M'<<8) | ('P'<<16) | ('_'<<24))
#define IMPS_FPS_IMCRP_BIT 0x80
#define IMPS_FPS_DEFAULT_MAX 7
#define IMPS_FPS_SIGNATURE ('_' | ('M'<<8) | ('P'<<16) | ('_'<<24))
#define IMPS_FPS_IMCRP_BIT 0x80
#define IMPS_FPS_DEFAULT_MAX 7
/*
* This is the value that must be in the "sig" member of the MP
* Configuration Table Header.
*/
#define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24))
#define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24))
/*
* These are the "type" values for Base MP Configuration Table entries.
*/
#define IMPS_FLAG_ENABLED 1
#define IMPS_BCT_PROCESSOR 0
#define IMPS_CPUFLAG_BOOT 2
#define IMPS_BCT_BUS 1
#define IMPS_BCT_IOAPIC 2
#define IMPS_BCT_IO_INTERRUPT 3
#define IMPS_BCT_LOCAL_INTERRUPT 4
#define IMPS_INT_INT 0
#define IMPS_INT_NMI 1
#define IMPS_INT_SMI 2
#define IMPS_INT_EXTINT 3
#define IMPS_FLAG_ENABLED 1
#define IMPS_BCT_PROCESSOR 0
#define IMPS_CPUFLAG_BOOT 2
#define IMPS_BCT_BUS 1
#define IMPS_BCT_IOAPIC 2
#define IMPS_BCT_IO_INTERRUPT 3
#define IMPS_BCT_LOCAL_INTERRUPT 4
#define IMPS_INT_INT 0
#define IMPS_INT_NMI 1
#define IMPS_INT_SMI 2
#define IMPS_INT_EXTINT 3
/*
* Typedefs and data item definitions done here.
*/
typedef struct imps_fps imps_fps; /* MP floating pointer structure */
typedef struct imps_cth imps_cth; /* MP configuration table header */
typedef struct imps_fps imps_fps; /* MP floating pointer structure */
typedef struct imps_cth imps_cth; /* MP configuration table header */
typedef struct imps_processor imps_processor;
typedef struct imps_bus imps_bus;
typedef struct imps_ioapic imps_ioapic;
@@ -114,12 +114,12 @@ typedef struct imps_interrupt imps_interrupt;
*/
struct imps_fps
{
unsigned sig;
imps_cth *cth_ptr;
unsigned char length;
unsigned char spec_rev;
unsigned char checksum;
unsigned char feature_info[5];
unsigned sig;
imps_cth *cth_ptr;
unsigned char length;
unsigned char spec_rev;
unsigned char checksum;
unsigned char feature_info[5];
};
/*
@@ -130,19 +130,19 @@ struct imps_fps
*/
struct imps_cth
{
unsigned sig;
unsigned short base_length;
unsigned char spec_rev;
unsigned char checksum;
char oem_id[8];
char prod_id[12];
unsigned oem_table_ptr;
unsigned short oem_table_size;
unsigned short entry_count;
unsigned lapic_addr;
unsigned short extended_length;
unsigned char extended_checksum;
char reserved[1];
unsigned sig;
unsigned short base_length;
unsigned char spec_rev;
unsigned char checksum;
char oem_id[8];
char prod_id[12];
unsigned oem_table_ptr;
unsigned short oem_table_size;
unsigned short entry_count;
unsigned lapic_addr;
unsigned short extended_length;
unsigned char extended_checksum;
char reserved[1];
};
/*
@@ -153,43 +153,42 @@ struct imps_cth
struct imps_processor
{
unsigned char type; /* must be 0 */
unsigned char apic_id;
unsigned char apic_ver;
unsigned char flags;
unsigned signature;
unsigned features;
char reserved[8];
unsigned char type; /* must be 0 */
unsigned char apic_id;
unsigned char apic_ver;
unsigned char flags;
unsigned signature;
unsigned features;
char reserved[8];
};
struct imps_bus
{
unsigned char type; /* must be 1 */
unsigned char id;
char bus_type[6];
unsigned char type; /* must be 1 */
unsigned char id;
char bus_type[6];
};
struct imps_ioapic
{
unsigned char type; /* must be 2 */
unsigned char id;
unsigned char ver;
unsigned char flags;
unsigned addr;
unsigned char type; /* must be 2 */
unsigned char id;
unsigned char ver;
unsigned char flags;
unsigned addr;
};
struct imps_interrupt
{
unsigned char type; /* must be 3 or 4 */
unsigned char int_type;
unsigned short flags;
unsigned char source_bus_id;
unsigned char source_bus_irq;
unsigned char dest_apic_id;
unsigned char dest_apic_intin;
unsigned char type; /* must be 3 or 4 */
unsigned char int_type;
unsigned short flags;
unsigned char source_bus_id;
unsigned char source_bus_irq;
unsigned char dest_apic_id;
unsigned char dest_apic_intin;
};
/*
* Exported globals here.
*/
@@ -216,7 +215,6 @@ extern int imps_num_cpus;
extern unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
/*
* This is the primary function for probing for Intel MPS 1.1/1.4
* compatible hardware and BIOS information. While probing the CPUs
@@ -229,21 +227,18 @@ extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
* Returns N if IMPS information was found (for number of CPUs started)
* and is valid, else 0.
*/
int imps_probe(void);
/*
* This one is used as a "force" function. Give it the number of CPUs
* to start, and it will assume a certain number and try it.
*/
int imps_force(int ncpus);
/*
* Defines that use variables
*/
#define IMPS_LAPIC_READ(x) (*((volatile unsigned *) (imps_lapic_addr+(x))))
#define IMPS_LAPIC_WRITE(x, y) \
(*((volatile unsigned *) (imps_lapic_addr+(x))) = (y))