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https://gitlab.rtems.org/rtems/rtos/rtems.git
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2007-12-05 Till Straumann <strauman@slac.stanford.edu>
* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h: Qualified all exception vector symbols that are only defined #ifdef <cpu_flavor> with <cpu_flavor> in the symbol name. If the special flavor __ppc_generic is effective the ALL vector symbols are available and ppc_vector_is_valid() works for all supported CPUs (run-time check). This is work towards a #ifdef <cpu_flavor> free libcpu and exception framework.
This commit is contained in:
Till Straumann
@@ -1,3 +1,14 @@
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2007-12-05 Till Straumann <strauman@slac.stanford.edu>
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* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h:
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Qualified all exception vector symbols that are only defined
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#ifdef <cpu_flavor> with <cpu_flavor> in the symbol name.
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If the special flavor __ppc_generic is effective the ALL
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vector symbols are available and ppc_vector_is_valid() works
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for all supported CPUs (run-time check).
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This is work towards a #ifdef <cpu_flavor> free libcpu and
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exception framework.
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2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>
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* mpc5xx/console-generic/console-generic.c, mpc8260/timer/timer.c,
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File diff suppressed because it is too large
Load Diff
@@ -31,6 +31,16 @@
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#define _LIBCPU_RAW_EXCEPTION_H
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#include <rtems/powerpc/powerpc.h>
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/* For now, many BSPs still rely on <cpu_flavor> being defined
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* but that should be phased out.
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* The BSP support for exceptions and interrupts under 'bspsupp'
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* is designed to be #ifdef <flavor> FREE.
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* BSPs using 'bspsupp' should work with __ppc_generic
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*/
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#ifndef __ppc_generic
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/*
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* find out, whether we want to (re)enable the MMU in the assembly code
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* FIXME: move this to a better location
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@@ -79,8 +89,8 @@
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* size LAST_VALID_EXC.
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* So until there is a CPU that uses 0xA we'll just use that :-(
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*/
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#define ASM_VEC_VECTOR 0x0A
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#define ASM_VEC_VECTOR_OFFSET (0xf20)
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#define ASM_60X_VEC_VECTOR 0x0A
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#define ASM_60X_VEC_VECTOR_OFFSET (0xf20)
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#define ASM_SYS_VECTOR 0x0C
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#define ASM_SYS_VECTOR_OFFSET (ASM_SYS_VECTOR << 8)
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@@ -92,25 +102,25 @@
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/*
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* vectors for PPC405
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*/
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#define ASM_CRIT_VECTOR ASM_RESET_VECTOR
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#define ASM_CRIT_VECTOR_OFFSET (ASM_CRIT_VECTOR << 8)
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#define ASM_BOOKE_CRIT_VECTOR ASM_RESET_VECTOR
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#define ASM_BOOKE_CRIT_VECTOR_OFFSET (ASM_BOOKE_CRIT_VECTOR << 8)
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#define ASM_PIT_VECTOR 0x10
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#define ASM_PIT_VECTOR_OFFSET (ASM_PIT_VECTOR << 8)
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#define ASM_BOOKE_PIT_VECTOR 0x10
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#define ASM_BOOKE_PIT_VECTOR_OFFSET (ASM_BOOKE_PIT_VECTOR << 8)
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#define ASM_ITLBMISS_VECTOR 0x11
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#define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8)
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#define ASM_BOOKE_ITLBMISS_VECTOR 0x11
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#define ASM_BOOKE_ITLBMISS_VECTOR_OFFSET (ASM_BOOKE_ITLBMISS_VECTOR << 8)
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#define ASM_DTLBMISS_VECTOR 0x12
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#define ASM_DTLBMISS_VECTOR_OFFSET (ASM_DTLBMISS_VECTOR << 8)
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#define ASM_BOOKE_DTLBMISS_VECTOR 0x12
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#define ASM_BOOKE_DTLBMISS_VECTOR_OFFSET (ASM_BOOKE_DTLBMISS_VECTOR << 8)
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#define ASM_FIT_VECTOR 0x13
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#define ASM_FIT_VECTOR_OFFSET (0x1010)
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#define ASM_BOOKE_FIT_VECTOR 0x13
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#define ASM_BOOKE_FIT_VECTOR_OFFSET (0x1010)
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#define ASM_WDOG_VECTOR 0x14
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#define ASM_WDOG_VECTOR_OFFSET (0x1020)
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#define ASM_BOOKE_WDOG_VECTOR 0x14
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#define ASM_BOOKE_WDOG_VECTOR_OFFSET (0x1020)
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#define LAST_VALID_EXC ASM_WDOG_VECTOR
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#define LAST_VALID_EXC ASM_BOOKE_WDOG_VECTOR
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/*
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* bit mask of all exception vectors, that are handled
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@@ -119,7 +129,7 @@
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* code to determine, whether to use SRR0/SRR1/rfi or SRR2/SRR3/rfci
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*/
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#define ASM_VECTORS_CRITICAL \
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(( 1 << (31-ASM_CRIT_VECTOR)) \
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(( 1 << (31-ASM_BOOKE_CRIT_VECTOR)) \
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|(1 << (31-ASM_MACH_VECTOR)) \
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|(1 << (31-ASM_WDOG_VECTOR)))
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@@ -132,81 +142,81 @@
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* FIXME: even more vector names might get used in common,
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* but the names have diverged between different PPC families
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*/
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#define ASM_FLOATASSIST_VECTOR 0x0E
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#define ASM_FLOATASSIST_VECTOR_OFFSET (ASM_FLOATASSIST_VECTOR << 8)
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#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
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#define ASM_8XX_FLOATASSIST_VECTOR_OFFSET (ASM_8XX_FLOATASSIST_VECTOR << 8)
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#define ASM_SOFTEMUL_VECTOR 0x10
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#define ASM_SOFTEMUL_VECTOR_OFFSET (ASM_SOFTEMUL_VECTOR << 8)
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#define ASM_8XX_SOFTEMUL_VECTOR 0x10
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#define ASM_8XX_SOFTEMUL_VECTOR_OFFSET (ASM_8XX_SOFTEMUL_VECTOR << 8)
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#define ASM_ITLBMISS_VECTOR 0x11
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#define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8)
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#define ASM_8XX_ITLBMISS_VECTOR 0x11
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#define ASM_8XX_ITLBMISS_VECTOR_OFFSET (ASM_8XX_ITLBMISS_VECTOR << 8)
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#define ASM_DTLBMISS_VECTOR 0x12
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#define ASM_DTLBMISS_VECTOR_OFFSET (ASM_DTLBMISS_VECTOR << 8)
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#define ASM_8XX_DTLBMISS_VECTOR 0x12
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#define ASM_8XX_DTLBMISS_VECTOR_OFFSET (ASM_8XX_DTLBMISS_VECTOR << 8)
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#define ASM_ITLBERROR_VECTOR 0x13
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#define ASM_ITLBERROR_VECTOR_OFFSET (ASM_ITLBERROR_VECTOR << 8)
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#define ASM_8XX_ITLBERROR_VECTOR 0x13
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#define ASM_8XX_ITLBERROR_VECTOR_OFFSET (ASM_8XX_ITLBERROR_VECTOR << 8)
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#define ASM_DTLBERROR_VECTOR 0x14
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#define ASM_DTLBERROR_VECTOR_OFFSET (ASM_DTLBERROR_VECTOR << 8)
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#define ASM_8XX_DTLBERROR_VECTOR 0x14
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#define ASM_8XX_DTLBERROR_VECTOR_OFFSET (ASM_8XX_DTLBERROR_VECTOR << 8)
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#define ASM_DBREAK_VECTOR 0x1C
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#define ASM_DBREAK_VECTOR_OFFSET (ASM_DBREAK_VECTOR << 8)
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#define ASM_8XX_DBREAK_VECTOR 0x1C
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#define ASM_8XX_DBREAK_VECTOR_OFFSET (ASM_8XX_DBREAK_VECTOR << 8)
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#define ASM_IBREAK_VECTOR 0x1D
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#define ASM_IBREAK_VECTOR_OFFSET (ASM_IBREAK_VECTOR << 8)
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#define ASM_8XX_IBREAK_VECTOR 0x1D
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#define ASM_8XX_IBREAK_VECTOR_OFFSET (ASM_8XX_IBREAK_VECTOR << 8)
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#define ASM_PERIFBREAK_VECTOR 0x1E
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#define ASM_PERIFBREAK_VECTOR_OFFSET (ASM_PERIFBREAK_VECTOR << 8)
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#define ASM_8XX_PERIFBREAK_VECTOR 0x1E
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#define ASM_8XX_PERIFBREAK_VECTOR_OFFSET (ASM_8XX_PERIFBREAK_VECTOR << 8)
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#define ASM_DEVPORT_VECTOR 0x1F
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#define ASM_DEVPORT_VECTOR_OFFSET (ASM_DEVPORT_VECTOR_OFFSET << 8)
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#define ASM_8XX_DEVPORT_VECTOR 0x1F
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#define ASM_8XX_DEVPORT_VECTOR_OFFSET (ASM_8XX_DEVPORT_VECTOR_OFFSET << 8)
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#define LAST_VALID_EXC ASM_DEVPORT_VECTOR
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#define LAST_VALID_EXC ASM_8XX_DEVPORT_VECTOR
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#elif (defined(mpc555) || defined(mpc505))
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/*
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* vectorx for MPC5xx
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*/
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#define ASM_FLOATASSIST_VECTOR 0x0E
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#define ASM_5XX_FLOATASSIST_VECTOR 0x0E
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#define ASM_SOFTEMUL_VECTOR 0x10
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#define ASM_5XX_SOFTEMUL_VECTOR 0x10
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#define ASM_IPROT_VECTOR 0x13
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#define ASM_DPROT_VECTOR 0x14
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#define ASM_5XX_IPROT_VECTOR 0x13
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#define ASM_5XX_DPROT_VECTOR 0x14
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#define ASM_DBREAK_VECTOR 0x1C
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#define ASM_IBREAK_VECTOR 0x1D
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#define ASM_MEBREAK_VECTOR 0x1E
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#define ASM_NMEBREAK_VECTOR 0x1F
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#define ASM_5XX_DBREAK_VECTOR 0x1C
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#define ASM_5XX_IBREAK_VECTOR 0x1D
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#define ASM_5XX_MEBREAK_VECTOR 0x1E
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#define ASM_5XX_NMEBREAK_VECTOR 0x1F
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#define LAST_VALID_EXC ASM_NMEBREAK_VECTOR
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#define LAST_VALID_EXC ASM_5XX_NMEBREAK_VECTOR
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#else /* 60x style cpu types */
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#define PPC_HAS_60X_VECTORS
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#define ASM_PERFMON_VECTOR 0x0F
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#define ASM_PERFMON_VECTOR_OFFSET (ASM_PERFMON_VECTOR << 8)
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#define ASM_60X_PERFMON_VECTOR 0x0F
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#define ASM_60X_PERFMON_VECTOR_OFFSET (ASM_60X_PERFMON_VECTOR << 8)
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#define ASM_IMISS_VECTOR 0x10
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#define ASM_60X_IMISS_VECTOR 0x10
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#define ASM_DLMISS_VECTOR 0x11
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#define ASM_60X_DLMISS_VECTOR 0x11
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#define ASM_DSMISS_VECTOR 0x12
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#define ASM_60X_DSMISS_VECTOR 0x12
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#define ASM_ADDR_VECTOR 0x13
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#define ASM_ADDR_VECTOR_OFFSET (ASM_ADDR_VECTOR << 8)
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#define ASM_60X_ADDR_VECTOR 0x13
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#define ASM_60X_ADDR_VECTOR_OFFSET (ASM_60X_ADDR_VECTOR << 8)
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#define ASM_SYSMGMT_VECTOR 0x14
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#define ASM_SYSMGMT_VECTOR_OFFSET (ASM_SYSMGMT_VECTOR << 8)
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#define ASM_60X_SYSMGMT_VECTOR 0x14
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#define ASM_60X_SYSMGMT_VECTOR_OFFSET (ASM_60X_SYSMGMT_VECTOR << 8)
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#define ASM_VEC_ASSIST_VECTOR 0x16
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#define ASM_VEC_ASSIST_VECTOR_OFFSET (ASM_VEC_ASSIST_VECTOR << 8)
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#define ASM_60X_VEC_ASSIST_VECTOR 0x16
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#define ASM_60X_VEC_ASSIST_VECTOR_OFFSET (ASM_60X_VEC_ASSIST_VECTOR << 8)
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#define ASM_ITM_VECTOR 0x17
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#define ASM_ITM_VECTOR_OFFSET (ASM_ITM_VECTOR << 8)
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#define ASM_60X_ITM_VECTOR 0x17
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#define ASM_60X_ITM_VECTOR_OFFSET (ASM_60X_ITM_VECTOR << 8)
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#define LAST_VALID_EXC ASM_ITM_VECTOR
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#define LAST_VALID_EXC ASM_60X_ITM_VECTOR
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#endif
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@@ -222,6 +232,61 @@
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#else
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#endif
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#else /* __ppc_generic */
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#define ASM_RESET_VECTOR 0x01
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#define ASM_MACH_VECTOR 0x02
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#define ASM_PROT_VECTOR 0x03
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#define ASM_ISI_VECTOR 0x04
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#define ASM_EXT_VECTOR 0x05
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#define ASM_ALIGN_VECTOR 0x06
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#define ASM_PROG_VECTOR 0x07
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#define ASM_FLOAT_VECTOR 0x08
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#define ASM_DEC_VECTOR 0x09
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#define ASM_60X_VEC_VECTOR 0x0A
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#define ASM_SYS_VECTOR 0x0C
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#define ASM_TRACE_VECTOR 0x0D
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#define ASM_BOOKE_CRIT_VECTOR 0x01
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#define ASM_BOOKE_PIT_VECTOR 0x10
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#define ASM_BOOKE_ITLBMISS_VECTOR 0x11
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#define ASM_BOOKE_DTLBMISS_VECTOR 0x12
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#define ASM_BOOKE_FIT_VECTOR 0x13
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#define ASM_BOOKE_WDOG_VECTOR 0x14
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#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
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#define ASM_8XX_SOFTEMUL_VECTOR 0x10
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#define ASM_8XX_ITLBMISS_VECTOR 0x11
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#define ASM_8XX_DTLBMISS_VECTOR 0x12
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#define ASM_8XX_ITLBERROR_VECTOR 0x13
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#define ASM_8XX_DTLBERROR_VECTOR 0x14
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#define ASM_8XX_DBREAK_VECTOR 0x1C
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#define ASM_8XX_IBREAK_VECTOR 0x1D
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#define ASM_8XX_PERIFBREAK_VECTOR 0x1E
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#define ASM_8XX_DEVPORT_VECTOR 0x1F
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#define ASM_5XX_FLOATASSIST_VECTOR 0x0E
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#define ASM_5XX_SOFTEMUL_VECTOR 0x10
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#define ASM_5XX_IPROT_VECTOR 0x13
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#define ASM_5XX_DPROT_VECTOR 0x14
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#define ASM_5XX_DBREAK_VECTOR 0x1C
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#define ASM_5XX_IBREAK_VECTOR 0x1D
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#define ASM_5XX_MEBREAK_VECTOR 0x1E
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#define ASM_5XX_NMEBREAK_VECTOR 0x1F
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#define ASM_60X_PERFMON_VECTOR 0x0F
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#define ASM_60X_IMISS_VECTOR 0x10
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#define ASM_60X_DLMISS_VECTOR 0x11
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#define ASM_60X_DSMISS_VECTOR 0x12
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#define ASM_60X_ADDR_VECTOR 0x13
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#define ASM_60X_SYSMGMT_VECTOR 0x14
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#define ASM_60X_VEC_ASSIST_VECTOR 0x16
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#define ASM_60X_ITM_VECTOR 0x17
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#define LAST_VALID_EXC 0x1F
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#endif /* __ppc_generic */
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#ifndef ASM
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@@ -319,6 +384,11 @@ extern int ppc_vector_is_valid(rtems_vector vector);
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extern int ppc_init_exceptions (rtems_raw_except_global_settings* config);
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extern int ppc_get_exception_config (rtems_raw_except_global_settings** config);
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void* ppc_get_vector_addr(rtems_vector vector);
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int ppc_is_e500();
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void e500_setup_raw_exceptions();
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/* This variable is initialized to 'TRUE' by default;
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* BSPs which have their vectors in ROM should set it
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* to FALSE prior to initializing raw exceptions.
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