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B.Robinson MIPS patch

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This commit is contained in:
Greg Menke
2006-06-08 18:03:55 +00:00
parent 549e88f623
commit 7c99007641
11 changed files with 252 additions and 189 deletions
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c/src/lib/libcpu/mips/ChangeLog
+7 -1
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@@ -1,7 +1,13 @@
2006-06-08 Bruce Robinson <brucer@pmccorp.com>
* Makefile.am: add interruptmask.c
* shared/interrupts/interuptmask.c: TX49 conditional mask computation
* shared/interrupts/vectorexceptions.c: Corrections to exception codes
& descriptions
2006-05-16 Ralf Corsépius <ralf.corsepius@rtems.org>
* configure.ac: Use RTEMS_AMPOLISH3.
2006-04-02 Ralf Corsépius <ralf.corsepius@rtems.org>
* Makefile.am: Remove bogus CFLAGS_OPTIMIZE_V.
c/src/lib/libcpu/mips/Makefile.am
+2 -1
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@@ -41,7 +41,8 @@ endif
noinst_PROGRAMS += shared/interrupts.rel
shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \
shared/interrupts/vectorexceptions.c shared/interrupts/isr_entries.S
shared/interrupts/vectorexceptions.c shared/interrupts/interruptmask.c \
shared/interrupts/isr_entries.S
shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS)
shared_interrupts_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c
+24
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@@ -0,0 +1,24 @@
/*
* $Id: interruptmask.c,v 1.0 2006/04/04 05:18:49
*/
#include <rtems.h>
/*
* This function returns a mask value which is used to select the bits
* in the processor status register that can be set to enable interrupts.
* The mask value should not include the 2 software interrupt enable bits.
*/
uint32_t mips_interrupt_mask( void )
{
uint32_t interrupt_mask;
#ifdef TX49
interrupt_mask = 0x00000400; /* Toshiba TX49 processors have a non-standard interrupt mask */
#else
interrupt_mask = 0x0000fc00;
#endif
return(interrupt_mask);
}
c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c
+11 -10
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@@ -24,17 +24,18 @@ static const char *cause_strings[32] =
/* 5 */ "Address Store",
/* 6 */ "Instruction Bus Error",
/* 7 */ "Data Bus Error",
/* 9 */ "Syscall",
/* 10 */ "Breakpoint",
/* 11 */ "Reserved Instruction",
/* 12 */ "Coprocessor Unuseable",
/* 13 */ "Overflow",
/* 14 */ "Trap",
/* 15 */ "Instruction Virtual Coherency Error",
/* 16 */ "FP Exception",
/* 8 */ "Syscall",
/* 9 */ "Breakpoint",
/* 10 */ "Reserved Instruction",
/* 11 */ "Coprocessor Unuseable",
/* 12 */ "Overflow",
/* 13 */ "Trap",
/* 14 */ "Instruction Virtual Coherency Error",
/* 15 */ "FP Exception",
/* 16 */ "Reserved 16",
/* 17 */ "Reserved 17",
/* 18 */ "Reserved 17",
/* 19 */ "Reserved 17",
/* 18 */ "Reserved 18",
/* 19 */ "Reserved 19",
/* 20 */ "Reserved 20",
/* 21 */ "Reserved 21",
/* 22 */ "Reserved 22",
cpukit/score/cpu/mips/ChangeLog
+8
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@@ -1,3 +1,11 @@
2006-06-08 Bruce Robinson <brucer@pmccorp.com>
* cpu.c: Add int64 types for __mips==3 cpus, incorporate
mips_interrupt_mask() into mask computations
* cpu_asm.S: Add int64 register save/restores for __mips==3 cpus. Adjustment
of mips1 vs mips3 macros.
* cpu.h: Add int64 types for __mips==3 cpus.
2006-03-17 Ralf Corsepius <ralf.corsepius@rtems.org>
* cpu.c (_CPU_Initialize): Add fpu initialization.
cpukit/score/cpu/mips/cpu.c
+14 -7
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@@ -50,11 +50,18 @@
/*
** local dword used in cpu_asm to pass the exception stack frame to the
** context switch code.
** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
** address to the context switch code.
*/
unsigned __exceptionStackFrame = 0;
#if (__mips == 1)
typedef uint32_t ESF_PTR_TYPE;
#elif (__mips == 3)
typedef uint64_t ESF_PTR_TYPE;
#else
#error "unknown MIPS ISA"
#endif
ESF_PTR_TYPE __exceptionStackFrame = 0;
@@ -107,11 +114,11 @@ uint32_t _CPU_ISR_Get_level( void )
#if (__mips == 3) || (__mips == 32)
/* IE bit and shift down hardware ints into bits 1 thru 6 */
sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
#elif __mips == 1
/* IEC bit and shift down hardware ints into bits 1 thru 6 */
sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
#else
#error "CPU ISR level: unknown MIPS level for SR handling"
@@ -142,8 +149,8 @@ void _CPU_ISR_Set_level( uint32_t new_level )
srbits = sr & ~(0xfc00 | SR_IE);
sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
(((new_level<<9) & 0xfc00) | \
sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
(((new_level<<9) & mips_interrupt_mask()) | \
((new_level & 1)?SR_IE:0)));
/*
if ( (new_level & SR_EXL) == (sr & SR_EXL) )
cpukit/score/cpu/mips/cpu_asm.S
+162 -161
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File diff suppressed because it is too large Load Diff
cpukit/score/cpu/mips/rtems/score/cpu.h
+16 -6
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@@ -442,7 +442,7 @@ typedef struct {
__MIPS_FPU_REGISTER_TYPE fp29;
__MIPS_FPU_REGISTER_TYPE fp30;
__MIPS_FPU_REGISTER_TYPE fp31;
__MIPS_FPU_REGISTER_TYPE fpcs;
uint32_t fpcs;
#endif
} Context_Control_fp;
@@ -766,6 +766,13 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define _CPU_Initialize_vectors()
/*
* Declare the function that is present in the shared libcpu directory,
* that returns the processor dependent interrupt mask.
*/
uint32_t mips_interrupt_mask( void );
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
@@ -872,12 +879,16 @@ void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
#if (__mips == 3) || (__mips == 32)
#define _INTON SR_IE
#if __mips_fpr==64
#define _EXTRABITS SR_FR
#else
#define _EXTRABITS 0
#endif
#endif /* __mips_fpr==64 */
#endif /* __mips == 3 */
#if __mips == 1
#define _INTON SR_IEC
#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */
#endif
#endif /* __mips == 1 */
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
{ \
@@ -888,9 +899,8 @@ void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
(_the_context)->sp = _stack_tmp; \
(_the_context)->fp = _stack_tmp; \
(_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
0x300 | \
((_intlvl & 1)?_INTON:0)) ) | \
(_the_context)->c0_sr = ((_intlvl==0)?(mips_interrupt_mask() | 0x300 | _INTON): \
( ((_intlvl<<9) & mips_interrupt_mask()) | 0x300 | ((_intlvl & 1)?_INTON:0)) ) | \
SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
}
make/ChangeLog
+6 -1
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@@ -1,6 +1,11 @@
2006-06-08 Bruce Robinson <brucer@pmccorp.com>
* custom/rbtx4925.cfg: Fix CPU_CFLAGS defines.
* custom/rbtx4938.cfg: Fix CPU_CFLAGS defines.
2005-04-10 Eric Norum <norume@aps.anl.gov>
* custom/uC5282.cfg: Keep frame pointer -- gdb is much more useful.
* custom/uC5282.cfg: Keep frame pointer -- gdb is much more useful.
2006-03-16 Ralf Corsepius <ralf.corsepius@rtems.org>
make/custom/rbtx4925.cfg
+1 -1
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@@ -13,7 +13,7 @@ RTEMS_BSP_FAMILY=rbtx4925
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
CPU_CFLAGS = -mips3 -G0 -EL -DCPU_TX49
CPU_CFLAGS = -mips3 -G0 -EL
# optimize flag: typically -0, could use -O4 or -fast
# -O4 is ok for RTEMS
make/custom/rbtx4938.cfg
+1 -1
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@@ -13,7 +13,7 @@ RTEMS_BSP_FAMILY=rbtx4938
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
CPU_CFLAGS = -mips3 -G0 -EL -DCPU_TX49
CPU_CFLAGS = -mips3 -G0 -EL
# optimize flag: typically -0, could use -O4 or -fast
# -O4 is ok for RTEMS