mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-08-29 09:50:44 +08:00
RaspberryPi: Added I2C and SPI bus support.
Further documentation can be found in https://devel.rtems.org/wiki/GSoC/2015/RaspberryPi_peripherals_and_SD_card and test data (including sample user applications, device drivers and wiring schemes) can be found in https://github.com/asuol/RTEMS_rpi_testing
This commit is contained in:
Andre Marques
committed by
Gedare Bloom
Gedare Bloom
parent
f7ea9579ad
commit
7aca0fefce
@@ -46,6 +46,8 @@ include_bsp_HEADERS += include/mmu.h
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include_bsp_HEADERS += include/usart.h
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include_bsp_HEADERS += include/raspberrypi.h
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include_bsp_HEADERS += include/rpi-gpio.h
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include_bsp_HEADERS += include/i2c.h
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include_bsp_HEADERS += include/spi.h
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include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache_.h \
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../../../libcpu/arm/shared/include/arm-cp15.h
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@@ -128,6 +130,10 @@ libbsp_a_SOURCES += gpio/rpi-gpio.c
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# SSP
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# I2C
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libbsp_a_SOURCES += i2c/i2c.c
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# SPI
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libbsp_a_SOURCES += spi/spi.c
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# Cache
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libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
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@@ -24,14 +24,18 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
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RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
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RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
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RTEMS_BSPOPTS_SET([I2C_IO_MODE],[*],[1])
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RTEMS_BSPOPTS_HELP([I2C_IO_MODE],[Define to 1 to use interrupt-driven I/O with the Raspberry Pi I2C bus. If defined to other value the access will be polled-driven.])
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RTEMS_BSPOPTS_SET([SPI_IO_MODE],[*],[1])
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RTEMS_BSPOPTS_HELP([SPI_IO_MODE],[Define to 1 to use interrupt-driven I/O with the Raspberry Pi SPI bus. If defined to other value the access will be polled-driven.])
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# Is this a Raspberry Pi 2?
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RTEMS_BSPOPTS_SET([BSP_IS_RPI2],[raspberrypi2],[1])
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RTEMS_BSPOPTS_SET([BSP_IS_RPI2],[*],[0])
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RTEMS_BSPOPTS_HELP([BSP_IS_RPI2],[Set if the BSP variant is Raspberry Pi 2.])
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AM_CONDITIONAL(RTEMS_RPI2,[test "$BSP_IS_RPI2" = "1"])
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RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
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RTEMS_BSP_LINKCMDS
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@@ -0,0 +1,421 @@
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/**
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* @file i2c.c
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*
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* @ingroup raspberrypi_i2c
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*
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* @brief Support for the I2C bus on the Raspberry Pi GPIO P1 header (model A/B)
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* and GPIO J8 header on model B+.
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*/
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/*
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* Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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/*
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* STATUS:
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* - 10-bit slave addressing untested
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*/
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#include <bsp.h>
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#include <bsp/raspberrypi.h>
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#include <bsp/gpio.h>
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#include <bsp/rpi-gpio.h>
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#include <bsp/irq.h>
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#include <bsp/i2c.h>
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#include <assert.h>
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#define TRANSFER_COUNT(buffer_size) (buffer_size + 0xFFFE) / 0xFFFF
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#define ADJUST_TRANSFER_SIZE(transfer_count, remaining_bytes) \
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transfer_count > 1 ? 0xFFFF : (remaining_bytes & 0xFFFF)
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#define I2C_POLLING(condition) \
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while ( condition ) { \
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; \
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}
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/**
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* @brief Object containing relevant information about an I2C bus.
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*
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* Encapsulates relevant data for a I2C bus transfer.
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*/
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typedef struct
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{
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i2c_bus base;
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uint32_t input_clock;
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rtems_id task_id;
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/* Remaining bytes to read/write on the current bus transfer. */
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uint32_t remaining_bytes;
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/* Each transfer has a limit of 0xFFFF bytes, hence larger transfers
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* have to be divided. Each transfer implies a stop condition, signaled
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* automatically by the BSC controller. */
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uint32_t remaining_transfers;
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uint8_t *current_buffer;
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uint32_t current_buffer_size;
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bool read_transfer;
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} rpi_i2c_bus;
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static int rpi_i2c_bus_transfer(rpi_i2c_bus *bus)
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{
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while ( bus->remaining_bytes >= 1 ) {
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/* If reading. */
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if ( bus->read_transfer ) {
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/* Poll RXD bit until there is data on the RX FIFO to read. */
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I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 5)) == 0);
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/* Read data from the RX FIFO. */
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(*(uint8_t *) bus->current_buffer) = BCM2835_REG(BCM2835_I2C_FIFO) & 0xFF;
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++bus->current_buffer;
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/* Check for acknowledgment or clock stretching errors. */
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if (
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(BCM2835_REG(BCM2835_I2C_S) & (1 << 8)) ||
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(BCM2835_REG(BCM2835_I2C_S) & (1 << 9))
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) {
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return -EIO;
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}
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}
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/* If writing. */
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else {
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/* If using the I2C bus in interrupt-driven mode. */
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#if I2C_IO_MODE == 1
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/* Generate interrupts on the TXW bit condition. */
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BCM2835_REG(BCM2835_I2C_C) |= (1 << 9);
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/* Sleep until the TX FIFO has free space for a new write. */
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if (
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rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout) !=
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RTEMS_SUCCESSFUL
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) {
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rtems_event_transient_clear();
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return -ETIMEDOUT;
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}
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/* If using the bus in polling mode. */
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#else
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/* Poll TXW bit until there is space available to write. */
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I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 2)) == 0);
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#endif
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/* Write data to the TX FIFO. */
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BCM2835_REG(BCM2835_I2C_FIFO) = (*(uint8_t *) bus->current_buffer);
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++bus->current_buffer;
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/* Check for acknowledgment or clock stretching errors. */
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if (
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(BCM2835_REG(BCM2835_I2C_S) & (1 << 8)) ||
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(BCM2835_REG(BCM2835_I2C_S) & (1 << 9))
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) {
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return -EIO;
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}
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}
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--bus->remaining_bytes;
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--bus->current_buffer_size;
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}
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return 0;
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}
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static int rpi_i2c_setup_transfer(rpi_i2c_bus *bus)
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{
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int rv;
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while ( bus->remaining_transfers > 0 ) {
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/* Setup the byte size of the current transfer. */
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bus->remaining_bytes = ADJUST_TRANSFER_SIZE(
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bus->remaining_transfers,
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bus->current_buffer_size
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);
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/* Set the DLEN register, which specifies how many data packets
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* will be transferred. */
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BCM2835_REG(BCM2835_I2C_DLEN) = bus->remaining_bytes;
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/* Clear the acknowledgment and clock stretching error status. */
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BCM2835_REG(BCM2835_I2C_S) |= (3 << 8);
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/* Send start bit. */
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BCM2835_REG(BCM2835_I2C_C) |= (1 << 7);
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/* Check for an acknowledgment error. */
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if ( (BCM2835_REG(BCM2835_I2C_S) & (1 << 8)) != 0 ) {
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return -EIO;
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}
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rv = rpi_i2c_bus_transfer(bus);
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if ( rv < 0 ) {
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return rv;
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}
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/* Wait for the current transfer to finish. */
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/* If using the I2C bus in interrupt-driven mode. */
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#if I2C_IO_MODE == 1
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/* Generate interrupts on the DONE bit condition. */
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BCM2835_REG(BCM2835_I2C_C) |= (1 << 8);
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if (
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rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout) !=
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RTEMS_SUCCESSFUL
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) {
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rtems_event_transient_clear();
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return -ETIMEDOUT;
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}
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/* If using the bus in polling mode. */
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#else
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/* Poll DONE bit until all data has been sent. */
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I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 1)) == 0);
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#endif
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--bus->remaining_transfers;
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}
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return 0;
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}
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/* Handler function that is called on any I2C interrupt.
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*
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* There are 3 situations that can generate an interrupt:
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*
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* 1. Transfer (read/write) complete;
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* 2. The TX FIFO has space for more data (during a write transfer);
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* 3. The RX FIFO is full.
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*
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* Because the I2C FIFO has a 16 byte size, the 3. situation is not
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* as useful to many applications as knowing that at least 1 byte can
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* be read from the RX FIFO. For that reason this information is
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* got through polling the RXD bit even in interrupt-driven mode.
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*
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* This leaves only 2 interrupts to be caught. At any given time
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* when no I2C bus transfer is taking place no I2C interrupts are
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* generated, and they do they are only enabled one at a time:
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*
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* - When trying to write, the 2. interrupt is enabled to signal that
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* data can be written on the TX FIFO, avoiding data loss in case
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* it is full. When caught the handler disables that interrupt from
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* being generated and sends a waking event to the transfer task,
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* which will allow the transfer process to continue
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* (by writing to the TX FIFO);
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*
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* - When the transfer is done on the Raspberry side, the 1. interrupt is
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* enabled for the device to signal it has finished the transfer as
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* well. When caught the handler disables that interrupt from being
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* generated and sends a waking event to the transfer task, marking
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* the end of the transfer.
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*/
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#if I2C_IO_MODE == 1
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static void i2c_handler(void *arg)
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{
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rpi_i2c_bus *bus = (rpi_i2c_bus *) arg;
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/* If the current enabled interrupt is on the TXW condition, disable it. */
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if ( (BCM2835_REG(BCM2835_I2C_C) & (1 << 9)) ) {
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BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 9);
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}
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/* If the current enabled interrupt is on the DONE condition, disable it. */
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else if ( (BCM2835_REG(BCM2835_I2C_C) & (1 << 8)) ) {
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BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 8);
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}
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/* Allow the transfer process to continue. */
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rtems_event_transient_send(bus->task_id);
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}
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#endif
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static int rpi_i2c_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t msg_count)
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{
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rpi_i2c_bus *bus = (rpi_i2c_bus *) base;
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uint32_t rv = 0;
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uint32_t i;
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/* Perform an initial parse through the messages for the I2C_M_RECV_LEN flag,
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* which the Pi seems to not support and the I2C framework expects the bus
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* to provide as part of the I2C_FUNC_I2C functionality.
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*
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* It states that the slave device sends an initial byte containing the size
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* of the transfer, and for this to work the Pi will likely require two
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* transfers, with a stop-start condition in-between. */
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for ( i = 0; i < msg_count; ++i ) {
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if ( msgs[i].flags & I2C_M_RECV_LEN ) {
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return -EINVAL;
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}
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}
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for ( i = 0; i < msg_count; ++i ) {
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/* Clear FIFOs. */
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BCM2835_REG(BCM2835_I2C_C) |= (3 << 4);
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/* Setup transfer. */
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bus->current_buffer = msgs[i].buf;
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bus->current_buffer_size = msgs[i].len;
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bus->remaining_transfers = TRANSFER_COUNT(bus->current_buffer_size);
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/* If the slave uses 10-bit addressing. */
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if ( msgs[i].flags & I2C_M_TEN ) {
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/* Write the 8 least-significative bits of the slave address
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* to the bus FIFO. */
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BCM2835_REG(BCM2835_I2C_FIFO) = msgs[i].addr & 0xFF;
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/* Address slave device, with the 2 most-significative bits at the end. */
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BCM2835_REG(BCM2835_I2C_A) = (0x1E << 2) | (msgs[i].addr >> 8);
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}
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/* If using the regular 7-bit slave addressing. */
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else {
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/* Address slave device. */
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BCM2835_REG(BCM2835_I2C_A) = msgs[i].addr;
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}
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if ( msgs[i].flags & I2C_M_RD ) {
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/* If the slave uses 10-bit addressing. */
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if ( msgs[i].flags & I2C_M_TEN ) {
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/* 10-bit addressing setup for a read transfer. */
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BCM2835_REG(BCM2835_I2C_DLEN) = 1;
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/* Set write bit. */
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BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 0);
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/* Send start bit. */
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BCM2835_REG(BCM2835_I2C_C) |= (1 << 7);
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/* Poll the TA bit until the transfer has started. */
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I2C_POLLING((BCM2835_REG(BCM2835_I2C_S) & (1 << 0)) == 0);
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}
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/* Set read bit. */
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BCM2835_REG(BCM2835_I2C_C) |= (1 << 0);
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bus->read_transfer = true;
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}
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else if ( msgs[i].flags == 0 || msgs[i].flags == I2C_M_TEN ) {
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/* If the slave uses 10-bit addressing. */
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if ( msgs[i].flags & I2C_M_TEN ) {
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/* 10-bit addressing setup for a write transfer. */
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bus->current_buffer_size += 1;
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bus->remaining_transfers = TRANSFER_COUNT(bus->current_buffer_size);
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}
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/* Set write bit. */
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BCM2835_REG(BCM2835_I2C_C) &= ~(1 << 0);
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bus->read_transfer = false;
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}
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rv = rpi_i2c_setup_transfer(bus);
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if ( rv < 0 ) {
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return rv;
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}
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}
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return rv;
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}
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/* Calculates a clock divider to be used with the BSC core clock rate
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* to set a I2C clock rate the closest (<=) to a desired frequency. */
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static int rpi_i2c_set_clock(i2c_bus *base, unsigned long clock)
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{
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rpi_i2c_bus *bus = (rpi_i2c_bus *) base;
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uint32_t clock_rate;
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uint16_t divider;
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/* Calculates an initial clock divider. */
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divider = BSC_CORE_CLK_HZ / clock;
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clock_rate = BSC_CORE_CLK_HZ / divider;
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/* If the resulting clock rate is greater than desired, try the next greater
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* divider. */
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while ( clock_rate > clock ) {
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++divider;
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clock_rate = BSC_CORE_CLK_HZ / divider;
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}
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/* Set clock divider. */
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BCM2835_REG(BCM2835_I2C_DIV) = divider;
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bus->input_clock = clock_rate;
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return 0;
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}
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static void rpi_i2c_destroy(i2c_bus *base)
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{
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rpi_i2c_bus *bus = (rpi_i2c_bus *) base;
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i2c_bus_destroy_and_free(&bus->base);
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}
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int rpi_i2c_register_bus(
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const char *bus_path,
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uint32_t bus_clock
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) {
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#if I2C_IO_MODE == 1
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rtems_status_code sc;
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#endif
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rpi_i2c_bus *bus;
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int rv;
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bus = (rpi_i2c_bus *) i2c_bus_alloc_and_init(sizeof(*bus));
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if ( bus == NULL ) {
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return -1;
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}
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/* Enable the I2C BSC interface. */
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BCM2835_REG(BCM2835_I2C_C) |= (1 << 15);
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/* If the access to the bus is configured to be interrupt-driven. */
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#if I2C_IO_MODE == 1
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bus->task_id = rtems_task_self();
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sc = rtems_interrupt_handler_install(
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BCM2835_IRQ_ID_I2C,
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NULL,
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RTEMS_INTERRUPT_UNIQUE,
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(rtems_interrupt_handler) i2c_handler,
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bus
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);
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if ( sc != RTEMS_SUCCESSFUL ) {
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return -EIO;
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}
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#endif
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rv = rpi_i2c_set_clock(&bus->base, bus_clock);
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if ( rv < 0 ) {
|
||||
(*bus->base.destroy)(&bus->base);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
bus->base.transfer = rpi_i2c_transfer;
|
||||
bus->base.set_clock = rpi_i2c_set_clock;
|
||||
bus->base.destroy = rpi_i2c_destroy;
|
||||
bus->base.functionality = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
|
||||
|
||||
return i2c_bus_register(&bus->base, bus_path);
|
||||
}
|
||||
|
||||
void rpi_i2c_init(void)
|
||||
{
|
||||
/* Enable the I2C interface on the Raspberry Pi. */
|
||||
rtems_gpio_initialize();
|
||||
|
||||
assert ( rpi_gpio_select_i2c() == RTEMS_SUCCESSFUL );
|
||||
}
|
||||
@@ -0,0 +1,95 @@
|
||||
/**
|
||||
* @file i2c.h
|
||||
*
|
||||
* @ingroup raspberrypi_i2c
|
||||
*
|
||||
* @brief Raspberry Pi specific I2C definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_RASPBERRYPI_I2C_H
|
||||
#define LIBBSP_ARM_RASPBERRYPI_I2C_H
|
||||
|
||||
#include <dev/i2c/i2c.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @name I2C constants.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief BSC controller core clock rate in Hz.
|
||||
*
|
||||
* This is set to 150 MHz as per the BCM2835 datasheet.
|
||||
*/
|
||||
#define BSC_CORE_CLK_HZ 150000000
|
||||
|
||||
/**
|
||||
* @brief Default bus clock.
|
||||
*
|
||||
* This sets the bus with a 100 kHz clock speed.
|
||||
*/
|
||||
#define DEFAULT_BUS_CLOCK 100000
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C directives.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setups the Raspberry Pi GPIO header to activate the BSC I2C bus.
|
||||
*/
|
||||
extern void rpi_i2c_init(void);
|
||||
|
||||
/**
|
||||
* @brief Registers the Raspberry Pi BSC I2C bus with the
|
||||
* Linux I2C User-Space API.
|
||||
*
|
||||
* @param[in] bus_path Path to the bus device file.
|
||||
* @param[in] bus_clock Bus clock in Hz.
|
||||
*
|
||||
* @retval 0 Bus registered successfully.
|
||||
* @retval <0 Could not register the bus. The return value is a negative
|
||||
* errno code.
|
||||
*/
|
||||
extern int rpi_i2c_register_bus(
|
||||
const char *bus_path,
|
||||
uint32_t bus_clock
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Setups the Raspberry Pi BSC I2C bus (located on the GPIO header)
|
||||
* on the "/dev/i2c" device file, using the default bus clock.
|
||||
*
|
||||
* @retval 0 Bus configured and registered successfully.
|
||||
* @retval <0 See @see rpi_i2c_register_bus().
|
||||
*/
|
||||
static inline int rpi_setup_i2c_bus(void)
|
||||
{
|
||||
rpi_i2c_init();
|
||||
|
||||
return rpi_i2c_register_bus("/dev/i2c", DEFAULT_BUS_CLOCK);
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_RASPBERRYPI_I2C_H */
|
||||
@@ -7,7 +7,7 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 Andre Marques <andre.lousa.marques at gmail.com>
|
||||
* Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
|
||||
* Copyright (c) 2013 Alan Cudmore.
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
@@ -68,15 +68,15 @@
|
||||
|
||||
#define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
|
||||
|
||||
#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE+0x00)
|
||||
#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE+0x04)
|
||||
#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE+0x08)
|
||||
#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE+0x0C)
|
||||
#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE+0x10)
|
||||
#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE+0x14)
|
||||
#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE+0x18)
|
||||
#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE+0x1C)
|
||||
#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE+0x20)
|
||||
#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00)
|
||||
#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04)
|
||||
#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08)
|
||||
#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C)
|
||||
#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10)
|
||||
#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14)
|
||||
#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18)
|
||||
#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C)
|
||||
#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20)
|
||||
|
||||
#define BCM2835_TIMER_PRESCALE 0xF9
|
||||
|
||||
@@ -90,19 +90,19 @@
|
||||
|
||||
#define BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000)
|
||||
|
||||
#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE+0x04)
|
||||
#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE+0x1C)
|
||||
#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE+0x28)
|
||||
#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE+0x34)
|
||||
#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE+0x40)
|
||||
#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE+0x4C)
|
||||
#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE+0x58)
|
||||
#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE+0x64)
|
||||
#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE+0x70)
|
||||
#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE+0x7C)
|
||||
#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE+0x88)
|
||||
#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE+0x94)
|
||||
#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE+0x98)
|
||||
#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04)
|
||||
#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C)
|
||||
#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28)
|
||||
#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34)
|
||||
#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40)
|
||||
#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C)
|
||||
#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58)
|
||||
#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64)
|
||||
#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70)
|
||||
#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C)
|
||||
#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88)
|
||||
#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94)
|
||||
#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98)
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -114,18 +114,18 @@
|
||||
|
||||
#define BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
|
||||
|
||||
#define AUX_ENABLES (BCM2835_AUX_BASE+0x04)
|
||||
#define AUX_MU_IO_REG (BCM2835_AUX_BASE+0x40)
|
||||
#define AUX_MU_IER_REG (BCM2835_AUX_BASE+0x44)
|
||||
#define AUX_MU_IIR_REG (BCM2835_AUX_BASE+0x48)
|
||||
#define AUX_MU_LCR_REG (BCM2835_AUX_BASE+0x4C)
|
||||
#define AUX_MU_MCR_REG (BCM2835_AUX_BASE+0x50)
|
||||
#define AUX_MU_LSR_REG (BCM2835_AUX_BASE+0x54)
|
||||
#define AUX_MU_MSR_REG (BCM2835_AUX_BASE+0x58)
|
||||
#define AUX_MU_SCRATCH (BCM2835_AUX_BASE+0x5C)
|
||||
#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE+0x60)
|
||||
#define AUX_MU_STAT_REG (BCM2835_AUX_BASE+0x64)
|
||||
#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE+0x68)
|
||||
#define AUX_ENABLES (BCM2835_AUX_BASE + 0x04)
|
||||
#define AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40)
|
||||
#define AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44)
|
||||
#define AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48)
|
||||
#define AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C)
|
||||
#define AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50)
|
||||
#define AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54)
|
||||
#define AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58)
|
||||
#define AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C)
|
||||
#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60)
|
||||
#define AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64)
|
||||
#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68)
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -137,24 +137,24 @@
|
||||
|
||||
#define BCM2835_UART0_BASE (RPI_PERIPHERAL_BASE + 0x201000)
|
||||
|
||||
#define BCM2835_UART0_DR (BCM2835_UART0_BASE+0x00)
|
||||
#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE+0x04)
|
||||
#define BCM2835_UART0_FR (BCM2835_UART0_BASE+0x18)
|
||||
#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE+0x20)
|
||||
#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE+0x24)
|
||||
#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE+0x28)
|
||||
#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE+0x2C)
|
||||
#define BCM2835_UART0_CR (BCM2835_UART0_BASE+0x30)
|
||||
#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE+0x34)
|
||||
#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE+0x38)
|
||||
#define BCM2835_UART0_RIS (BCM2835_UART0_BASE+0x3C)
|
||||
#define BCM2835_UART0_MIS (BCM2835_UART0_BASE+0x40)
|
||||
#define BCM2835_UART0_ICR (BCM2835_UART0_BASE+0x44)
|
||||
#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE+0x48)
|
||||
#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE+0x80)
|
||||
#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE+0x84)
|
||||
#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE+0x88)
|
||||
#define BCM2835_UART0_TDR (BCM2835_UART0_BASE+0x8C)
|
||||
#define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00)
|
||||
#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE + 0x04)
|
||||
#define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18)
|
||||
#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20)
|
||||
#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24)
|
||||
#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28)
|
||||
#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C)
|
||||
#define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30)
|
||||
#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE + 0x34)
|
||||
#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE + 0x38)
|
||||
#define BCM2835_UART0_RIS (BCM2835_UART0_BASE + 0x3C)
|
||||
#define BCM2835_UART0_MIS (BCM2835_UART0_BASE + 0x40)
|
||||
#define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44)
|
||||
#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE + 0x48)
|
||||
#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE + 0x80)
|
||||
#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE + 0x84)
|
||||
#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE + 0x88)
|
||||
#define BCM2835_UART0_TDR (BCM2835_UART0_BASE + 0x8C)
|
||||
|
||||
#define BCM2835_UART0_MIS_RX 0x10
|
||||
#define BCM2835_UART0_MIS_TX 0x20
|
||||
@@ -173,16 +173,16 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2835_I2C_BASE (0x20804000)
|
||||
#define BCM2835_I2C_BASE (RPI_PERIPHERAL_BASE + 0x804000)
|
||||
|
||||
#define BCM2835_I2C_C (BCM2835_I2C_BASE+0x00)
|
||||
#define BCM2835_I2C_S (BCM2835_I2C_BASE+0x04)
|
||||
#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE+0x08)
|
||||
#define BCM2835_I2C_A (BCM2835_I2C_BASE+0x0C)
|
||||
#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE+0x10)
|
||||
#define BCM2835_I2C_DIV (BCM2835_I2C_BASE+0x14)
|
||||
#define BCM2835_I2C_DEL (BCM2835_I2C_BASE+0x18)
|
||||
#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE+0x1C)
|
||||
#define BCM2835_I2C_C (BCM2835_I2C_BASE + 0x00)
|
||||
#define BCM2835_I2C_S (BCM2835_I2C_BASE + 0x04)
|
||||
#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE + 0x08)
|
||||
#define BCM2835_I2C_A (BCM2835_I2C_BASE + 0x0C)
|
||||
#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE + 0x10)
|
||||
#define BCM2835_I2C_DIV (BCM2835_I2C_BASE + 0x14)
|
||||
#define BCM2835_I2C_DEL (BCM2835_I2C_BASE + 0x18)
|
||||
#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE + 0x1C)
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -192,14 +192,14 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2835_SPI_BASE (0x20204000)
|
||||
#define BCM2835_SPI_BASE (RPI_PERIPHERAL_BASE + 0x204000)
|
||||
|
||||
#define BCM2835_SPI_CS (BCM2835_SPI_BASE+0x00)
|
||||
#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE+0x04)
|
||||
#define BCM2835_SPI_CLK (BCM2835_SPI_BASE+0x08)
|
||||
#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE+0x0C)
|
||||
#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE+0x10)
|
||||
#define BCM2835_SPI_DC (BCM2835_SPI_BASE+0x14)
|
||||
#define BCM2835_SPI_CS (BCM2835_SPI_BASE + 0x00)
|
||||
#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE + 0x04)
|
||||
#define BCM2835_SPI_CLK (BCM2835_SPI_BASE + 0x08)
|
||||
#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE + 0x0C)
|
||||
#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE + 0x10)
|
||||
#define BCM2835_SPI_DC (BCM2835_SPI_BASE + 0x14)
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -209,22 +209,22 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2835_I2C_SPI_BASE (0x20214000)
|
||||
#define BCM2835_I2C_SPI_BASE (RPI_PERIPHERAL_BASE + 0x214000)
|
||||
|
||||
#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE+0x00)
|
||||
#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE+0x04)
|
||||
#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE+0x08)
|
||||
#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE+0x0C)
|
||||
#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE+0x10)
|
||||
#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE+0x14)
|
||||
#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE+0x18)
|
||||
#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE+0x1C)
|
||||
#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE+0x20)
|
||||
#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE+0x24)
|
||||
#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE+0x28)
|
||||
#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE+0x2C)
|
||||
#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE+0x30)
|
||||
#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE+0x34)
|
||||
#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE + 0x00)
|
||||
#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE + 0x04)
|
||||
#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE + 0x08)
|
||||
#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE + 0x0C)
|
||||
#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE + 0x10)
|
||||
#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE + 0x14)
|
||||
#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE + 0x18)
|
||||
#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE + 0x1C)
|
||||
#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE + 0x20)
|
||||
#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE + 0x24)
|
||||
#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE + 0x28)
|
||||
#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE + 0x2C)
|
||||
#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE + 0x30)
|
||||
#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE + 0x34)
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -262,13 +262,28 @@
|
||||
*/
|
||||
#define BCM2835_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
|
||||
|
||||
#define BCM2835_GPU_TIMER_CS (BCM2835_TIMER_BASE+0x00)
|
||||
#define BCM2835_GPU_TIMER_CLO (BCM2835_TIMER_BASE+0x04)
|
||||
#define BCM2835_GPU_TIMER_CHI (BCM2835_TIMER_BASE+0x08)
|
||||
#define BCM2835_GPU_TIMER_C0 (BCM2835_TIMER_BASE+0x0C)
|
||||
#define BCM2835_GPU_TIMER_C1 (BCM2835_TIMER_BASE+0x10)
|
||||
#define BCM2835_GPU_TIMER_C2 (BCM2835_TIMER_BASE+0x14)
|
||||
#define BCM2835_GPU_TIMER_C3 (BCM2835_TIMER_BASE+0x18)
|
||||
#define BCM2835_GPU_TIMER_CS (BCM2835_TIMER_BASE + 0x00)
|
||||
#define BCM2835_GPU_TIMER_CLO (BCM2835_TIMER_BASE + 0x04)
|
||||
#define BCM2835_GPU_TIMER_CHI (BCM2835_TIMER_BASE + 0x08)
|
||||
#define BCM2835_GPU_TIMER_C0 (BCM2835_TIMER_BASE + 0x0C)
|
||||
#define BCM2835_GPU_TIMER_C1 (BCM2835_TIMER_BASE + 0x10)
|
||||
#define BCM2835_GPU_TIMER_C2 (BCM2835_TIMER_BASE + 0x14)
|
||||
#define BCM2835_GPU_TIMER_C3 (BCM2835_TIMER_BASE + 0x18)
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EMMC Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* NOTE: Since the SD controller follows the SDHCI standard,
|
||||
* the rtems-libbsd tree already provides the remaining registers.
|
||||
*/
|
||||
|
||||
#define BCM2835_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
/**
|
||||
* @file spi.h
|
||||
*
|
||||
* @ingroup raspberrypi_spi
|
||||
*
|
||||
* @brief Raspberry Pi specific SPI definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_RASPBERRYPI_SPI_H
|
||||
#define LIBBSP_ARM_RASPBERRYPI_SPI_H
|
||||
|
||||
#include <rtems/libi2c.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @name SPI constants.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPU processor core clock rate in Hz.
|
||||
*
|
||||
* Unless configured otherwise on a "config.txt" file present on the SD card
|
||||
* the GPU defaults to 250 MHz. Currently only 250 MHz is supported.
|
||||
*/
|
||||
|
||||
/* TODO: It would be nice if this value could be probed at startup, probably
|
||||
* using the Mailbox interface since the usual way of setting this on
|
||||
* the hardware is through a "config.txt" text file on the SD card.
|
||||
* Having this setup on the configure.ac script would require changing
|
||||
* the same setting on two different places. */
|
||||
#define GPU_CORE_CLOCK_RATE 250000000
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI directives.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setups the Raspberry Pi SPI bus (located on the GPIO header)
|
||||
* on the "/dev/spi" device file, and registers the bus on the
|
||||
* libi2c API.
|
||||
*
|
||||
* @param[in] bidirectional_mode If TRUE sets the SPI bus to use 2-wire SPI,
|
||||
* where the MOSI data line doubles as the
|
||||
* slave out (SO) and slave in (SI) data lines.
|
||||
* If FALSE the bus defaults to the usual
|
||||
* 3-wire SPI, with 2 separate data lines
|
||||
* (MOSI and MISO).
|
||||
*
|
||||
* @retval Returns libi2c bus number.
|
||||
* @retval <0 Could not register the bus. See @see rtems_libi2c_register_bus().
|
||||
*/
|
||||
extern int rpi_spi_init(bool bidirectional_mode);
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_RASPBERRYPI_SPI_H */
|
||||
@@ -138,6 +138,14 @@ $(PROJECT_INCLUDE)/bsp/rpi-gpio.h: include/rpi-gpio.h $(PROJECT_INCLUDE)/bsp/$(d
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/rpi-gpio.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rpi-gpio.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/i2c.h: include/i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2c.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/spi.h: include/spi.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/spi.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/spi.h
|
||||
|
||||
$(PROJECT_INCLUDE)/libcpu/cache_.h: ../../../libcpu/arm/shared/include/cache_.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user