mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-22 17:31:01 +08:00
Joel Sherrill
@@ -25,12 +25,6 @@ The following persons/organizations have made contributions:
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||||
examples in the back of the IDP user's manual, and the libgloss example
|
||||
support for the IDP board from the newlib/libgloss distribution.
|
||||
|
||||
+ David Glessner (dwg@glenqcy.glenayre.com) of Glenayre Electronics
|
||||
submitted the support for the Motorola MC68302 CPU. This included
|
||||
the "gen68302" BSP which uses the on-chip peripherals on the MC68302
|
||||
as well as the modifications to the m68k dependent executive code to
|
||||
support m68k family members based on the mc68000 core.
|
||||
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||||
+ Bryce Cogswell (cogswell@cs.uoregon.edu) submitted the support for MS-DOS
|
||||
as a development environment as well as djgpp/go32 as a target environment.
|
||||
|
||||
|
||||
@@ -6,8 +6,6 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
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||||
AC_CONFIG_SUBDIRS([av5282]);;
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||||
csb360 )
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||||
AC_CONFIG_SUBDIRS([csb360]);;
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||||
gen68302 )
|
||||
AC_CONFIG_SUBDIRS([gen68302]);;
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||||
gen68340 )
|
||||
AC_CONFIG_SUBDIRS([gen68340]);;
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||||
gen68360 )
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||||
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||||
@@ -1,60 +0,0 @@
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||||
ACLOCAL_AMFLAGS = -I ../../../../aclocal
|
||||
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||||
include $(top_srcdir)/../../../../automake/compile.am
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||||
|
||||
include_bspdir = $(includedir)/bsp
|
||||
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||||
dist_project_lib_DATA = bsp_specs
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||||
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||||
include_HEADERS = include/bsp.h
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||||
include_HEADERS += ../../shared/include/tm27.h
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||||
|
||||
nodist_include_HEADERS = include/bspopts.h
|
||||
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
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||||
DISTCLEANFILES = include/bspopts.h
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||||
noinst_PROGRAMS =
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||||
include_HEADERS += include/coverhd.h
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||||
include_HEADERS += include/m302_int.h
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||||
|
||||
EXTRA_DIST = times
|
||||
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||||
noinst_LIBRARIES = libbspstart.a
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||||
libbspstart_a_SOURCES = start/start.S
|
||||
project_lib_DATA = start.$(OBJEXT)
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||||
|
||||
dist_project_lib_DATA += startup/linkcmds
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||||
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||||
noinst_LIBRARIES += libbsp.a
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libbsp_a_SOURCES =
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# startup
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||||
libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \
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../../shared/bsppredriverhook.c \
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../../shared/bsppost.c ../../shared/bspstart.c ../../shared/bootcard.c \
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../../shared/bspgetworkarea.c ../../shared/sbrk.c \
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../../shared/setvec.c ../../shared/gnatinstallhandler.c
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# clock
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libbsp_a_SOURCES += clock/ckinit.c
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# console
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libbsp_a_SOURCES += console/console.c ../../shared/dummy_printk_support.c
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# timer
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libbsp_a_SOURCES += timer/timer.c timer/timerisr.S
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if HAS_NETWORKING
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network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
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noinst_PROGRAMS += network.rel
|
||||
network_rel_SOURCES = network/network.c
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||||
network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
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||||
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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||||
endif
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||||
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||||
libbsp_a_LIBADD = \
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||||
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
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||||
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
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if HAS_NETWORKING
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libbsp_a_LIBADD += network.rel
|
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endif
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||||
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/../../../../automake/local.am
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@@ -1,150 +0,0 @@
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BSP NAME: gen68302
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BOARD: proprietary (see below for relevant information)
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||||
BUS: none
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CPU FAMILY: MC68000
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||||
COPROCESSORS: 68302 communications co-processor
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||||
MODE: not applicable
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||||
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||||
DEBUG MONITOR: none
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||||
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||||
PERIPHERALS
|
||||
===========
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||||
TIMERS: two 68302 timers, one 68302 watchdog timer
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||||
RESOLUTION: ?
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||||
SERIAL PORTS: three 68302 SCCs
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||||
REAL-TIME CLOCK:
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||||
DMA: built-in 68302, not used
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VIDEO: none
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SCSI: none
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NETWORKING: none
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DRIVER INFORMATION
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||||
==================
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||||
CLOCK DRIVER: 68302 (TIMER1)
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IOSUPP DRIVER: 68302 SCC2
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SHMSUPP: none
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||||
TIMER DRIVER: 68302 TIMER2
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||||
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||||
STDIO
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=====
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PORT: ?
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||||
ELECTRICAL: EIA-232
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||||
BAUD: 9600
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||||
BITS PER CHARACTER: 8
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||||
PARITY: None
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||||
STOP BITS: 1
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||||
|
||||
NOTES
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=====
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||||
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||||
Board description
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||||
-----------------
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||||
clock rate: 16 MHz
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||||
bus width: 16 bits
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ROM: 128 kbyte (flash, 0 wait states, chip select 0)
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||||
RAM: 256 kbyte (static, 0 wait states, chip select 1)
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||||
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The 68302's built-in DRAM refresh controller circuitry is neither used
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||||
nor configured at startup.
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||||
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Host System
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||||
-----------
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||||
HP 9000/715, HP-UX 9.05
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||||
gcc-2.6.3
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binutils-2.5.2
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||||
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||||
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Verification
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||||
------------
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The 1-ms clock ISR rate was verified with an in-circuit emulator.
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Single processor tests:
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||||
Multi-processort tests: not applicable
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Timing tests: see results in c/src/tests/tmtests/times
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Note: The board has 256 kbyte RAM, so the timing tests would not run
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with the standard executive RAM size configuration of 256 K.
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Modifying the conftbl.h files to specify 160 kbyte for workspace
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seemed to work.
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* Porting
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** Mod c/src/tests/tmtests/*/conftbl.h
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Modified to use 160 kbyte for executive RAM size.
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** Add c/make/custom/gen68302.cfg
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Based on m68k_no_bsp.cfg. Turned off multiprocessor support. Had to
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use a BSP-specific compiler configuration file in order to link the
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proper startup file.
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** Mod c/make/compilers/gcc-m68000.cfg
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Added "-m68000" to the AS macro so that non-68000 instructions are
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neither generated nor allowed (remember that the GNU assembler
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supports pseudo-assembler instructions (e.g. jbsr) that will be
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"intelligently" assembled.) Added "m68000/" before libgcc.a so that
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non-68000 instructions aren't included.
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||||
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** Add c/make/compilers/gcc-gen68302.cfg
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Based on modified gcc-m68000.cfg.
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Changed make-exe define to produce IEEE-695 output files for loading
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into the emulator.
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The board has no debug monitor, so I had to create a 68302-specific
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startup file (c/src/lib/libbsp/m68k/gen68302/start302/start302.s) to
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override the c/src/lib/start/m68k/start.s. START_FILE entry was
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modified to causes start302.s to be linked first (in lieu of start.s).
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** Mod c/src/exec/cpu/m68k/cpu.h
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Turned off software and hardware interrupt stack support. Added
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||||
support in _CPU_Bitfield_Find_first_bit() and
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_CPU_Priority_Bits_index() to replace the bfffo instruction.
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TODO: add software-maintained interrupt stack.
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||||
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||||
TODO: optimize things so that subtracting _priority from 15 isn't
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required in _CPU_Priority_Bits_index().
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||||
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** Mod c/src/exec/cpu/m68k/cpu.c
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Added the log base 2 table (__log2table) that's required by the BFFFO
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replacement in cpu.h.
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||||
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** Mod c/src/exec/cpu/m68k/cpu_asm.s
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Added _ISR_Exit that's currently used in TBD.... Added ifdef wrapper
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around ISR exit code that accessed the format nibble. Added some code
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to restore the status register and call _Thread_Dispatch.
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TODO: add software-maintained interrupt stack.
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||||
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||||
** Mod c/src/exec/cpu/m68k/m68k.h
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Changed "typedef char signed8" to "typedef signed char signed8".
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** Add c/src/lib/libbsp/m68k/gen68302/...
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*** clock/
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TODO: Add set_vector support. Figure out what to do with Clock_exit().
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TODO: Pre-compute (rtems_configuration_get_microseconds_per_tick()/1000) so that
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it doesn't have to be re-computed on each Clock_isr().
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*** console/
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These files assume SCC2, but it shouldn't be too difficult to re-write
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these to use any of the other SCCs.
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*** include/
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*** start302/
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This contains the start302.s file that does some fairly tricky memory
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re-mapping so that RAM ends up at 0 and ROM ends up at 0xc00000.
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||||
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||||
*** startup/
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*** timer/
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*** wrapup/
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||||
@@ -1,13 +0,0 @@
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%rename endfile old_endfile
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||||
%rename startfile old_startfile
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||||
%rename link old_link
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||||
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||||
*startfile:
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||||
%{!qrtems: %(old_startfile)} \
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||||
%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e start}}
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||||
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||||
*link:
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||||
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
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||||
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||||
*endfile:
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||||
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
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@@ -1,101 +0,0 @@
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/*
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* This routine initializes Timer 1 for an MC68302.
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* The tick frequency is 1 millisecond.
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||||
*/
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||||
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||||
/*
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||||
* COPYRIGHT (c) 1989-2014.
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||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
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||||
#include <stdlib.h> /* for atexit() */
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#include <bsp.h>
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||||
#include <rtems/m68k/m68302.h>
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||||
#define CLOCK_VECTOR 137
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||||
#define TMR1_VAL ( RBIT_TMR_RST /* software reset the timer */\
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| RBIT_TMR_ICLK_MASTER16 /* master clock divided by 16 */\
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| RBIT_TMR_FRR /* restart timer after ref reached */\
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| RBIT_TMR_ORI) /* enable interrupt when ref reached */
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#define TRR1_VAL 1000 /* 1000 ticks @ 16MHz/16
|
||||
* = 1 millisecond tick.
|
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*/
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||||
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/*
|
||||
* Clock_driver_ticks is a monotonically increasing counter of the
|
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* number of clock ticks since the driver was initialized.
|
||||
*/
|
||||
volatile uint32_t Clock_driver_ticks;
|
||||
|
||||
/*
|
||||
* Clock_isrs is the number of clock ISRs until the next invocation of
|
||||
* the RTEMS clock tick routine. The clock tick device driver
|
||||
* gets an interrupt once a millisecond and counts down until the
|
||||
* length of time between the user configured microseconds per tick
|
||||
* has passed.
|
||||
*/
|
||||
uint32_t Clock_isrs;
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|
||||
void Clock_exit( void );
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||||
|
||||
/*
|
||||
* ISR Handler
|
||||
*/
|
||||
static rtems_isr Clock_isr(
|
||||
rtems_vector_number vector
|
||||
)
|
||||
{
|
||||
Clock_driver_ticks += 1;
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||||
|
||||
m302.reg.isr = RBIT_ISR_TIMER1; /* clear in-service bit */
|
||||
m302.reg.ter1 = (RBIT_TER_REF | RBIT_TER_CAP); /* clear timer intr request */
|
||||
|
||||
if ( Clock_isrs == 1 ) {
|
||||
rtems_clock_tick();
|
||||
Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000;
|
||||
}
|
||||
else
|
||||
Clock_isrs -= 1;
|
||||
}
|
||||
|
||||
static void Install_clock(
|
||||
rtems_isr_entry clock_isr
|
||||
)
|
||||
{
|
||||
Clock_driver_ticks = 0;
|
||||
Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000;
|
||||
|
||||
set_vector( clock_isr, CLOCK_VECTOR, 1 );
|
||||
|
||||
m302.reg.trr1 = TRR1_VAL; /* set timer reference register */
|
||||
m302.reg.tmr1 = TMR1_VAL; /* set timer mode register & enable */
|
||||
/*
|
||||
* Enable TIMER1 interrupts only.
|
||||
*/
|
||||
m302.reg.imr |= RBIT_IMR_TIMER1; /* set 68302 int-mask to allow ints */
|
||||
|
||||
atexit( Clock_exit );
|
||||
}
|
||||
|
||||
void Clock_exit( void )
|
||||
{
|
||||
/* TODO: figure out what to do here */
|
||||
/* do not restore old vector */
|
||||
}
|
||||
|
||||
rtems_device_driver Clock_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *pargp
|
||||
)
|
||||
{
|
||||
Install_clock( Clock_isr );
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,23 +0,0 @@
|
||||
## Process this file with autoconf to produce a configure script.
|
||||
|
||||
AC_PREREQ([2.69])
|
||||
AC_INIT([rtems-c-src-lib-libbsp-m68k-gen68302],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
|
||||
AC_CONFIG_SRCDIR([bsp_specs])
|
||||
RTEMS_TOP(../../../../../..)
|
||||
|
||||
RTEMS_CANONICAL_TARGET_CPU
|
||||
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
|
||||
RTEMS_BSP_CONFIGURE
|
||||
|
||||
RTEMS_PROG_CC_FOR_TARGET
|
||||
RTEMS_CANONICALIZE_TOOLS
|
||||
RTEMS_PROG_CCAS
|
||||
|
||||
RTEMS_CHECK_NETWORKING
|
||||
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
|
||||
|
||||
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
|
||||
|
||||
# Explicitly list all Makefiles here
|
||||
AC_CONFIG_FILES([Makefile])
|
||||
AC_OUTPUT
|
||||
@@ -1,245 +0,0 @@
|
||||
/*
|
||||
* Initialize the MC68302 SCC2 for console IO board support package.
|
||||
*/
|
||||
|
||||
/*
|
||||
* COPYRIGHT (c) 1989-2014.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#define GEN68302_INIT
|
||||
|
||||
#include <bsp.h>
|
||||
#include <rtems/libio.h>
|
||||
|
||||
#include <rtems/m68k/m68302.h>
|
||||
|
||||
/* console_initialize
|
||||
*
|
||||
* This routine initializes the console IO driver.
|
||||
*/
|
||||
rtems_device_driver console_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *arg
|
||||
)
|
||||
{
|
||||
rtems_status_code status;
|
||||
volatile m302_dualPortRAM_t *p = &m302;
|
||||
|
||||
p->reg.pacnt |= 0x0003; /* enable RXD2 and TXD2 signals */
|
||||
/*
|
||||
* TODO: Check assembly code. I think gcc's volatile semantics force
|
||||
* this to not use a CLR.
|
||||
*/
|
||||
p->reg.simode = 0; /* NMSI mode */
|
||||
|
||||
p->reg.scc[1].scon = 0x00d8; /* 9600 baud */
|
||||
p->reg.scc[1].scm = 0x01b1;
|
||||
|
||||
p->scc2.parm.rfcr = 0x50; /* Rx buffers in supervisor data */
|
||||
p->scc2.parm.tfcr = 0x50; /* Tx buffers in supervisor data */
|
||||
p->scc2.parm.mrblr = 0x0001; /* Max Rx buffer length is 1 byte */
|
||||
|
||||
p->scc2.prot.uart.max_idl = 0x0000; /* 0 = maximum timeout value */
|
||||
p->scc2.prot.uart.brkcr = 0x0001; /* send 1 break char on STOP TX cmd */
|
||||
p->scc2.prot.uart.parec = 0x0000; /* reset parity error counter */
|
||||
p->scc2.prot.uart.frmec = 0x0000; /* reset framing error counter */
|
||||
p->scc2.prot.uart.nosec = 0x0000; /* reset noise error counter */
|
||||
p->scc2.prot.uart.brkec = 0x0000; /* reset break condition counter */
|
||||
|
||||
p->scc2.prot.uart.character[0] = 0x0003; /* use <ctrl>c as control char */
|
||||
p->scc2.prot.uart.character[1] = 0x8000; /* set end of cntrl char table */
|
||||
|
||||
p->scc2.bd.rx[0].status = 0xA000; /* RxBD0 empty, wrap, no intr */
|
||||
p->scc2.bd.rx[0].length = 0x0000;
|
||||
p->scc2.bd.rx[0].buffer =
|
||||
(uint8_t*) &m302.scc2.bd.rx[1]; /* RxBD1 is Rx buffer */
|
||||
|
||||
p->reg.scc[1].dsr = 0x7000; /* set full-length last stop bit */
|
||||
|
||||
p->scc2.bd.tx[0].status = 0x3000; /* TxBD0 not ready, wrap, intr */
|
||||
p->scc2.bd.tx[0].length = 0x0001;
|
||||
p->scc2.bd.tx[0].buffer =
|
||||
(uint8_t*) &m302.scc2.bd.tx[1]; /* TxBD1 is Tx buffer */
|
||||
|
||||
p->reg.scc[1].scce = 0xFF; /* clear all SCC event flags */
|
||||
p->reg.scc[1].sccm = 0x03; /* enable only Tx & Rx interrupts */
|
||||
p->reg.scc[1].scm = 0x01BD;
|
||||
|
||||
status = rtems_io_register_name(
|
||||
"/dev/console",
|
||||
major,
|
||||
(rtems_device_minor_number) 0
|
||||
);
|
||||
|
||||
if (status != RTEMS_SUCCESSFUL)
|
||||
rtems_fatal_error_occurred(status);
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
|
||||
}
|
||||
|
||||
/* inbyte
|
||||
*
|
||||
* Receive a character from the MC68302's SCC2.
|
||||
*/
|
||||
static char inbyte( void )
|
||||
{
|
||||
char ch;
|
||||
|
||||
#define RXS (m302.scc2.bd.rx[0].status)
|
||||
#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer))
|
||||
|
||||
do {
|
||||
while (RXS & RBIT_HDLC_EMPTY_BIT)
|
||||
/* Wait until character received */ ;
|
||||
|
||||
ch = RXD;
|
||||
RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT;
|
||||
|
||||
if (ch == '\r' || ch == '\n')
|
||||
break;
|
||||
} while (ch < ' ' || ch > '~');
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
/* outbyte
|
||||
*
|
||||
* Transmit a character out on the MC68302's SCC2.
|
||||
* It may support XON/XOFF flow control.
|
||||
*/
|
||||
static void outbyte(
|
||||
char ch
|
||||
)
|
||||
{
|
||||
#define TXS (m302.scc2.bd.tx[0].status)
|
||||
#define TXD (* ((volatile char *) m302.scc2.bd.tx[0].buffer))
|
||||
|
||||
#define RXS (m302.scc2.bd.rx[0].status)
|
||||
#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer))
|
||||
|
||||
while (TXS & RBIT_HDLC_READY_BIT)
|
||||
/* Wait until okay to transmit */ ;
|
||||
|
||||
/*
|
||||
* Check for flow control requests and process.
|
||||
*/
|
||||
while ( ! (RXS & RBIT_HDLC_EMPTY_BIT)) {
|
||||
if (RXD == XOFF) {
|
||||
do {
|
||||
RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT;
|
||||
while (RXS & RBIT_HDLC_EMPTY_BIT)
|
||||
/* Wait until character received */ ;
|
||||
} while (RXD != XON);
|
||||
RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT;
|
||||
}
|
||||
}
|
||||
|
||||
TXD = ch;
|
||||
TXS = RBIT_HDLC_READY_BIT | RBIT_HDLC_WRAP_BIT;
|
||||
if (ch == '\n')
|
||||
outbyte('\r');
|
||||
}
|
||||
|
||||
/*
|
||||
* Open entry point
|
||||
*/
|
||||
rtems_device_driver console_open(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Close entry point
|
||||
*/
|
||||
rtems_device_driver console_close(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/*
|
||||
* read bytes from the serial port. We only have stdin.
|
||||
*/
|
||||
rtems_device_driver console_read(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
rtems_libio_rw_args_t *rw_args;
|
||||
char *buffer;
|
||||
int maximum;
|
||||
int count = 0;
|
||||
|
||||
rw_args = (rtems_libio_rw_args_t *) arg;
|
||||
|
||||
buffer = rw_args->buffer;
|
||||
maximum = rw_args->count;
|
||||
|
||||
for (count = 0; count < maximum; count++) {
|
||||
buffer[ count ] = inbyte();
|
||||
if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
|
||||
buffer[ count++ ] = '\n';
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
rw_args->bytes_moved = count;
|
||||
return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
|
||||
}
|
||||
|
||||
/*
|
||||
* write bytes to the serial port. Stdout and stderr are the same.
|
||||
*/
|
||||
rtems_device_driver console_write(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
int count;
|
||||
int maximum;
|
||||
rtems_libio_rw_args_t *rw_args;
|
||||
char *buffer;
|
||||
|
||||
rw_args = (rtems_libio_rw_args_t *) arg;
|
||||
|
||||
buffer = rw_args->buffer;
|
||||
maximum = rw_args->count;
|
||||
|
||||
for (count = 0; count < maximum; count++) {
|
||||
if ( buffer[ count ] == '\n') {
|
||||
outbyte('\r');
|
||||
}
|
||||
outbyte( buffer[ count ] );
|
||||
}
|
||||
|
||||
rw_args->bytes_moved = maximum;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* IO Control entry point
|
||||
*/
|
||||
rtems_device_driver console_control(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,72 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup m68k_gen68302
|
||||
*
|
||||
* @brief Global BSP definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_M68K_GEN68302_BSP_H
|
||||
#define LIBBSP_M68K_GEN68302_BSP_H
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <bsp/default-initial-extension.h>
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/iosupp.h>
|
||||
#include <rtems/clockdrv.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup m68k_gen68302 GEN68302 Support
|
||||
*
|
||||
* @ingroup bsp_m68k
|
||||
*
|
||||
* @brief GEN68302 support.
|
||||
*/
|
||||
|
||||
/* Constants */
|
||||
|
||||
#define RAM_START 0
|
||||
#define RAM_END 0x040000
|
||||
|
||||
/* Structures */
|
||||
|
||||
#ifdef GEN68302_INIT
|
||||
#undef EXTERN
|
||||
#define EXTERN
|
||||
#else
|
||||
#undef EXTERN
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* miscellaneous stuff assumed to exist */
|
||||
|
||||
extern rtems_isr_entry M68Kvec[]; /* vector table address */
|
||||
|
||||
/* functions */
|
||||
|
||||
rtems_isr_entry set_vector(
|
||||
rtems_isr_entry handler,
|
||||
rtems_vector_number vector,
|
||||
int type
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,119 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup m68k_gen68302
|
||||
*
|
||||
* @brief C overhead definitions.
|
||||
*/
|
||||
|
||||
/* coverhd.h
|
||||
*
|
||||
* This include file has defines to represent the overhead associated
|
||||
* with calling a particular directive from C. These are used in the
|
||||
* Timing Test Suite to ignore the overhead required to pass arguments
|
||||
* to directives. On some CPUs and/or target boards, this overhead
|
||||
* is significant and makes it difficult to distinguish internal
|
||||
* RTEMS execution time from that used to call the directive.
|
||||
* This file should be updated after running the C overhead timing
|
||||
* test. Once this update has been performed, the RTEMS Time Test
|
||||
* Suite should be rebuilt to account for these overhead times in the
|
||||
* timing results.
|
||||
*
|
||||
* NOTE: If these are all zero, then the times reported include
|
||||
* all calling overhead including passing of arguments.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef __COVERHD_h
|
||||
#define __COVERHD_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 14
|
||||
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 11
|
||||
#define CALLING_OVERHEAD_TASK_CREATE 22
|
||||
#define CALLING_OVERHEAD_TASK_IDENT 17
|
||||
#define CALLING_OVERHEAD_TASK_START 18
|
||||
#define CALLING_OVERHEAD_TASK_RESTART 15
|
||||
#define CALLING_OVERHEAD_TASK_DELETE 12
|
||||
#define CALLING_OVERHEAD_TASK_SUSPEND 12
|
||||
#define CALLING_OVERHEAD_TASK_RESUME 12
|
||||
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 16
|
||||
#define CALLING_OVERHEAD_TASK_MODE 15
|
||||
#define CALLING_OVERHEAD_TASK_GET_NOTE 16
|
||||
#define CALLING_OVERHEAD_TASK_SET_NOTE 16
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 31
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 11
|
||||
#define CALLING_OVERHEAD_INTERRUPT_CATCH 17
|
||||
#define CALLING_OVERHEAD_CLOCK_GET 32
|
||||
#define CALLING_OVERHEAD_CLOCK_SET 31
|
||||
#define CALLING_OVERHEAD_CLOCK_TICK 8
|
||||
|
||||
#define CALLING_OVERHEAD_TIMER_CREATE 13
|
||||
#define CALLING_OVERHEAD_TIMER_IDENT 12
|
||||
#define CALLING_OVERHEAD_TIMER_DELETE 14
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 19
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 39
|
||||
#define CALLING_OVERHEAD_TIMER_RESET 12
|
||||
#define CALLING_OVERHEAD_TIMER_CANCEL 12
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 18
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 12
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 17
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 17
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 12
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 18
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 17
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 12
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 14
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 14
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 17
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 19
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 14
|
||||
|
||||
#define CALLING_OVERHEAD_EVENT_SEND 15
|
||||
#define CALLING_OVERHEAD_EVENT_RECEIVE 18
|
||||
#define CALLING_OVERHEAD_SIGNAL_CATCH 14
|
||||
#define CALLING_OVERHEAD_SIGNAL_SEND 14
|
||||
#define CALLING_OVERHEAD_PARTITION_CREATE 23
|
||||
#define CALLING_OVERHEAD_PARTITION_IDENT 17
|
||||
#define CALLING_OVERHEAD_PARTITION_DELETE 12
|
||||
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 15
|
||||
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 15
|
||||
#define CALLING_OVERHEAD_REGION_CREATE 23
|
||||
#define CALLING_OVERHEAD_REGION_IDENT 14
|
||||
#define CALLING_OVERHEAD_REGION_DELETE 12
|
||||
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 21
|
||||
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 15
|
||||
#define CALLING_OVERHEAD_PORT_CREATE 20
|
||||
#define CALLING_OVERHEAD_PORT_IDENT 14
|
||||
#define CALLING_OVERHEAD_PORT_DELETE 12
|
||||
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 18
|
||||
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 18
|
||||
|
||||
#define CALLING_OVERHEAD_IO_INITIALIZE 18
|
||||
#define CALLING_OVERHEAD_IO_OPEN 18
|
||||
#define CALLING_OVERHEAD_IO_CLOSE 18
|
||||
#define CALLING_OVERHEAD_IO_READ 18
|
||||
#define CALLING_OVERHEAD_IO_WRITE 18
|
||||
#define CALLING_OVERHEAD_IO_CONTROL 18
|
||||
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 11
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 13
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 14
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 12
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 12
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 14
|
||||
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 8
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
#
|
||||
# Config file for a "generic 68302" BSP
|
||||
#
|
||||
|
||||
include $(RTEMS_ROOT)/make/custom/default.cfg
|
||||
|
||||
RTEMS_CPU=m68k
|
||||
RTEMS_CPU_MODEL=m68302
|
||||
|
||||
#
|
||||
# This contains the compiler options necessary to select the CPU model
|
||||
# and (hopefully) optimize for it.
|
||||
CPU_CFLAGS = -mcpu=68302
|
||||
|
||||
# optimize flag: typically -O2
|
||||
CFLAGS_OPTIMIZE_V = -O2 -g -fomit-frame-pointer
|
||||
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
|
||||
|
||||
LDFLAGS = -Wl,--gc-sections
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,71 +0,0 @@
|
||||
## Automatically generated by ampolish3 - Do not edit
|
||||
|
||||
if AMPOLISH3
|
||||
$(srcdir)/preinstall.am: Makefile.am
|
||||
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
|
||||
endif
|
||||
|
||||
PREINSTALL_DIRS =
|
||||
DISTCLEANFILES += $(PREINSTALL_DIRS)
|
||||
|
||||
all-am: $(PREINSTALL_FILES)
|
||||
|
||||
PREINSTALL_FILES =
|
||||
CLEANFILES = $(PREINSTALL_FILES)
|
||||
|
||||
all-local: $(TMPINSTALL_FILES)
|
||||
|
||||
TMPINSTALL_FILES =
|
||||
CLEANFILES += $(TMPINSTALL_FILES)
|
||||
|
||||
$(PROJECT_LIB)/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_LIB)
|
||||
@: > $(PROJECT_LIB)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)
|
||||
@: > $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
|
||||
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
|
||||
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
|
||||
|
||||
$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
|
||||
|
||||
$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
|
||||
|
||||
$(PROJECT_INCLUDE)/m302_int.h: include/m302_int.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/m302_int.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/m302_int.h
|
||||
|
||||
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
|
||||
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
|
||||
|
||||
@@ -1,255 +0,0 @@
|
||||
/* entry.s
|
||||
*
|
||||
* This file contains the entry point for the application.
|
||||
* The name of this entry point is compiler dependent.
|
||||
* It jumps to the BSP which is responsible for performing
|
||||
* all initialization.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <rtems/asm.h>
|
||||
|
||||
.set BAR, 0xF2 | Base Address Register location
|
||||
.set SCR, 0xF4 | System Control Register location
|
||||
.set BAR_VAL, 0x0f7f | BAR value
|
||||
.set SCR_VAL, 0x00080f00 | SCR value
|
||||
.set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN).
|
||||
.set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address
|
||||
|
||||
.set oSYSRAM, 0x000 | 576 bytes of internal system RAM
|
||||
|
||||
.set oGIMR, 0x812
|
||||
|
||||
.set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg
|
||||
.set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg
|
||||
.set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg
|
||||
.set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg
|
||||
.set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg
|
||||
.set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg
|
||||
.set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg
|
||||
.set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg
|
||||
|
||||
.set tmpSRAM_BASE, 0x400000 | start of temporary SRAM
|
||||
.set FLASH_BASE, 0xc00000 | start of FLASH''s normal location
|
||||
|
||||
BEGIN_CODE
|
||||
PUBLIC (M68Kvec) | Vector Table
|
||||
SYM (M68Kvec): | standard location for vectors
|
||||
V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP
|
||||
V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC
|
||||
V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error
|
||||
V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error
|
||||
.space 240 | reserve space for reset of vectors
|
||||
|
||||
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
|
||||
SYM (lowintstack):
|
||||
.space 4092 | reserve for interrupt stack
|
||||
SYM (hiintstack):
|
||||
.space 4 | end of interrupt stack
|
||||
#endif
|
||||
|
||||
PUBLIC (start) | Default entry point for GNU
|
||||
SYM (start):
|
||||
move.w #0x2700,sr | Disable all interrupts
|
||||
move.w #BAR_VAL,BAR | Set Base Address Register
|
||||
move.l #SCR_VAL,SCR | Set System Control Register
|
||||
lea BaseAddr,a5
|
||||
move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register
|
||||
|
||||
|
|
||||
| Set up chip select registers for the remapping process.
|
||||
|
|
||||
|
||||
|
|
||||
| 0 X x x x x
|
||||
| 0 000 0 0-- - --- ---- ---- ----
|
||||
| x xxx x xxx x xx
|
||||
|
|
||||
move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH)
|
||||
move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS
|
||||
|
||||
|
|
||||
| X x x x x x
|
||||
| 0 100 0 0-- - --- ---- ---- ----
|
||||
| x xxx x xxx x xx
|
||||
|
|
||||
move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM)
|
||||
move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS
|
||||
|
||||
|
|
||||
| Copy the initial boot FLASH area to the temporary SRAM location.
|
||||
|
|
||||
moveq #0,d0
|
||||
movea.l d0,a0 | a0 -> start of FLASH
|
||||
lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM
|
||||
| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy
|
||||
moveq #127,d0
|
||||
cpy_flash: move.l (a0)+,(a1)+ | copy
|
||||
subq.l #1,d0
|
||||
bne cpy_flash
|
||||
|
||||
|
|
||||
| Copy remap code to 68302''s internal system RAM.
|
||||
|
|
||||
movea.w #begRemap-V___ISSP,a0 | a0 -> remap code
|
||||
lea a5@(oSYSRAM),a1 | a1 -> internal system RAM
|
||||
| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy
|
||||
moveq #11,d0
|
||||
cpy_remap: move.w (a0)+,(a1)+ | copy
|
||||
dbra d0,cpy_remap
|
||||
|
||||
|
|
||||
| Jump to the remap code in the 68302''s internal system RAM.
|
||||
|
|
||||
jmp a5@(oSYSRAM) | (effectively a jmp begRemap)
|
||||
|
||||
|
|
||||
| This remap code, when executed from the 68302''s internal system RAM
|
||||
| will 1) remap CS1 so that SRAM is at 0
|
||||
| 2) remap CS0 so that FLASH is at FLASH_BASE
|
||||
| and 3) jump to executable code in the remapped FLASH.
|
||||
|
|
||||
begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM)
|
||||
move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH)
|
||||
lea FLASH_BASE,a0
|
||||
jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH
|
||||
endRemap:
|
||||
|
|
||||
| Now set up the remaining chip select registers.
|
||||
|
|
||||
|
||||
|
|
||||
| 4 0 x x x x
|
||||
| 1 000 1 111 0 000 0--- ---- ----
|
||||
| x xxx x xxx x xx
|
||||
|
|
||||
move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM)
|
||||
move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS
|
||||
|
||||
|
|
||||
| 8 X x x x x
|
||||
| 1 000 0 0-- - --- ---- ---- ----
|
||||
| x xxx x xxx x xx
|
||||
|
|
||||
move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO)
|
||||
move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS
|
||||
|
||||
endPreBoot:
|
||||
|
||||
move.b #0x30,0x800001 | set status LED amber
|
||||
|
||||
.set oPIOB_Ctrl, 0x824
|
||||
.set oPIOB_DDR, 0x826
|
||||
.set oPIOB_Data, 0x828
|
||||
|
||||
.set oPIOA_Ctrl, 0x81e
|
||||
.set oPIOA_DDR, 0x820
|
||||
.set oPIOA_Data, 0x822
|
||||
|
||||
move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors.
|
||||
move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output.
|
||||
move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated
|
||||
| peripheral pins.
|
||||
|
||||
move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors.
|
||||
move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output.
|
||||
move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated
|
||||
| peripheral pins.
|
||||
|
||||
|
|
||||
| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4
|
||||
| are not set because they are the 68302''s BAR and SCR.
|
||||
|
|
||||
movea.w #0x010,a0
|
||||
moveq #(0x0f0-0x010)/4-1,d0
|
||||
move.l #Bad,d1
|
||||
cpy_Bad: move.l d1,(a0)+
|
||||
dbra d0,cpy_Bad
|
||||
|
||||
.set vbase, 0x0200
|
||||
|
||||
lea vbase,a0
|
||||
moveq #31,d0
|
||||
cpy_Bad1: move.l d1,(a0)+
|
||||
dbra d0,cpy_Bad1
|
||||
|
||||
|
|
||||
| Fill in special locations to configure OS
|
||||
|
|
||||
move.l #Bad,0x008 | Bus Error
|
||||
move.l #Bad,0x00c | Address Error
|
||||
move.l #Bad,0x024 | Trace
|
||||
| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call
|
||||
|
||||
| move.l #_cnsl_isr,vbase+0x028 | SCC2
|
||||
move.l #timerisr,vbase+0x018 | Timer ISR
|
||||
|
||||
|
|
||||
| zero out uninitialized data area
|
||||
|
|
||||
zerobss:
|
||||
moveal # SYM (_clear_end),a0 | find end of .bss
|
||||
moveal # SYM (_clear_start),a1 | find beginning of .bss
|
||||
moveq #0,d0
|
||||
|
||||
loop: movel d0,a1@+ | to zero out uninitialized
|
||||
cmpal a0,a1
|
||||
jlt loop | loop until _clear_end reached
|
||||
|
||||
movel d0, SYM (_stack_init) | Set Stack pointer
|
||||
movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!!
|
||||
movel d0,a7 | set master stack pointer
|
||||
movel d0,a6 | set base pointer
|
||||
|
||||
/*
|
||||
* RTEMS should maintain a separate interrupt stack on CPUs
|
||||
* without one in hardware. This is currently not supported
|
||||
* on versions of the m68k without a HW intr stack.
|
||||
*/
|
||||
|
||||
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
|
||||
lea SYM (hiintstack),a0 | a0 = high end of intr stack
|
||||
movec a0,isp | set interrupt stack
|
||||
#endif
|
||||
|
||||
move.l #0,a7@- | command line
|
||||
jsr SYM (boot_card)
|
||||
|
||||
nop
|
||||
Bad: bra Bad
|
||||
|
||||
nop
|
||||
END_CODE
|
||||
|
||||
BEGIN_DATA
|
||||
|
||||
PUBLIC (start_frame)
|
||||
SYM (start_frame):
|
||||
.space 4,0
|
||||
|
||||
PUBLIC (stack_start)
|
||||
SYM (stack_start):
|
||||
.space 4,0
|
||||
END_DATA
|
||||
|
||||
BEGIN_BSS
|
||||
|
||||
PUBLIC (environ)
|
||||
.align 2
|
||||
SYM (environ):
|
||||
.long 0
|
||||
|
||||
PUBLIC (heap_size)
|
||||
.set SYM (heap_size),0x2000
|
||||
|
||||
PUBLIC (stack_size)
|
||||
.set SYM (stack_size),0x1000
|
||||
|
||||
END_DATA
|
||||
END
|
||||
@@ -1,204 +0,0 @@
|
||||
/*
|
||||
* This file contains directives for the GNU linker which are specific
|
||||
* to the Generic MC68302 board.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-2007.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram : org = 0x0000, l = 16M
|
||||
}
|
||||
|
||||
m302 = 0xf7f000;
|
||||
_VBR = 0x000000; /* location of the VBR table (in RAM) */
|
||||
|
||||
/*
|
||||
* Declare some sizes.
|
||||
*/
|
||||
RamBase = DEFINED(RamBase) ? RamBase : 0x0;
|
||||
RamSize = DEFINED(RamSize) ? RamSize : 16M;
|
||||
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
|
||||
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
ram : {
|
||||
. = 0xc00000;
|
||||
} >ram
|
||||
|
||||
/*
|
||||
* Text, data and bss segments
|
||||
*/
|
||||
.text : {
|
||||
*(.text*)
|
||||
|
||||
/*
|
||||
* C++ constructors/destructors
|
||||
*/
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
/*
|
||||
* Initialization and finalization code.
|
||||
*
|
||||
* Various files can provide initialization and finalization
|
||||
* functions. crtbegin.o and crtend.o are two instances. The
|
||||
* body of these functions are in .init and .fini sections. We
|
||||
* accumulate the bodies here, and prepend function prologues
|
||||
* from crti.o and function epilogues from crtn.o. crti.o must
|
||||
* be linked first; crtn.o must be linked last. Because these
|
||||
* are wildcards, it doesn't matter if the user does not
|
||||
* actually link against crti.o and crtn.o; the linker won't
|
||||
* look for a file to match a wildcard. The wildcard also
|
||||
* means that it doesn't matter which directory crti.o and
|
||||
* crtn.o are in.
|
||||
*/
|
||||
PROVIDE (_init = .);
|
||||
*crti.o(.init)
|
||||
*(.init)
|
||||
*crtn.o(.init)
|
||||
PROVIDE (_fini = .);
|
||||
*crti.o(.fini)
|
||||
*(.fini)
|
||||
*crtn.o(.fini)
|
||||
|
||||
/*
|
||||
* Special FreeBSD sysctl sections.
|
||||
*/
|
||||
. = ALIGN (16);
|
||||
__start_set_sysctl_set = .;
|
||||
*(set_sysctl_*);
|
||||
__stop_set_sysctl_set = ABSOLUTE(.);
|
||||
*(set_domain_*);
|
||||
*(set_pseudo_*);
|
||||
|
||||
/*
|
||||
* C++ constructors/destructors
|
||||
*
|
||||
* gcc uses crtbegin.o to find the start of the constructors
|
||||
* and destructors so we make sure it is first. Because this
|
||||
* is a wildcard, it doesn't matter if the user does not
|
||||
* actually link against crtbegin.o; the linker won't look for
|
||||
* a file to match a wildcard. The wildcard also means that
|
||||
* it doesn't matter which directory crtbegin.o is in. The
|
||||
* constructor and destructor list are terminated in
|
||||
* crtend.o. The same comments apply to it.
|
||||
*/
|
||||
. = ALIGN (16);
|
||||
*crtbegin.o(.ctors)
|
||||
*(.ctors)
|
||||
*crtend.o(.ctors)
|
||||
*crtbegin.o(.dtors)
|
||||
*(.dtors)
|
||||
*crtend.o(.dtors)
|
||||
|
||||
/*
|
||||
* Exception frame info
|
||||
*/
|
||||
. = ALIGN (16);
|
||||
*(.eh_frame)
|
||||
|
||||
/*
|
||||
* Read-only data
|
||||
*/
|
||||
. = ALIGN (16);
|
||||
_rodata_start = . ;
|
||||
*(.rodata*)
|
||||
KEEP (*(SORT(.rtemsroset.*)))
|
||||
*(.gnu.linkonce.r*)
|
||||
|
||||
. = ALIGN (16);
|
||||
PROVIDE (_etext = .);
|
||||
} >ram
|
||||
|
||||
.tdata : {
|
||||
_TLS_Data_begin = .;
|
||||
*(.tdata .tdata.* .gnu.linkonce.td.*)
|
||||
_TLS_Data_end = .;
|
||||
} >ram
|
||||
|
||||
.tbss : {
|
||||
_TLS_BSS_begin = .;
|
||||
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
|
||||
_TLS_BSS_end = .;
|
||||
} >ram
|
||||
|
||||
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
|
||||
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
|
||||
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
|
||||
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
|
||||
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
|
||||
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
|
||||
|
||||
.data : {
|
||||
PROVIDE (_copy_start = .);
|
||||
*(.data*)
|
||||
KEEP (*(SORT(.rtemsrwset.*)))
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.gcc_except_table*)
|
||||
*(.jcr)
|
||||
. = ALIGN (16);
|
||||
PROVIDE (_edata = .);
|
||||
PROVIDE (_copy_end = .);
|
||||
} >ram
|
||||
.bss : {
|
||||
_clear_start = .;
|
||||
*(.dynbss)
|
||||
*(.bss* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (16);
|
||||
PROVIDE (end = .);
|
||||
|
||||
. += _StackSize;
|
||||
. = ALIGN (16);
|
||||
_stack_init = .;
|
||||
_clear_end = .;
|
||||
|
||||
WorkAreaBase = .;
|
||||
} >ram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* These must appear regardless of . */
|
||||
}
|
||||
@@ -1,105 +0,0 @@
|
||||
/*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
#include <rtems/btimer.h>
|
||||
#include <rtems/m68k/m68302.h>
|
||||
|
||||
#define TMR2_VAL 0x071b /* Timer mode register
|
||||
* (section 3.5.2.1 in 68302 manual)
|
||||
* 15-8: "7" prescaler divide by 8 (x+1)
|
||||
* 7-6: 00 dis. intr. on capture event
|
||||
* 5: 0 active-low pulse
|
||||
* 4: 1 intr. on reaching reference
|
||||
* 3: 1 restart counter on reference
|
||||
* 2-1: 01 master clock input source
|
||||
* 0: 1 enable timer
|
||||
*/
|
||||
#define TRR2_VAL 2000 /* Timer reference register
|
||||
* (section 3.5.2.2 in 68302 manual)
|
||||
* 2000 ticks @ (16MHz/1)/8 = 1-ms count
|
||||
*/
|
||||
|
||||
uint32_t Timer_interrupts;
|
||||
|
||||
bool benchmark_timer_find_average_overhead;
|
||||
|
||||
rtems_isr timerisr(void);
|
||||
|
||||
void benchmark_timer_initialize( void )
|
||||
{
|
||||
m302.reg.tmr2 = 0; /* disable timer */
|
||||
|
||||
Timer_interrupts = 0; /* clear timer ISR count */
|
||||
|
||||
m302.reg.trr2 = TRR2_VAL; /* set timer reference register */
|
||||
m302.reg.tmr2 = TMR2_VAL; /* set timer mode register */
|
||||
m302.reg.imr |= RBIT_IMR_TIMER2; /* set 68302 int-mask to allow ints */
|
||||
}
|
||||
|
||||
/*
|
||||
* The following controls the behavior of benchmark_timer_read().
|
||||
*
|
||||
* FIND_AVG_OVERHEAD * instructs the routine to return the "raw" count.
|
||||
*
|
||||
* AVG_OVEREHAD is the overhead for starting and stopping the timer. It
|
||||
* is usually deducted from the number returned.
|
||||
*
|
||||
* LEAST_VALID is the lowest number this routine should trust. Numbers
|
||||
* below this are "noise" and zero is returned.
|
||||
*/
|
||||
|
||||
#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */
|
||||
/* (Y countdowns) to start/stop the timer. */
|
||||
/* This value is in microseconds. */
|
||||
#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */
|
||||
|
||||
/*
|
||||
* Return timer value in 1/2-microsecond units
|
||||
*/
|
||||
benchmark_timer_t benchmark_timer_read( void )
|
||||
{
|
||||
uint16_t clicks;
|
||||
uint32_t total;
|
||||
|
||||
/*
|
||||
* Read the timer and see how many clicks it has been since counter
|
||||
* rolled over.
|
||||
*/
|
||||
|
||||
clicks = m302.reg.tcn2;
|
||||
|
||||
/*
|
||||
* Total is calculated by taking into account the number of timer overflow
|
||||
* interrupts since the timer was initialized and clicks since the last
|
||||
* interrupts.
|
||||
*/
|
||||
|
||||
total = (Timer_interrupts * TRR2_VAL) + clicks;
|
||||
|
||||
if ( benchmark_timer_find_average_overhead == true )
|
||||
return total; /* in XXX microsecond units */
|
||||
|
||||
if ( total < LEAST_VALID )
|
||||
return 0; /* below timer resolution */
|
||||
|
||||
/*
|
||||
* Convert 1/2-microsecond count into microseconds
|
||||
*/
|
||||
|
||||
return (total - AVG_OVERHEAD) >> 1;
|
||||
}
|
||||
|
||||
void benchmark_timer_disable_subtracting_average_overhead(
|
||||
bool find_flag
|
||||
)
|
||||
{
|
||||
benchmark_timer_find_average_overhead = find_flag;
|
||||
}
|
||||
@@ -1,26 +0,0 @@
|
||||
/*
|
||||
* Handle 68302 TIMER2 interrupts.
|
||||
*
|
||||
* All code in this routine is pure overhead which can perturb the
|
||||
* accuracy of RTEMS' timing test suite.
|
||||
*
|
||||
* See also: benchmark_timer_read()
|
||||
*
|
||||
* To reduce overhead this is best to be the "rawest" hardware interupt
|
||||
* handler you can write. This should be the only interrupt which can
|
||||
* occur during the measured time period.
|
||||
*
|
||||
* An external counter, Timer_interrupts, is incremented.
|
||||
*/
|
||||
|
||||
#include <rtems/asm.h>
|
||||
|
||||
BEGIN_CODE
|
||||
PUBLIC(timerisr)
|
||||
SYM(timerisr):
|
||||
move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit
|
||||
move.b #3,SYM(m302)+2137 | clear timer interrupt event register
|
||||
addq.l #1,SYM(Timer_interrupts) | increment timer value
|
||||
rte
|
||||
END_CODE
|
||||
END
|
||||
@@ -1,189 +0,0 @@
|
||||
#
|
||||
# Timing Test Suite Results for the generic 68302 BSP
|
||||
#
|
||||
|
||||
NOTE: This BSP is used submitted and no information is currently available.
|
||||
|
||||
Board: gen68302
|
||||
CPU: Motorola 68302
|
||||
Clock Speed: 16 Mhz
|
||||
Memory Configuration: SRAM, DRAM, cache, etc
|
||||
Wait States:
|
||||
|
||||
Times Reported in: cycles, microseconds, etc
|
||||
Timer Source: Count Down Timer, on-CPU cycle counter, etc
|
||||
|
||||
Column A: unused
|
||||
Column B: unused
|
||||
|
||||
# DESCRIPTION A B
|
||||
== ================================================================= ==== ====
|
||||
1 rtems_semaphore_create 20
|
||||
rtems_semaphore_delete 21
|
||||
rtems_semaphore_obtain: available 15
|
||||
rtems_semaphore_obtain: not available -- NO_WAIT 15
|
||||
rtems_semaphore_release: no waiting tasks 16
|
||||
|
||||
2 rtems_semaphore_obtain: not available -- caller blocks 62
|
||||
|
||||
3 rtems_semaphore_release: task readied -- preempts caller 55
|
||||
|
||||
4 rtems_task_restart: blocked task -- preempts caller 77
|
||||
rtems_task_restart: ready task -- preempts caller 70
|
||||
rtems_semaphore_release: task readied -- returns to caller 25
|
||||
rtems_task_create 57
|
||||
rtems_task_start 31
|
||||
rtems_task_restart: suspended task -- returns to caller 36
|
||||
rtems_task_delete: suspended task 47
|
||||
rtems_task_restart: ready task -- returns to caller 37
|
||||
rtems_task_restart: blocked task -- returns to caller 46
|
||||
rtems_task_delete: blocked task 50
|
||||
|
||||
5 rtems_task_suspend: calling task 51
|
||||
rtems_task_resume: task readied -- preempts caller 49
|
||||
|
||||
6 rtems_task_restart: calling task 59
|
||||
rtems_task_suspend: returns to caller 18
|
||||
rtems_task_resume: task readied -- returns to caller 19
|
||||
rtems_task_delete: ready task 50
|
||||
|
||||
7 rtems_task_restart: suspended task -- preempts caller 70
|
||||
|
||||
8 rtems_task_set_priority: obtain current priority 12
|
||||
rtems_task_set_priority: returns to caller 27
|
||||
rtems_task_mode: obtain current mode 5
|
||||
rtems_task_mode: no reschedule 5
|
||||
rtems_task_mode: reschedule -- returns to caller 8
|
||||
rtems_task_mode: reschedule -- preempts caller 39
|
||||
rtems_clock_set 33
|
||||
rtems_clock_get 3
|
||||
|
||||
9 rtems_message_queue_create 110
|
||||
rtems_message_queue_send: no waiting tasks 37
|
||||
rtems_message_queue_urgent: no waiting tasks 37
|
||||
rtems_message_queue_receive: available 31
|
||||
rtems_message_queue_flush: no messages flushed 12
|
||||
rtems_message_queue_flush: messages flushed 16
|
||||
rtems_message_queue_delete 26
|
||||
|
||||
10 rtems_message_queue_receive: not available -- NO_WAIT 15
|
||||
rtems_message_queue_receive: not available -- caller blocks 62
|
||||
|
||||
11 rtems_message_queue_send: task readied -- preempts caller 72
|
||||
|
||||
12 rtems_message_queue_send: task readied -- returns to caller 39
|
||||
|
||||
13 rtems_message_queue_urgent: task readied -- preempts caller 72
|
||||
|
||||
14 rtems_message_queue_urgent: task readied -- returns to caller 39
|
||||
|
||||
15 rtems_event_receive: obtain current events 1
|
||||
rtems_event_receive: not available -- NO_WAIT 12
|
||||
rtems_event_receive: not available -- caller blocks 56
|
||||
rtems_event_send: no task readied 12
|
||||
rtems_event_receive: available 12
|
||||
rtems_event_send: task readied -- returns to caller 24
|
||||
|
||||
16 rtems_event_send: task readied -- preempts caller 55
|
||||
|
||||
17 rtems_task_set_priority: preempts caller 62
|
||||
|
||||
18 rtems_task_delete: calling task 83
|
||||
|
||||
19 rtems_signal_catch 9
|
||||
rtems_signal_send: returns to caller 15
|
||||
rtems_signal_send: signal to self 18
|
||||
exit ASR overhead: returns to calling task 22
|
||||
exit ASR overhead: returns to preempting task 49
|
||||
|
||||
20 rtems_partition_create 35
|
||||
rtems_region_create 23
|
||||
rtems_partition_get_buffer: available 15
|
||||
rtems_partition_get_buffer: not available 13
|
||||
rtems_partition_return_buffer 18
|
||||
rtems_partition_delete 16
|
||||
rtems_region_get_segment: available 22
|
||||
rtems_region_get_segment: not available -- NO_WAIT 21
|
||||
rtems_region_return_segment: no waiting tasks 19
|
||||
rtems_region_get_segment: not available -- caller blocks 64
|
||||
rtems_region_return_segment: task readied -- preempts caller 74
|
||||
rtems_region_return_segment: task readied -- returns to caller 44
|
||||
rtems_region_delete 16
|
||||
rtems_io_initialize 2
|
||||
rtems_io_open 1
|
||||
rtems_io_close 1
|
||||
rtems_io_read 1
|
||||
rtems_io_write 1
|
||||
rtems_io_control 1
|
||||
|
||||
21 rtems_task_ident 149
|
||||
rtems_message_queue_ident 145
|
||||
rtems_semaphore_ident 156
|
||||
rtems_partition_ident 145
|
||||
rtems_region_ident 148
|
||||
rtems_port_ident 145
|
||||
rtems_timer_ident 145
|
||||
rtems_rate_monotonic_ident 145
|
||||
|
||||
22 rtems_message_queue_broadcast: task readied -- returns to caller 42
|
||||
rtems_message_queue_broadcast: no waiting tasks 17
|
||||
rtems_message_queue_broadcast: task readied -- preempts caller 78
|
||||
|
||||
23 rtems_timer_create 14
|
||||
rtems_timer_fire_after: inactive 22
|
||||
rtems_timer_fire_after: active 24
|
||||
rtems_timer_cancel: active 15
|
||||
rtems_timer_cancel: inactive 13
|
||||
rtems_timer_reset: inactive 21
|
||||
rtems_timer_reset: active 23
|
||||
rtems_timer_fire_when: inactive 34
|
||||
rtems_timer_fire_when: active 34
|
||||
rtems_timer_delete: active 19
|
||||
rtems_timer_delete: inactive 17
|
||||
rtems_task_wake_when 69
|
||||
|
||||
24 rtems_task_wake_after: yield -- returns to caller 9
|
||||
rtems_task_wake_after: yields -- preempts caller 45
|
||||
|
||||
25 rtems_clock_tick 4
|
||||
|
||||
26 _ISR_Disable 0
|
||||
_ISR_Flash 1
|
||||
_ISR_Enable 1
|
||||
_Thread_Disable_dispatch 0
|
||||
_Thread_Enable_dispatch 7
|
||||
_Thread_Set_state 11
|
||||
_Thread_Disptach (NO FP) 31
|
||||
context switch: no floating point contexts 21
|
||||
context switch: self 10
|
||||
context switch: to another task 10
|
||||
context switch: restore 1st FP task 25
|
||||
fp context switch: save idle, restore idle 31
|
||||
fp context switch: save idle, restore initialized 19
|
||||
fp context switch: save initialized, restore initialized 20
|
||||
_Thread_Resume 7
|
||||
_Thread_Unblock 7
|
||||
_Thread_Ready 9
|
||||
_Thread_Get 4
|
||||
_Semaphore_Get 2
|
||||
_Thread_Get: invalid id 0
|
||||
|
||||
27 interrupt entry overhead: returns to interrupted task 6
|
||||
interrupt exit overhead: returns to interrupted task 6
|
||||
interrupt entry overhead: returns to nested interrupt 6
|
||||
interrupt exit overhead: returns to nested interrupt 5
|
||||
interrupt entry overhead: returns to preempting task 7
|
||||
interrupt exit overhead: returns to preempting task 36
|
||||
|
||||
28 rtems_port_create 16
|
||||
rtems_port_external_to_internal 11
|
||||
rtems_port_internal_to_external 11
|
||||
rtems_port_delete 16
|
||||
|
||||
29 rtems_rate_monotonic_create 15
|
||||
rtems_rate_monotonic_period: initiate period -- returns to caller 21
|
||||
rtems_rate_monotonic_period: obtain status 13
|
||||
rtems_rate_monotonic_cancel 16
|
||||
rtems_rate_monotonic_delete: inactive 18
|
||||
rtems_rate_monotonic_delete: active 20
|
||||
rtems_rate_monotonic_period: conclude periods -- caller blocks 53
|
||||
Reference in New Issue
Block a user