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adapted for modified exception code
This commit is contained in:
Thomas Doerfler
@@ -1,3 +1,24 @@
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2008-07-10 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* rtems/asm.h: Added defines for save and restore registers and
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special purpose registers 4 to 7.
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* rtems/new-exceptions/cpu.h: Changed define PPC_BSP_HAS_FIXED_PR288 to
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a value that results in a compile time error on usage since SPRG0 is
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now used for the interrupt disable mask.
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* rtems/powerpc/registers.h: Bugfix: Swapped values of TBWU and TBWL.
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Added defines SPRG4..7 and USPRG0.
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Changed _CPU_ISR_{Disable, Enable, Flush} to use static inline
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functions. The interrupt disable mask is now stored in SPRG0. Which
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was previously denoted to indicate a PR288 bugfix. You may now
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initialize the interrupt disable mask via
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ppc_interrupt_set_disable_mask() and
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PPC_INTERRUPT_DISABLE_MASK_DEFAULT. The default value will be set in
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bootcard.c.
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2008-02-20 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/old-exceptions/cpu.h: Remove (Abandoned).
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@@ -157,15 +157,25 @@
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*/
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#define srr0 0x01a
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#define srr1 0x01b
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#if defined(ppc403) || defined(ppc405)
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#define srr2 0x3de /* IBM 400 series only */
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#define srr3 0x3df /* IBM 400 series only */
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#endif /* ppc403 or ppc405 */
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#define srr2 0x3de /* IBM 400 series only */
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#define srr3 0x3df /* IBM 400 series only */
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#define csrr0 58 /* Book E */
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#define csrr1 59 /* Book E */
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#define mcsrr0 570 /* e500 */
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#define mcsrr1 571 /* e500 */
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#define dsrr0 574 /* e200 */
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#define dsrr1 575 /* e200 */
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#define sprg0 0x110
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#define sprg1 0x111
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#define sprg2 0x112
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#define sprg3 0x113
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#define sprg4 276
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#define sprg5 277
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#define sprg6 278
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#define sprg7 279
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#define usprg0 256
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#define dar 0x013 /* Data Address Register */
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#define dec 0x016 /* Decrementer Register */
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@@ -311,15 +311,11 @@ void _BSP_Fatal_error(unsigned int);
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/* end of Fatal Error manager macros */
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/*
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* Until all new-exception processing BSPs have fixed
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* PR288, we let the good BSPs pass
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*
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* PPC_BSP_HAS_FIXED_PR288
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*
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* in SPRG0 and let _CPU_Initialize assert this.
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* SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
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* Now SPRG0 is devoted to the interrupt disable mask.
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*/
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#define PPC_BSP_HAS_FIXED_PR288 0x600dbabe
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#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
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#endif /* ASM */
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@@ -18,10 +18,6 @@
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#ifndef _RTEMS_POWERPC_REGISTERS_H
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#define _RTEMS_POWERPC_REGISTERS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Bit encodings for Machine State Register (MSR) */
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#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */
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#define MSR_POW (1<<18) /* Enable Power Management */
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@@ -37,6 +33,7 @@ extern "C" {
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#define MSR_BE (1<<9) /* Branch Trace */
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#define MSR_DE (1<<9) /* BookE debug exception */
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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#define MSR_E300_CE (1<<7) /* e300 critical interrupt */
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR (1<<5) /* Instruction MMU enable */
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#define MSR_DR (1<<4) /* Data MMU enable */
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@@ -120,8 +117,8 @@ n:
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#define TBRU 269 /* Time base Upper/Lower (Reading) */
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#define TBRL 268
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#define TBWU 284 /* Time base Upper/Lower (Writing) */
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#define TBWL 285
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#define TBWU 285 /* Time base Upper/Lower (Writing) */
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#define TBWL 284
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#define XER 1
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#define LR 8
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#define CTR 9
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@@ -184,6 +181,11 @@ n:
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#define SPRG2 274
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#define SPR3 275
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#define SPRG3 275
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#define SPRG4 276
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#define SPRG5 277
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#define SPRG6 278
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#define SPRG7 279
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#define USPRG0 256
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#define DSISR 18
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#define SRR0 26 /* Saved Registers (exception) */
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#define SRR1 27
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@@ -307,6 +309,22 @@ lidate */
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#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17)
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#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13)
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/**
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* @brief Default value for the interrupt disable mask.
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*
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* The interrupt disable mask is stored in the SPRG0 (= special purpose
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* register 272).
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*/
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#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
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#ifndef ASM
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define _CPU_MSR_GET( _msr_value ) \
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do { \
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_msr_value = 0; \
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@@ -316,16 +334,57 @@ lidate */
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#define _CPU_MSR_SET( _msr_value ) \
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{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
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#define _CPU_ISR_Disable( _isr_cookie ) \
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{ register unsigned int _disable_mask = MSR_EE; \
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_isr_cookie = 0; \
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asm volatile ( \
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"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
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"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
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"0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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static inline void ppc_interrupt_set_disable_mask( uint32_t mask)
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{
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asm volatile (
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"mtspr 272, %0"
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:
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: "r" (mask)
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);
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}
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static inline uint32_t ppc_interrupt_disable()
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{
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uint32_t level;
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uint32_t mask;
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asm volatile (
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"mfmsr %0;"
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"mfspr %1, 272;"
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"andc %1, %0, %1;"
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"mtmsr %1"
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: "=r" (level), "=r" (mask)
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);
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return level;
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}
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static inline void ppc_interrupt_enable( uint32_t level)
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{
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asm volatile (
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"mtmsr %0"
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:
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: "r" (level)
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);
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}
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static inline void ppc_interrupt_flash( uint32_t level)
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{
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uint32_t current_level;
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asm volatile (
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"mfmsr %0;"
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"mtmsr %1;"
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"mtmsr %0"
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: "=&r" (current_level)
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: "r" (level)
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);
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}
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#define _CPU_ISR_Disable( _isr_cookie ) \
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do { \
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_isr_cookie = ppc_interrupt_disable(); \
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} while (0)
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/*
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* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
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@@ -334,11 +393,7 @@ lidate */
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*/
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#define _CPU_ISR_Enable( _isr_cookie ) \
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{ \
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asm volatile ( "mtmsr %0" : \
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"=r" ((_isr_cookie)) : \
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"0" ((_isr_cookie))); \
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}
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ppc_interrupt_enable( _isr_cookie)
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/*
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* This temporarily restores the interrupt to _isr_cookie before immediately
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@@ -352,19 +407,14 @@ lidate */
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*/
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#define _CPU_ISR_Flash( _isr_cookie ) \
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{ register unsigned int _disable_mask = MSR_EE; \
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asm volatile ( \
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"mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
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"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
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"0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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ppc_interrupt_flash( _isr_cookie)
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/* end of ISR handler macros */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __cplusplus */
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#endif /* ASM */
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#endif /* _RTEMS_POWERPC_REGISTERS_H */
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