mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-22 13:31:41 +08:00
New (Submission by Bruce Robinson <brucer@pmccorp.com>).
This commit is contained in:
Ralf Corsepius
@@ -0,0 +1,14 @@
|
||||
aclocal.m4
|
||||
autom4te*.cache
|
||||
config.cache
|
||||
config.guess
|
||||
config.log
|
||||
config.status
|
||||
config.sub
|
||||
configure
|
||||
depcomp
|
||||
install-sh
|
||||
Makefile
|
||||
Makefile.in
|
||||
missing
|
||||
mkinstalldirs
|
||||
@@ -0,0 +1,13 @@
|
||||
2006-03-16 Ralf Corsépius <ralf.corsepius@rtems.org>
|
||||
|
||||
* liblnk/pmon.S, liblnk/regs.S, liblnk/lnklib.S, README,
|
||||
bsp_specs, configure.ac, startup/inittlb.c, startup/bspstart.c,
|
||||
startup/setvec.c, startup/ghlinkcmds, startup/idtmem.S,
|
||||
startup/exception.S, startup/bspclean.c, startup/idttlb.S,
|
||||
startup/linkcmds, include/usc.h, include/tm27.h, include/bsp.h,
|
||||
include/coverhd.h, clock/clock.h, clock/clock.S, clock/ckinit.c,
|
||||
Makefile.am, start/start.S, console/console.c, times:
|
||||
New (Submission by Bruce Robinson <brucer@pmccorp.com>).
|
||||
|
||||
* The HURRICANE BSP is for a Quick Logic Hurricane evaluation board.
|
||||
This board has a PMC-Sierra RM5230 or RM5231 MIPS Processor.
|
||||
@@ -0,0 +1,116 @@
|
||||
##
|
||||
## $Id$
|
||||
##
|
||||
|
||||
ACLOCAL_AMFLAGS = -I ../../../../aclocal
|
||||
|
||||
include $(top_srcdir)/../../../../automake/compile.am
|
||||
include $(top_srcdir)/../../bsp.am
|
||||
|
||||
dist_project_lib_DATA = bsp_specs
|
||||
|
||||
include_HEADERS = include/bsp.h
|
||||
include_HEADERS += include/tm27.h
|
||||
include_HEADERS += include/usc.h
|
||||
|
||||
nodist_include_HEADERS = include/bspopts.h
|
||||
DISTCLEANFILES = include/bspopts.h
|
||||
|
||||
noinst_PROGRAMS =
|
||||
|
||||
nodist_include_HEADERS += ../../shared/include/coverhd.h
|
||||
|
||||
EXTRA_DIST = start/start.S start/regs.S
|
||||
start.$(OBJEXT): start/start.S
|
||||
$(CPPASCOMPILE) -DASM -o $@ -c $<
|
||||
|
||||
project_lib_DATA = start.$(OBJEXT)
|
||||
|
||||
dist_project_lib_DATA += startup/linkcmds
|
||||
|
||||
noinst_PROGRAMS += startup.rel
|
||||
startup_rel_SOURCES = ../../shared/bspclean.c \
|
||||
../../shared/bsplibc.c ../../shared/bsppost.c startup/bspstart.c \
|
||||
../../shared/bootcard.c ../../shared/main.c ../../shared/sbrk.c \
|
||||
../../shared/gnatinstallhandler.c ../../shared/setvec.c \
|
||||
startup/inittlb.c \
|
||||
startup/idtmem.S startup/idttlb.S startup/exception.S
|
||||
startup_rel_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
noinst_PROGRAMS += clock.rel
|
||||
clock_rel_SOURCES = clock/ckinit.c
|
||||
clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
noinst_PROGRAMS += console.rel
|
||||
console_rel_SOURCES = console/console.c
|
||||
console_rel_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
noinst_PROGRAMS += liblnk.rel
|
||||
liblnk_rel_SOURCES = liblnk/lnklib.S liblnk/pmon.S
|
||||
liblnk_rel_CPPFLAGS = $(AM_CPPFLAGS)
|
||||
liblnk_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
|
||||
|
||||
noinst_LIBRARIES = libbsp.a
|
||||
libbsp_a_SOURCES =
|
||||
libbsp_a_LIBADD = startup.rel clock.rel console.rel liblnk.rel
|
||||
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
|
||||
../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel \
|
||||
../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel \
|
||||
../../../libcpu/@RTEMS_CPU@/rm52xx/vectorisrs.rel
|
||||
|
||||
all-local: $(PREINSTALL_FILES) $(TMPINSTALL_FILES)
|
||||
|
||||
PREINSTALL_DIRS =
|
||||
PREINSTALL_FILES =
|
||||
TMPINSTALL_FILES =
|
||||
|
||||
$(PROJECT_INCLUDE)/$(dirstamp):
|
||||
@$(mkdir_p) $(PROJECT_INCLUDE)
|
||||
@: > $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
|
||||
$(PROJECT_LIB)/$(dirstamp):
|
||||
@$(mkdir_p) $(PROJECT_LIB)
|
||||
@: > $(PROJECT_LIB)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
|
||||
|
||||
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
|
||||
|
||||
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
|
||||
|
||||
$(PROJECT_INCLUDE)/usc.h: include/usc.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/usc.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/usc.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
|
||||
|
||||
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
|
||||
|
||||
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
|
||||
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
|
||||
|
||||
CLEANFILES = $(PREINSTALL_FILES)
|
||||
DISTCLEANFILES += $(PREINSTALL_DIRS)
|
||||
CLEANFILES += $(TMPINSTALL_FILES)
|
||||
|
||||
include $(top_srcdir)/../../../../automake/local.am
|
||||
@@ -0,0 +1,46 @@
|
||||
#
|
||||
# README,v 1.2 1998/01/16 16:56:31 joel Exp
|
||||
#
|
||||
# @(#)README 08/20/96 1.2
|
||||
#
|
||||
|
||||
BSP NAME: hurricane
|
||||
BOARD: Quick Logic Hurricane SBC with V320USC
|
||||
BUS: N/A
|
||||
CPU FAMILY: mips
|
||||
CPU: PMC-Sierra RM5231
|
||||
COPROCESSORS: N/A
|
||||
MODE: 32 bit mode
|
||||
|
||||
DEBUG MONITOR: PMON
|
||||
|
||||
PERIPHERALS
|
||||
===========
|
||||
TIMERS: V320USC internal
|
||||
SERIAL PORTS: PMON controlled
|
||||
REAL-TIME CLOCK: none
|
||||
DMA: none
|
||||
VIDEO: none
|
||||
SCSI: none
|
||||
NETWORKING: none
|
||||
|
||||
DRIVER INFORMATION
|
||||
==================
|
||||
CLOCK DRIVER: V320USC internal
|
||||
IOSUPP DRIVER: N/A
|
||||
SHMSUPP: N/A
|
||||
TIMER DRIVER: V320USC internal
|
||||
TTY DRIVER: uses PMON
|
||||
|
||||
STDIO
|
||||
=====
|
||||
PORT: Console port 0
|
||||
ELECTRICAL: RS-232
|
||||
BAUD: 9600
|
||||
BITS PER CHARACTER: 8
|
||||
PARITY: None
|
||||
STOP BITS: 1
|
||||
|
||||
NOTES
|
||||
=====
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
%rename lib old_lib
|
||||
%rename endfile old_endfile
|
||||
%rename startfile old_startfile
|
||||
%rename link old_link
|
||||
|
||||
*lib:
|
||||
%{!qrtems: %(old_lib)} %{!nostdlib: %{qrtems: --start-group \
|
||||
%{!qrtems_debug: -lrtemsbsp -lrtemscpu} %{qrtems_debug: -lrtemsbsp_g -lrtemscpu_g} \
|
||||
-lc -lgcc --end-group \
|
||||
%{!qnolinkcmds: -T linkcmds%s}}}
|
||||
|
||||
*startfile:
|
||||
%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: \
|
||||
%{!qrtems_debug: start.o%s} \
|
||||
%{qrtems_debug: start_g.o%s} crti.o%s crtbegin.o%s }}
|
||||
|
||||
*link:
|
||||
%{!qrtems: %(old_link)} %{qrtems: --oformat=elf32-littlemips -dc -dp -N -e start}
|
||||
|
||||
*endfile:
|
||||
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s }
|
||||
|
||||
@@ -0,0 +1,262 @@
|
||||
|
||||
/* ckinit.c
|
||||
*
|
||||
* This file contains the clock driver initialization for the Hurricane BSP.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
|
||||
* static char _sccsid[] = "@(#)ckinit.c 08/20/96 1.3\n";
|
||||
*/
|
||||
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/libio.h>
|
||||
|
||||
#define EXT_INT1 0x800 /* external interrupt 5 */
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
/* formerly in the BSP */
|
||||
#if 0
|
||||
#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
|
||||
#endif
|
||||
|
||||
#define CLOCKS_PER_MICROSECOND \
|
||||
rtems_cpu_configuration_get_clicks_per_microsecond()
|
||||
/* to avoid including the bsp */
|
||||
mips_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int );
|
||||
|
||||
void USC_isr( void );
|
||||
void reset_wdt(void);
|
||||
void enable_wdi(void);
|
||||
void init_hbt(void);
|
||||
void enable_hbi(void);
|
||||
void disable_hbi(void);
|
||||
|
||||
void Clock_exit( void );
|
||||
rtems_isr Clock_isr( rtems_vector_number vector );
|
||||
|
||||
|
||||
/*
|
||||
* The interrupt vector number associated with the clock tick device
|
||||
* driver.
|
||||
*/
|
||||
|
||||
#define CLOCK_VECTOR_MASK EXT_INT1
|
||||
#define CLOCK_VECTOR MIPS_INTERRUPT_BASE + 0x3
|
||||
|
||||
/*
|
||||
* Clock_driver_ticks is a monotonically increasing counter of the
|
||||
* number of clock ticks since the driver was initialized.
|
||||
*/
|
||||
|
||||
volatile uint32_t Clock_driver_ticks;
|
||||
|
||||
/*
|
||||
* Clock_isrs is the number of clock ISRs until the next invocation of
|
||||
* the RTEMS clock tick routine. The clock tick device driver
|
||||
* gets an interrupt once a millisecond and counts down until the
|
||||
* length of time between the user configured microseconds per tick
|
||||
* has passed.
|
||||
*/
|
||||
|
||||
uint32_t Clock_isrs; /* ISRs until next tick */
|
||||
|
||||
/*
|
||||
* These are set by clock driver during its init
|
||||
*/
|
||||
|
||||
rtems_device_major_number rtems_clock_major = ~0;
|
||||
rtems_device_minor_number rtems_clock_minor;
|
||||
|
||||
/*
|
||||
* The previous ISR on this clock tick interrupt vector.
|
||||
*/
|
||||
|
||||
rtems_isr_entry Old_ticker;
|
||||
|
||||
void Clock_exit( void );
|
||||
|
||||
static uint32_t mips_timer_rate = 0;
|
||||
|
||||
/*
|
||||
* Isr Handler
|
||||
*/
|
||||
|
||||
rtems_isr Clock_isr(
|
||||
rtems_vector_number vector
|
||||
)
|
||||
{
|
||||
/*
|
||||
* bump the number of clock driver ticks since initialization
|
||||
*
|
||||
* determine if it is time to announce the passing of tick as configured
|
||||
* to RTEMS through the rtems_clock_tick directive
|
||||
*
|
||||
* perform any timer dependent tasks
|
||||
*/
|
||||
|
||||
reset_wdt(); /* Reset hardware watchdog timer */
|
||||
|
||||
Clock_driver_ticks += 1;
|
||||
|
||||
rtems_clock_tick();
|
||||
}
|
||||
|
||||
/* User callback shell (set from Clock_Control) */
|
||||
static void (*user_callback)(void);
|
||||
|
||||
rtems_isr User_Clock_isr(
|
||||
rtems_vector_number vector
|
||||
)
|
||||
{
|
||||
if (user_callback)
|
||||
user_callback();
|
||||
}
|
||||
|
||||
/*
|
||||
* Install_clock
|
||||
*
|
||||
* Install a clock tick handleR and reprograms the chip. This
|
||||
* is used to initially establish the clock tick.
|
||||
*/
|
||||
|
||||
void Install_clock(
|
||||
rtems_isr_entry clock_isr
|
||||
)
|
||||
{
|
||||
/*
|
||||
* Initialize the clock tick device driver variables
|
||||
*/
|
||||
|
||||
Clock_driver_ticks = 0;
|
||||
Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
|
||||
|
||||
mips_timer_rate =
|
||||
rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
|
||||
|
||||
/*
|
||||
* Hardware specific initialize goes here
|
||||
*/
|
||||
|
||||
/* Set up USC heartbeat timer to generate interrupts */
|
||||
disable_hbi(); /* Disable heartbeat interrupt in USC */
|
||||
|
||||
/* Install interrupt handler */
|
||||
Old_ticker = (rtems_isr_entry) set_vector( USC_isr, CLOCK_VECTOR, 1 );
|
||||
|
||||
init_hbt(); /* Initialize heartbeat timer */
|
||||
|
||||
reset_wdt(); /* Reset watchdog timer */
|
||||
|
||||
enable_wdi(); /* Enable watchdog interrupt in USC */
|
||||
|
||||
enable_hbi(); /* Enable heartbeat interrupt in USC */
|
||||
|
||||
/* Enable USC interrupt in MIPS processor */
|
||||
mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
|
||||
|
||||
/*
|
||||
* Schedule the clock cleanup routine to execute if the application exits.
|
||||
*/
|
||||
|
||||
atexit( Clock_exit );
|
||||
}
|
||||
|
||||
/*
|
||||
* Clean up before the application exits
|
||||
*/
|
||||
|
||||
void Clock_exit( void )
|
||||
{
|
||||
/* mips: turn off the timer interrupts */
|
||||
mips_disable_in_interrupt_mask(~CLOCK_VECTOR_MASK);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clock_initialize
|
||||
*
|
||||
* Device driver entry point for clock tick driver initialization.
|
||||
*/
|
||||
|
||||
rtems_device_driver Clock_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *pargp
|
||||
)
|
||||
{
|
||||
Install_clock( Clock_isr );
|
||||
|
||||
/*
|
||||
* make major/minor avail to others such as shared memory driver
|
||||
*/
|
||||
|
||||
rtems_clock_major = major;
|
||||
rtems_clock_minor = minor;
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
rtems_device_driver Clock_control(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *pargp
|
||||
)
|
||||
{
|
||||
uint32_t isrlevel;
|
||||
rtems_libio_ioctl_args_t *args = pargp;
|
||||
|
||||
if (args == 0)
|
||||
goto done;
|
||||
|
||||
/*
|
||||
* This is hokey, but until we get a defined interface
|
||||
* to do this, it will just be this simple...
|
||||
*/
|
||||
|
||||
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
|
||||
{
|
||||
Clock_isr(CLOCK_VECTOR);
|
||||
}
|
||||
else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
|
||||
{
|
||||
rtems_interrupt_disable( isrlevel );
|
||||
user_callback = (void (*)(void))args->buffer;
|
||||
(void) set_vector( User_Clock_isr, CLOCK_VECTOR, 1 );
|
||||
rtems_interrupt_enable( isrlevel );
|
||||
}
|
||||
|
||||
done:
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -0,0 +1,45 @@
|
||||
/* clock.s
|
||||
*
|
||||
* This file contains the assembly code for the Hurricane BSP clock driver.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* clock.S,v 1.5 2001/05/24 13:23:48 joel Exp
|
||||
*/
|
||||
/* @(#)clock.S 08/20/96 1.2 */
|
||||
|
||||
#include <iregdef.h>
|
||||
#include <idtcpu.h>
|
||||
#include <asm.h>
|
||||
|
||||
FRAME(mips_set_timer,sp,0,ra)
|
||||
.set noreorder
|
||||
mfc0 t0,C0_COUNT
|
||||
nop
|
||||
addu t0,a0,t0
|
||||
mtc0 t0,C0_COMPARE
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
ENDFRAME(mips_set_timer)
|
||||
|
||||
FRAME(mips_get_timer,sp,0,ra)
|
||||
.set noreorder
|
||||
mfc0 v0,C0_COUNT
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
ENDFRAME(mips_get_timer)
|
||||
@@ -0,0 +1,25 @@
|
||||
/* clock.s
|
||||
*
|
||||
* This file contains the assembly code for the Hurricane BSP clock driver.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* clock.h,v 1.2 1996/09/11 19:14:52 joel Exp
|
||||
*/
|
||||
|
||||
/* @(#)clock.h 08/20/96 1.2 */
|
||||
|
||||
extern void mips_set_timer( uint32_t timer_clock_interval );
|
||||
@@ -0,0 +1,21 @@
|
||||
## Process this file with autoconf to produce a configure script.
|
||||
##
|
||||
## configure.ac,v 1.5.2.2 2003/08/11 14:37:57 ralf Exp
|
||||
|
||||
AC_PREREQ(2.59)
|
||||
AC_INIT([rtems-c-src-lib-libbsp-mips-hurricane],[_RTEMS_VERSION],[rtems-bugs@rtems.com])
|
||||
AC_CONFIG_SRCDIR([bsp_specs])
|
||||
RTEMS_TOP(../../../../../..)
|
||||
|
||||
RTEMS_CANONICAL_TARGET_CPU
|
||||
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9])
|
||||
|
||||
RTEMS_BSP_CONFIGURE
|
||||
|
||||
RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
|
||||
RTEMS_CANONICALIZE_TOOLS
|
||||
RTEMS_PROG_CCAS
|
||||
|
||||
# Explicitly list all Makefiles here
|
||||
AC_CONFIG_FILES([Makefile])
|
||||
AC_OUTPUT
|
||||
@@ -0,0 +1,270 @@
|
||||
/*
|
||||
* This file contains the IDT 4650 console IO package.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* console.c,v 1.10.4.1 2003/09/04 18:44:52 joel Exp
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
|
||||
* static char _sccsid[] = "@(#)console.c 08/20/96 1.6\n";
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include <bsp.h>
|
||||
#include <rtems/libio.h>
|
||||
#include <ctype.h>
|
||||
|
||||
/* PMON entry points */
|
||||
int mon_read(int fd, char *buf, int cnt); /* stdin is fd=0 */
|
||||
int mon_write(int fd, char *buf, int cnt); /* stdout is fd=1 */
|
||||
|
||||
/* console_initialize
|
||||
*
|
||||
* This routine initializes the console IO driver.
|
||||
*
|
||||
* Input parameters: NONE
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* Return values:
|
||||
*/
|
||||
|
||||
rtems_device_driver console_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *arg
|
||||
)
|
||||
{
|
||||
rtems_status_code status;
|
||||
|
||||
status = rtems_io_register_name(
|
||||
"/dev/console",
|
||||
major,
|
||||
(rtems_device_minor_number) 0
|
||||
);
|
||||
|
||||
if (status != RTEMS_SUCCESSFUL)
|
||||
rtems_fatal_error_occurred(status);
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
|
||||
/* is_character_ready
|
||||
*
|
||||
* This routine returns TRUE if a character is available.
|
||||
*
|
||||
* Input parameters: NONE
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* Return values:
|
||||
*/
|
||||
|
||||
rtems_boolean is_character_ready(
|
||||
char *ch
|
||||
)
|
||||
{
|
||||
*ch = '\0'; /* return NULL for no particular reason */
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
/* inbyte
|
||||
*
|
||||
* This routine reads a character from the SOURCE.
|
||||
*
|
||||
* Input parameters: NONE
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
* Return values:
|
||||
* character read from SOURCE
|
||||
*/
|
||||
|
||||
char inbyte( void )
|
||||
{
|
||||
char buf[10];
|
||||
/*
|
||||
* If polling, wait until a character is available.
|
||||
*/
|
||||
|
||||
mon_read(0, buf, 1); /* stdin is fd=0, read 1 byte */
|
||||
|
||||
return (buf[0]);
|
||||
}
|
||||
|
||||
/* outbyte
|
||||
*
|
||||
* This routine transmits a character out the SOURCE. It may support
|
||||
* XON/XOFF flow control.
|
||||
*
|
||||
* Input parameters:
|
||||
* ch - character to be transmitted
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*/
|
||||
|
||||
void outbyte(
|
||||
char ch
|
||||
)
|
||||
{
|
||||
char buf[10];
|
||||
/*
|
||||
* If polling, wait for the transmitter to be ready.
|
||||
* Check for flow control requests and process.
|
||||
* Then output the character.
|
||||
*/
|
||||
buf[0] = ch;
|
||||
|
||||
mon_write( 1, buf, 1 ); /* stdout is fd=1, write 1 byte */
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
static int console_fd = -1;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Open entry point
|
||||
*/
|
||||
|
||||
rtems_device_driver console_open(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
int console_fd = open("tty0", 2); /* open for read/write */
|
||||
#endif
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Close entry point
|
||||
*/
|
||||
|
||||
rtems_device_driver console_close(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
if ( console_fd )
|
||||
close( console_fd );
|
||||
#endif
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/*
|
||||
* read bytes from the serial port. We only have stdin.
|
||||
*/
|
||||
|
||||
rtems_device_driver console_read(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
rtems_libio_rw_args_t *rw_args;
|
||||
char *buffer;
|
||||
int maximum;
|
||||
int count = 0;
|
||||
|
||||
rw_args = (rtems_libio_rw_args_t *) arg;
|
||||
|
||||
buffer = rw_args->buffer;
|
||||
maximum = rw_args->count;
|
||||
|
||||
for (count = 0; count < maximum; count++) {
|
||||
buffer[ count ] = inbyte();
|
||||
if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
|
||||
buffer[ count++ ] = '\n';
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
rw_args->bytes_moved = count;
|
||||
return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
|
||||
}
|
||||
|
||||
/*
|
||||
* write bytes to the serial port. Stdout and stderr are the same.
|
||||
*/
|
||||
|
||||
rtems_device_driver console_write(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
int count;
|
||||
int maximum;
|
||||
rtems_libio_rw_args_t *rw_args;
|
||||
char *buffer;
|
||||
|
||||
rw_args = (rtems_libio_rw_args_t *) arg;
|
||||
|
||||
buffer = rw_args->buffer;
|
||||
maximum = rw_args->count;
|
||||
|
||||
for (count = 0; count < maximum; count++) {
|
||||
if ( buffer[ count ] == '\n') {
|
||||
outbyte('\r');
|
||||
}
|
||||
outbyte( buffer[ count ] );
|
||||
}
|
||||
|
||||
rw_args->bytes_moved = maximum;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* IO Control entry point
|
||||
*/
|
||||
|
||||
rtems_device_driver console_control(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void * arg
|
||||
)
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
#include <rtems/bspIo.h>
|
||||
|
||||
void hurricane_output_char(char c) { outbyte( c ); }
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = hurricane_output_char;
|
||||
BSP_polling_getchar_function_type BSP_poll_char = NULL;
|
||||
|
||||
@@ -0,0 +1,129 @@
|
||||
/* bsp.h
|
||||
*
|
||||
* This include file contains all board IO definitions.
|
||||
*
|
||||
* XXX : put yours in here
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* bsp.h,v 1.12.4.1 2003/09/04 18:44:52 joel Exp
|
||||
*/
|
||||
/* @(#)bsp.h 03/15/96 1.1 */
|
||||
|
||||
#ifndef __HURRICANE_BSP_h
|
||||
#define __HURRICANE_BSP_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/iosupp.h>
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/clockdrv.h>
|
||||
#include <libcpu/rm5231.h>
|
||||
|
||||
/*
|
||||
* confdefs.h overrides for this BSP:
|
||||
* - number of termios serial ports (defaults to 1)
|
||||
* - Interrupt stack space is not minimum if defined.
|
||||
*/
|
||||
|
||||
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
|
||||
#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
|
||||
|
||||
extern void WriteDisplay( char * string );
|
||||
|
||||
/*
|
||||
* Define the time limits for RTEMS Test Suite test durations.
|
||||
* Long test and short test duration limits are provided. These
|
||||
* values are in seconds and need to be converted to ticks for the
|
||||
* application.
|
||||
*
|
||||
*/
|
||||
|
||||
#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */
|
||||
#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */
|
||||
|
||||
/*
|
||||
* Stuff for Time Test 27
|
||||
*/
|
||||
|
||||
#define MUST_WAIT_FOR_INTERRUPT 0
|
||||
|
||||
#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
|
||||
|
||||
#define Cause_tm27_intr()
|
||||
|
||||
#define Clear_tm27_intr()
|
||||
|
||||
#define Lower_tm27_intr()
|
||||
|
||||
extern uint32_t mips_get_timer( void );
|
||||
|
||||
#define CPU_CLOCK_RATE_MHZ (200)
|
||||
#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
|
||||
|
||||
/*
|
||||
* Simple spin delay in microsecond units for device drivers.
|
||||
* This is very dependent on the clock speed of the target.
|
||||
*
|
||||
* NOTE: This macro generates a warning like "integer constant out
|
||||
* of range" which is safe to ignore. In 64 bit mode, unsigned32
|
||||
* types are actually 64 bits long so that comparisons between
|
||||
* unsigned32 types and pointers are valid. The warning is caused
|
||||
* by code in the delay macro that is necessary for 64 bit mode.
|
||||
*/
|
||||
|
||||
#define rtems_bsp_delay( microseconds ) \
|
||||
{ \
|
||||
unsigned32 _end_clock = \
|
||||
mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \
|
||||
_end_clock %= 0x100000000; /* make sure result is 32 bits */ \
|
||||
\
|
||||
/* handle timer overflow, if necessary */ \
|
||||
while ( _end_clock < mips_get_timer() ); \
|
||||
\
|
||||
while ( _end_clock > mips_get_timer() ); \
|
||||
}
|
||||
|
||||
/* Constants */
|
||||
|
||||
#define RAM_START 0
|
||||
#define RAM_END 0x100000
|
||||
|
||||
/* miscellaneous stuff assumed to exist */
|
||||
|
||||
extern rtems_configuration_table BSP_Configuration;
|
||||
|
||||
/*
|
||||
* Device Driver Table Entries
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: Use the standard Console driver entry
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: Use the standard Clock driver entry
|
||||
*/
|
||||
|
||||
/* miscellaneous stuff assumed to exist */
|
||||
|
||||
rtems_isr_entry set_vector(
|
||||
rtems_isr_entry, rtems_vector_number, int );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HURRICANE_BSP_h */
|
||||
|
||||
/* end of include file */
|
||||
@@ -0,0 +1,115 @@
|
||||
/* coverhd.h
|
||||
*
|
||||
* This include file has defines to represent the overhead associated
|
||||
* with calling a particular directive from C. These are used in the
|
||||
* Timing Test Suite to ignore the overhead required to pass arguments
|
||||
* to directives. On some CPUs and/or target boards, this overhead
|
||||
* is significant and makes it difficult to distinguish internal
|
||||
* RTEMS execution time from that used to call the directive.
|
||||
* This file should be updated after running the C overhead timing
|
||||
* test. Once this update has been performed, the RTEMS Time Test
|
||||
* Suite should be rebuilt to account for these overhead times in the
|
||||
* timing results.
|
||||
*
|
||||
* NOTE: If these are all zero, then the times reported include
|
||||
* all calling overhead including passing of arguments.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* coverhd.h,v 1.7.6.1 2003/09/04 18:44:52 joel Exp
|
||||
*/
|
||||
/* @(#)coverhd.h 04/08/96 1.3 */
|
||||
|
||||
#ifndef __COVERHD_h
|
||||
#define __COVERHD_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 5
|
||||
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4
|
||||
#define CALLING_OVERHEAD_TASK_CREATE 6
|
||||
#define CALLING_OVERHEAD_TASK_IDENT 4
|
||||
#define CALLING_OVERHEAD_TASK_START 5
|
||||
#define CALLING_OVERHEAD_TASK_RESTART 4
|
||||
#define CALLING_OVERHEAD_TASK_DELETE 4
|
||||
#define CALLING_OVERHEAD_TASK_SUSPEND 4
|
||||
#define CALLING_OVERHEAD_TASK_RESUME 4
|
||||
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5
|
||||
#define CALLING_OVERHEAD_TASK_MODE 4
|
||||
#define CALLING_OVERHEAD_TASK_GET_NOTE 5
|
||||
#define CALLING_OVERHEAD_TASK_SET_NOTE 5
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 9
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4
|
||||
#define CALLING_OVERHEAD_INTERRUPT_CATCH 5
|
||||
#define CALLING_OVERHEAD_CLOCK_GET 9
|
||||
#define CALLING_OVERHEAD_CLOCK_SET 8
|
||||
#define CALLING_OVERHEAD_CLOCK_TICK 3
|
||||
|
||||
#define CALLING_OVERHEAD_TIMER_CREATE 4
|
||||
#define CALLING_OVERHEAD_TIMER_IDENT 4
|
||||
#define CALLING_OVERHEAD_TIMER_DELETE 4
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 10
|
||||
#define CALLING_OVERHEAD_TIMER_RESET 4
|
||||
#define CALLING_OVERHEAD_TIMER_CANCEL 4
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 5
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 4
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 4
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 4
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 5
|
||||
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 4
|
||||
|
||||
#define CALLING_OVERHEAD_EVENT_SEND 4
|
||||
#define CALLING_OVERHEAD_EVENT_RECEIVE 5
|
||||
#define CALLING_OVERHEAD_SIGNAL_CATCH 5
|
||||
#define CALLING_OVERHEAD_SIGNAL_SEND 4
|
||||
#define CALLING_OVERHEAD_PARTITION_CREATE 6
|
||||
#define CALLING_OVERHEAD_PARTITION_IDENT 4
|
||||
#define CALLING_OVERHEAD_PARTITION_DELETE 4
|
||||
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 4
|
||||
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 4
|
||||
#define CALLING_OVERHEAD_REGION_CREATE 6
|
||||
#define CALLING_OVERHEAD_REGION_IDENT 4
|
||||
#define CALLING_OVERHEAD_REGION_DELETE 4
|
||||
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 5
|
||||
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 4
|
||||
#define CALLING_OVERHEAD_PORT_CREATE 6
|
||||
#define CALLING_OVERHEAD_PORT_IDENT 4
|
||||
#define CALLING_OVERHEAD_PORT_DELETE 4
|
||||
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4
|
||||
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4
|
||||
|
||||
#define CALLING_OVERHEAD_IO_INITIALIZE 5
|
||||
#define CALLING_OVERHEAD_IO_OPEN 5
|
||||
#define CALLING_OVERHEAD_IO_CLOSE 5
|
||||
#define CALLING_OVERHEAD_IO_READ 5
|
||||
#define CALLING_OVERHEAD_IO_WRITE 5
|
||||
#define CALLING_OVERHEAD_IO_CONTROL 5
|
||||
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4
|
||||
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4
|
||||
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* tm27.h
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
/*
|
||||
* Define the interrupt mechanism for Time Test 27
|
||||
*/
|
||||
|
||||
#define MUST_WAIT_FOR_INTERRUPT 0
|
||||
|
||||
#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
|
||||
|
||||
#define Cause_tm27_intr() /* empty */
|
||||
|
||||
#define Clear_tm27_intr() /* empty */
|
||||
|
||||
#define Lower_tm27_intr() /* empty */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/* USC constants */
|
||||
|
||||
#ifndef _USC_H__
|
||||
#define _USC_H__
|
||||
|
||||
|
||||
#define USC_REG_BASE (0x1D000000 | 0xA0000000)
|
||||
|
||||
/* Internal register addresses */
|
||||
#define SYSTEM (USC_REG_BASE + 0x73)
|
||||
|
||||
#define INT_CFG0 (USC_REG_BASE + 0xE0)
|
||||
#define INT_CFG1 (USC_REG_BASE + 0xE4)
|
||||
#define INT_CFG2 (USC_REG_BASE + 0xE8)
|
||||
#define INT_STAT (USC_REG_BASE + 0xEC)
|
||||
|
||||
#define WD_HBI (USC_REG_BASE + 0xF4)
|
||||
|
||||
#define INT_CFG3 (USC_REG_BASE + 0x158)
|
||||
|
||||
/* INT_CFGx register masks */
|
||||
#define HBI_MASK 0x00200000 /* Heartbeat timer interrupt mask */
|
||||
#define WDI_MASK 0x00400000 /* Watchdog timer interrupt mask */
|
||||
#define MODE_TOTEM_POLE 0x20000000 /* Totem Pole Output Mode */
|
||||
|
||||
/* WD_HBI register bits */
|
||||
#define WD_EN 0x00800000 /* Watchdog enable */
|
||||
#define HBI_4000_PS 0x00200000 /* Heartbeat timer prescaler = 4000 */
|
||||
#define WD_INIT 0x10 /* Watchdog reset pattern (written to byte 2 in WD_HBI register) */
|
||||
|
||||
|
||||
#endif /* _USC_H__ */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* lnklib.S,v 1.4 1999/03/31 23:21:19 joel Exp
|
||||
*/
|
||||
|
||||
#include <rtems/mips/iregdef.h>
|
||||
#include <rtems/mips/idtcpu.h>
|
||||
|
||||
#define FRAME(name,frm_reg,offset,ret_reg) \
|
||||
.globl name; \
|
||||
.ent name; \
|
||||
name:; \
|
||||
.frame frm_reg,offset,ret_reg
|
||||
|
||||
#define ENDFRAME(name) \
|
||||
.end name
|
||||
|
||||
#define PROM_LINK(name,entry) \
|
||||
.globl name; \
|
||||
.ent name; \
|
||||
name: la $2,+entry; \
|
||||
j $2; \
|
||||
.end name
|
||||
|
||||
#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
|
||||
|
||||
#define PROM_RESET PROM_ENTRY(0)
|
||||
#define PROM_NOT_IMP PROM_ENTRY(1)
|
||||
#define PROM_RESTART PROM_ENTRY(2)
|
||||
#define PROM_REINIT PROM_ENTRY(3)
|
||||
#define PROM_GETCHAR PROM_ENTRY(11)
|
||||
#define PROM_PUTCHAR PROM_ENTRY(12)
|
||||
#define PROM_SHOWCHAR PROM_ENTRY(13)
|
||||
#define PROM_PRINTF PROM_ENTRY(16)
|
||||
#define PROM_RETURN PROM_ENTRY(17)
|
||||
|
||||
#define PROM_RGETS PROM_ENTRY(25)
|
||||
#define PROM_FLUSHCACHE PROM_ENTRY(28)
|
||||
#define PROM_CLEARCACHE PROM_ENTRY(29)
|
||||
#define PROM_SETJMP PROM_ENTRY(30)
|
||||
#define PROM_LONGJMP PROM_ENTRY(31)
|
||||
|
||||
.text
|
||||
|
||||
PROM_LINK(idtsim_putchar, PROM_PUTCHAR)
|
||||
PROM_LINK(idtsim_getchar, PROM_GETCHAR)
|
||||
PROM_LINK(idtsim_showchar, PROM_SHOWCHAR)
|
||||
PROM_LINK(idtsim__exit, PROM_RETURN)
|
||||
PROM_LINK(idtsim_reinit, PROM_REINIT)
|
||||
PROM_LINK(idtsim_restart, PROM_RESTART)
|
||||
PROM_LINK(idtsim_reset, PROM_RESET)
|
||||
PROM_LINK(idtsim_promexit, PROM_RETURN)
|
||||
PROM_LINK(idtsim_setjmp, PROM_SETJMP)
|
||||
PROM_LINK(idtsim_longjmp, PROM_LONGJMP)
|
||||
|
||||
FRAME(idtsim_init_sbrk,sp,0,ra)
|
||||
j ra
|
||||
ENDFRAME(idtsim_init_sbrk)
|
||||
|
||||
FRAME(idtsim_init_file,sp,0,ra)
|
||||
j ra
|
||||
ENDFRAME(idtsim_init_file)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*
|
||||
* pmon.S -- low-level entry points into PMON monitor.
|
||||
*
|
||||
* Copyright (c) 1996, 1997 Cygnus Support
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
#ifdef __mips16
|
||||
/* This file contains 32 bit assembly code. */
|
||||
.set nomips16
|
||||
#endif
|
||||
|
||||
#if __mips < 3
|
||||
/* This machine does not support 64-bit operations. */
|
||||
#define ADDU addu
|
||||
#define SUBU subu
|
||||
#else
|
||||
/* This machine supports 64-bit operations. */
|
||||
#define ADDU daddu
|
||||
#define SUBU dsubu
|
||||
#endif
|
||||
|
||||
#include "regs.S"
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
#ifdef LSI
|
||||
#define PMON_VECTOR 0xbfc00200
|
||||
#else
|
||||
#define PMON_VECTOR 0xbfc00500
|
||||
#endif
|
||||
|
||||
#ifndef __mips_eabi
|
||||
/* Provide named functions for entry into the monitor: */
|
||||
#define INDIRECT(name,index) \
|
||||
.globl name; \
|
||||
.ent name; \
|
||||
.set noreorder; \
|
||||
name: la $2,+(PMON_VECTOR+((index)*4)); \
|
||||
lw $2,0($2); \
|
||||
j $2; \
|
||||
nop; \
|
||||
.set reorder; \
|
||||
.end name
|
||||
|
||||
#else
|
||||
#define INDIRECT(name,index) \
|
||||
.globl name; \
|
||||
.ent name; \
|
||||
.set noreorder; \
|
||||
name: la $2,+(PMON_VECTOR+((index)*4)); \
|
||||
lw $2,0($2); \
|
||||
SUBU sp,sp,0x40; \
|
||||
sd ra,0x38(sp); \
|
||||
sd fp,0x30(sp); \
|
||||
jal $2; \
|
||||
move fp,sp; \
|
||||
ld ra,0x38(sp); \
|
||||
ld fp,0x30(sp); \
|
||||
j ra; \
|
||||
ADDU sp,sp,0x40; \
|
||||
.set reorder; \
|
||||
.end name
|
||||
#endif
|
||||
|
||||
|
||||
/* The following magic numbers are for the slots into the PMON monitor */
|
||||
/* The first are used as the lo-level library run-time: */
|
||||
INDIRECT(mon_read,0)
|
||||
INDIRECT(mon_write,1)
|
||||
INDIRECT(mon_open,2)
|
||||
INDIRECT(mon_close,3)
|
||||
/* The following are useful monitor routines: */
|
||||
INDIRECT(mon_ioctl,4)
|
||||
INDIRECT(mon_printf,5)
|
||||
INDIRECT(mon_vsprintf,6)
|
||||
INDIRECT(mon_ttctl,7)
|
||||
INDIRECT(mon_cliexit,8)
|
||||
INDIRECT(mon_getenv,9)
|
||||
INDIRECT(mon_onintr,10)
|
||||
INDIRECT(mon_flush_cache,11)
|
||||
INDIRECT(mon_exception,12)
|
||||
INDIRECT(mon_fpgaconfig,21)
|
||||
|
||||
#if 0
|
||||
|
||||
/* The following routine is required by the "print()" function: */
|
||||
.globl pmon_outbyte
|
||||
.ent pmon_outbyte
|
||||
.set noreorder
|
||||
pmon_outbyte:
|
||||
subu sp,sp,0x20 /* allocate stack space for string */
|
||||
sd ra,0x18(sp) /* stack return address */
|
||||
sd fp,0x10(sp) /* stack frame-pointer */
|
||||
move fp,sp /* take a copy of the stack pointer */
|
||||
/* We leave so much space on the stack for the string (16
|
||||
characters), since the call to mon_printf seems to corrupt
|
||||
the 8bytes at offset 8 into the string/stack. */
|
||||
sb a0,0x00(sp) /* character to print */
|
||||
sb z0,0x01(sp) /* NUL terminator */
|
||||
jal mon_printf /* and output the string */
|
||||
move a0,sp /* take a copy of the string pointer {DELAY SLOT} */
|
||||
|
||||
move sp,fp /* recover stack pointer */
|
||||
ld ra,0x18(sp) /* recover return address */
|
||||
ld fp,0x10(sp) /* recover frame-pointer */
|
||||
j ra /* return to the caller */
|
||||
addu sp,sp,0x20 /* dump the stack space {DELAY SLOT} */
|
||||
.set reorder
|
||||
.end pmon_outbyte
|
||||
|
||||
/* The following routine is required by the "sbrk()" function: */
|
||||
.globl get_mem_info
|
||||
.ent get_mem_info
|
||||
.set noreorder
|
||||
get_mem_info:
|
||||
# in: a0 = pointer to 3 word structure
|
||||
# out: void
|
||||
subu sp,sp,0x18 /* create some stack space */
|
||||
sd ra,0x00(sp) /* stack return address */
|
||||
sd fp,0x08(sp) /* stack frame-pointer */
|
||||
sd a0,0x10(sp) /* stack structure pointer */
|
||||
move fp,sp /* take a copy of the stack pointer */
|
||||
|
||||
# The monitor has already sized memory, but unfortunately we
|
||||
# do not have access to the data location containing the
|
||||
# memory size.
|
||||
|
||||
jal __sizemem
|
||||
nop
|
||||
|
||||
ld a0,0x10(sp) # recover structure pointer
|
||||
sw v0,0(a0) # amount of memory available
|
||||
|
||||
# Deal with getting the cache size information:
|
||||
mfc0 a1, C0_CONFIG
|
||||
nop
|
||||
nop
|
||||
andi a2,a1,0x7 << 9 # bits 11..9 for instruction cache size
|
||||
sll a2,a2,12 - 8
|
||||
sw a2,4(a0)
|
||||
andi a2,a1,0x7 << 6 # bits 8..6 for data cache size
|
||||
sll a2,a2,12 - 5
|
||||
sw a2,8(a0) # data cache size
|
||||
#
|
||||
move sp,fp /* recover stack pointer */
|
||||
ld ra,0x00(sp) /* recover return address */
|
||||
ld fp,0x08(sp) /* recover frame-pointer */
|
||||
j ra /* return to the caller */
|
||||
addu sp,sp,0x18 /* restore stack pointer {DELAY SLOT} */
|
||||
.set reorder
|
||||
.end get_mem_info
|
||||
|
||||
#ifdef LSI
|
||||
|
||||
# For the LSI MiniRISC board, we can safely assume that we have
|
||||
# at least one megabyte of RAM.
|
||||
|
||||
.globl __sizemem
|
||||
.ent __sizemem
|
||||
__sizemem:
|
||||
li v0,0x100000
|
||||
j ra
|
||||
.end __sizemem
|
||||
#else
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* EOF pmon.S */
|
||||
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* regs.S -- standard MIPS register names.
|
||||
*
|
||||
* Copyright (c) 1995 Cygnus Support
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
/* Standard MIPS register names: */
|
||||
#define zero $0
|
||||
#define z0 $0
|
||||
#define v0 $2
|
||||
#define v1 $3
|
||||
#define a0 $4
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24
|
||||
#define t9 $25
|
||||
#define k0 $26 /* kernel private register 0 */
|
||||
#define k1 $27 /* kernel private register 1 */
|
||||
#define gp $28 /* global data pointer */
|
||||
#define sp $29 /* stack-pointer */
|
||||
#define fp $30 /* frame-pointer */
|
||||
#define ra $31 /* return address */
|
||||
#define pc $pc /* pc, used on mips16 */
|
||||
|
||||
#define fp0 $f0
|
||||
#define fp1 $f1
|
||||
|
||||
/* Useful memory constants: */
|
||||
#define K0BASE 0x80000000
|
||||
#ifndef __mips64
|
||||
#define K1BASE 0xA0000000
|
||||
#else
|
||||
#define K1BASE 0xFFFFFFFFA0000000LL
|
||||
#endif
|
||||
|
||||
#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
|
||||
|
||||
/* Standard Co-Processor 0 register numbers: */
|
||||
#define C0_COUNT $9 /* Count Register */
|
||||
#define C0_SR $12 /* Status Register */
|
||||
#define C0_CAUSE $13 /* last exception description */
|
||||
#define C0_EPC $14 /* Exception error address */
|
||||
#define C0_CONFIG $16 /* CPU configuration */
|
||||
|
||||
/* Standard Status Register bitmasks: */
|
||||
#define SR_CU1 0x20000000 /* Mark CP1 as usable */
|
||||
#define SR_FR 0x04000000 /* Enable MIPS III FP registers */
|
||||
#define SR_BEV 0x00400000 /* Controls location of exception vectors */
|
||||
#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */
|
||||
|
||||
#define SR_KX 0x00000080 /* Kernel extended addressing enabled */
|
||||
#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
|
||||
#define SR_UX 0x00000020 /* User extended addressing enabled */
|
||||
|
||||
/* Standard (R4000) cache operations. Taken from "MIPS R4000
|
||||
Microprocessor User's Manual" 2nd edition: */
|
||||
|
||||
#define CACHE_I (0) /* primary instruction */
|
||||
#define CACHE_D (1) /* primary data */
|
||||
#define CACHE_SI (2) /* secondary instruction */
|
||||
#define CACHE_SD (3) /* secondary data (or combined instruction/data) */
|
||||
|
||||
#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
|
||||
#define INDEX_LOAD_TAG (1)
|
||||
#define INDEX_STORE_TAG (2)
|
||||
#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */
|
||||
#define HIT_INVALIDATE (4)
|
||||
#define CACHE_FILL (5) /* CACHE_I only */
|
||||
#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */
|
||||
#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */
|
||||
#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */
|
||||
|
||||
#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
|
||||
|
||||
/* Individual cache operations: */
|
||||
#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
|
||||
#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
|
||||
#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
|
||||
#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
|
||||
|
||||
#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
|
||||
#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
|
||||
#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
|
||||
#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
|
||||
|
||||
#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
|
||||
#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
|
||||
#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
|
||||
#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
|
||||
|
||||
#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
|
||||
#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
|
||||
|
||||
#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
|
||||
#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
|
||||
#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
|
||||
#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
|
||||
|
||||
#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
|
||||
#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
|
||||
#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
|
||||
|
||||
#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
|
||||
#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
|
||||
#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
|
||||
|
||||
#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
|
||||
#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
|
||||
|
||||
/*> EOF regs.S <*/
|
||||
@@ -0,0 +1,342 @@
|
||||
/*
|
||||
|
||||
Based upon IDT provided code with the following release:
|
||||
|
||||
This source code has been made available to you by IDT on an AS-IS
|
||||
basis. Anyone receiving this source is licensed under IDT copyrights
|
||||
to use it in any way he or she deems fit, including copying it,
|
||||
modifying it, compiling it, and redistributing it either with or
|
||||
without modifications. No license under IDT patents or patent
|
||||
applications is to be implied by the copyright license.
|
||||
|
||||
Any user of this software should understand that IDT cannot provide
|
||||
technical support for this software and will not be responsible for
|
||||
any consequences resulting from the use of this software.
|
||||
|
||||
Any person who transfers this source code or any derivative work must
|
||||
include the IDT copyright notice, this paragraph, and the preceeding
|
||||
two paragraphs in the transferred software.
|
||||
|
||||
COPYRIGHT IDT CORPORATION 1996
|
||||
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
|
||||
|
||||
start.S,v 1.6 2001/09/28 23:14:23 joel Exp
|
||||
*/
|
||||
|
||||
/*************************************************************************
|
||||
**
|
||||
** Copyright 1991-95 Integrated Device Technology, Inc.
|
||||
** All Rights Reserved
|
||||
**
|
||||
** idt_csu.S -- IDT stand alone startup code
|
||||
**
|
||||
**************************************************************************/
|
||||
#include <rtems/mips/iregdef.h>
|
||||
#include <rtems/mips/idtcpu.h>
|
||||
#include <rtems/asm.h>
|
||||
|
||||
|
||||
#if 0
|
||||
.extern _fdata,4 /* this is defined by the linker */
|
||||
.extern _edata,4 /* this is defined by the linker */
|
||||
.extern _idata,4 /* this is defined by the linker */
|
||||
#endif
|
||||
.extern _fbss,4 /* this is defined by the linker */
|
||||
.extern end,4 /* this is defined by the linker */
|
||||
|
||||
.lcomm sim_mem_cfg_struct,12
|
||||
|
||||
.text
|
||||
|
||||
/* For the V3 Eval board, we can safely assume that we have
|
||||
at least 16 megabytes of RAM */
|
||||
#define HARD_CODED_MEM_SIZE 0x1000000
|
||||
|
||||
#define TMP_STKSIZE 1024
|
||||
|
||||
/*
|
||||
** P_STACKSIZE is the size of the Prom Stack.
|
||||
** the prom stack grows downward
|
||||
*/
|
||||
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
|
||||
|
||||
/**************************************************************************
|
||||
**
|
||||
** start - Typical standalone start up code required for R3000/R4000
|
||||
**
|
||||
**
|
||||
** 1) Initialize the STATUS Register
|
||||
** a) Clear parity error bit
|
||||
** b) Set co_processor 1 usable bit ON
|
||||
** c) Clear all IntMask Enables
|
||||
** d) Set kernel/disabled mode
|
||||
** 2) Initialize Cause Register
|
||||
** a) clear software interrupt bits
|
||||
** 3) Determine FPU installed or not
|
||||
** if not, clear CoProcessor 1 usable bit
|
||||
** 4) Clear bss area
|
||||
** 5) MUST allocate temporary stack until memory size determined
|
||||
** It MUST be uncached to prevent overwriting when caches are cleared
|
||||
** 6) Install exception handlers
|
||||
** 7) Determine memory and cache sizes
|
||||
** 8) Establish permanent stack (cached or uncached as defined by bss)
|
||||
** 9) Flush Instruction and Data caches
|
||||
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
|
||||
** 11) Execute initialization code if the IDT/c library is to be used
|
||||
**
|
||||
** 12) Jump to user's "main()" (boot_card() for RTEMS)
|
||||
** 13) Jump to promexit
|
||||
**
|
||||
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
|
||||
** This is used to mark code specific to R3xxx or R4xxx processors.
|
||||
** IDT/C 6.x defines __mips to be the ISA level for which we're
|
||||
** generating code. This is used to make sure the stack etc. is
|
||||
** double word aligned, when using -mips3 (default) or -mips2,
|
||||
** when compiling with IDT/C6.x
|
||||
**
|
||||
***************************************************************************/
|
||||
|
||||
FRAME(start,sp,0,ra)
|
||||
|
||||
.set noreorder
|
||||
#if __mips_fpr == 64
|
||||
li v0,SR_CU1|SR_FR|SR_DE /* initally clear ERL, enable FPU with 64 bit regs, disable cache errors */
|
||||
#else
|
||||
li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPU with 32 bit regs, disable cache errors */
|
||||
#endif
|
||||
|
||||
mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */
|
||||
nop
|
||||
mtc0 zero,C0_CAUSE /* clear software interrupts */
|
||||
nop
|
||||
|
||||
la t0,0xBE200000 /* on Hurricane board, enable interrupt output signal from UART ch. B */
|
||||
li t1,0x8 /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */
|
||||
sw t1,0x10(t0)
|
||||
|
||||
li v0,CFG_C_NONCOHERENT # initialise default cache mode
|
||||
mtc0 v0,C0_CONFIG
|
||||
|
||||
/*
|
||||
** check to see if an fpu is really plugged in
|
||||
*/
|
||||
li t3,0xaaaa5555 /* put a's and 5's in t3 */
|
||||
mtc1 t3,fp0 /* try to write them into fp0 */
|
||||
mtc1 zero,fp1 /* try to write zero in fp */
|
||||
mfc1 t0,fp0
|
||||
mfc1 t1,fp1
|
||||
nop
|
||||
bne t0,t3,1f /* branch if no match */
|
||||
nop
|
||||
bne t1,zero,1f /* double check for positive id */
|
||||
nop
|
||||
/* We have a FPU. clear fcsr */
|
||||
ctc1 zero, fcr31
|
||||
j 2f /* status register already correct */
|
||||
nop
|
||||
1:
|
||||
li v0,SR_DE /* clear ERL and disable FPA */
|
||||
|
||||
mtc0 v0, C0_SR /* reset status register */
|
||||
2:
|
||||
la gp, _gp
|
||||
|
||||
#if 0
|
||||
/* Initialize data sections from "rom" copy */
|
||||
la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */
|
||||
la t1,_fdata /* start of initialized data section */
|
||||
la t2,_edata /* end of initialized data section */
|
||||
3:
|
||||
lw t3,0(t0)
|
||||
sw t3,0(t1)
|
||||
addiu t1,t1,4
|
||||
bne t1,t2,3b
|
||||
addiu t0,t0,4
|
||||
#endif
|
||||
|
||||
/* clear bss before using it */
|
||||
la v0,_fbss /* start of bss */
|
||||
la v1,end /* end of bss */
|
||||
4: sw zero,0(v0)
|
||||
bltu v0,v1,4b
|
||||
add v0,4
|
||||
|
||||
|
||||
/************************************************************************
|
||||
**
|
||||
** Temporary Stack - needed to handle stack saves until
|
||||
** memory size is determined and permanent stack set
|
||||
**
|
||||
** MUST be uncached to avoid confusion at cache
|
||||
** switching during memory sizing
|
||||
**
|
||||
*************************************************************************/
|
||||
/* For MIPS 3, we need to be sure that the stack is aligned on a
|
||||
* double word boundary.
|
||||
*/
|
||||
andi t0, v0, 0x7
|
||||
beqz t0, 11f /* Last three bits Zero, already aligned */
|
||||
nop
|
||||
add v0, 4
|
||||
11:
|
||||
|
||||
or v0, K1BASE /* switch to uncached */
|
||||
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
|
||||
sub v1, v1, (4*4) /* overhead */
|
||||
move sp, v1 /* set sp to top of stack */
|
||||
4: sw zero, 0(v0)
|
||||
bltu v0, v1, 4b /* clear out temp stack */
|
||||
add v0, 4
|
||||
|
||||
/* jal init_exc_vecs */ /* install exception handlers */
|
||||
/* nop */ /* MUST do before memory probes */
|
||||
|
||||
/* Force processor into uncached space during memory/cache probes */
|
||||
la v0, 5f
|
||||
li v1, K1BASE
|
||||
or v0, v1
|
||||
j v0
|
||||
nop
|
||||
5:
|
||||
|
||||
li a0, HARD_CODED_MEM_SIZE /* Set memory size global */
|
||||
jal set_memory_size
|
||||
nop
|
||||
|
||||
la a0, sim_mem_cfg_struct
|
||||
jal get_mem_conf /* Make call to get mem size */
|
||||
nop
|
||||
la a0, sim_mem_cfg_struct
|
||||
lw a0, 0(a0) /* Get memory size from struct */
|
||||
|
||||
jal config_cache /* determine size of D & I caches */
|
||||
nop
|
||||
|
||||
move v0, a0 /* mem_size */
|
||||
|
||||
/* For MIPS 3, we need to be sure that the stack (and hence v0
|
||||
* here) is aligned on a double word boundary.
|
||||
*/
|
||||
andi t0, v0, 0x7
|
||||
beqz t0, 12f /* Last three bits Zero, already aligned */
|
||||
nop
|
||||
subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/
|
||||
12:
|
||||
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
**
|
||||
** Permanent Stack - now know top of memory, put permanent stack there
|
||||
**
|
||||
***************************************************************************/
|
||||
|
||||
la t2, _fbss /* cache mode as linked */
|
||||
and t2, 0xF0000000 /* isolate segment */
|
||||
la t1, 6f
|
||||
j t1 /* back to original cache mode */
|
||||
nop
|
||||
6:
|
||||
or v0, t2 /* stack back to original cache mode */
|
||||
addiu v0,v0,-16 /* overhead */
|
||||
move sp, v0 /* now replace count w top of memory */
|
||||
move v1, v0
|
||||
subu v1, P_STACKSIZE /* clear requested stack size */
|
||||
|
||||
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
|
||||
bltu v1,v0,7b
|
||||
add v1, 4
|
||||
.set reorder
|
||||
|
||||
/* FIX THIS - This corrupts memory spaces */
|
||||
/* jal flush_cache_nowrite */ /* flush Data & Instruction caches */
|
||||
|
||||
/* jal mon_flush_cache */
|
||||
|
||||
/**************************************************************************
|
||||
**
|
||||
** If this chip supports a Translation Lookaside Buffer, clear it
|
||||
**
|
||||
***************************************************************************/
|
||||
|
||||
.set noreorder
|
||||
mfc0 t1, C0_SR /* look at Status Register */
|
||||
nop
|
||||
.set reorder
|
||||
|
||||
jal init_tlb /* clear the tlb */
|
||||
|
||||
/* Force processor into cached instruction space for rest of initialization */
|
||||
#if 0
|
||||
la t0, 1f
|
||||
li t1, K0BASE /* force into cached space */
|
||||
or t0, t1
|
||||
j t0
|
||||
nop
|
||||
1:
|
||||
#endif
|
||||
|
||||
/************************************************************************
|
||||
**
|
||||
** Initialization required if using IDT/c or libc.a, standard C Lib
|
||||
**
|
||||
** can SKIP if not necessary for application
|
||||
**
|
||||
************************************************************************/
|
||||
8:
|
||||
|
||||
/* FIX THIS - Need the pmon equivalent
|
||||
jal idtsim_init_sbrk
|
||||
jal idtsim_init_file
|
||||
*/
|
||||
|
||||
/*********************** END I/O initialization **********************/
|
||||
|
||||
|
||||
move a0,zero /* Set argc passed to main */
|
||||
move a1,zero /* Set argv passed to main */
|
||||
jal boot_card
|
||||
nop
|
||||
|
||||
# jump to the "exit" routine
|
||||
jal _sys_exit
|
||||
move a0,v0 # pass through the exit code
|
||||
|
||||
|
||||
# FIX THIS - Need the pmon equivalent
|
||||
# jal idtsim_promexit
|
||||
|
||||
1:
|
||||
beq zero,zero,1b
|
||||
nop
|
||||
|
||||
ENDFRAME(start)
|
||||
|
||||
/*
|
||||
* _sys_exit -- Exit from the application. Normally we cause a user trap
|
||||
* to return to the ROM monitor for another run. NOTE: This is
|
||||
* the only other routine we provide in the crt0.o object, since
|
||||
* it may be tied to the "_start" routine. It also allows
|
||||
* executables that contain a complete world to be linked with
|
||||
* just the crt0.o object.
|
||||
*/
|
||||
FRAME(_sys_exit,sp,0,ra)
|
||||
|
||||
break 1023
|
||||
nop
|
||||
13:
|
||||
b 13b # but loop back just in-case
|
||||
nop
|
||||
|
||||
ENDFRAME(_sys_exit)
|
||||
|
||||
|
||||
|
||||
.globl __sizemem
|
||||
.ent __sizemem
|
||||
__sizemem:
|
||||
li v0,HARD_CODED_MEM_SIZE
|
||||
j ra
|
||||
nop
|
||||
.end __sizemem
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
/* bsp_cleanup()
|
||||
*
|
||||
* This routine normally is part of start.s and usually returns
|
||||
* control to a monitor.
|
||||
*
|
||||
* INPUT: NONE
|
||||
*
|
||||
* OUTPUT: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* bspclean.c,v 1.9.6.1 2003/09/04 18:44:52 joel Exp
|
||||
*/
|
||||
|
||||
/*
|
||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
|
||||
* static char _sccsid[] = "@(#)bspclean.c 03/15/96 1.1\n";
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
|
||||
void idtsim__exit();
|
||||
|
||||
void bsp_cleanup( void )
|
||||
{
|
||||
idtsim__exit();
|
||||
}
|
||||
@@ -0,0 +1,124 @@
|
||||
/*
|
||||
* This routine starts the application. It includes application,
|
||||
* board, and monitor specific initialization and configuration.
|
||||
* The generic CPU dependent initialization has been performed
|
||||
* before this routine is invoked.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* bspstart.c,v 1.14.6.1 2003/09/04 18:44:52 joel Exp
|
||||
*/
|
||||
|
||||
/*
|
||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
|
||||
* static char _sccsid[] = "@(#)bspstart.c 06/11/96 1.2\n";
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <rtems/libio.h>
|
||||
#include <rtems/libcsupport.h>
|
||||
|
||||
/*
|
||||
* The original table from the application and our copy of it with
|
||||
* some changes.
|
||||
*/
|
||||
|
||||
extern rtems_configuration_table Configuration;
|
||||
|
||||
rtems_configuration_table BSP_Configuration;
|
||||
|
||||
rtems_cpu_table Cpu_table;
|
||||
|
||||
char *rtems_progname;
|
||||
|
||||
/*
|
||||
* Use the shared implementations of the following routines
|
||||
*/
|
||||
|
||||
void bsp_postdriver_hook(void);
|
||||
void bsp_libc_init( void *, uint32_t, int );
|
||||
|
||||
void init_exc_vecs(void);
|
||||
|
||||
/*
|
||||
* Function: bsp_pretasking_hook
|
||||
* Created: 95/03/10
|
||||
*
|
||||
* Description:
|
||||
* BSP pretasking hook. Called just before drivers are initialized.
|
||||
* Used to setup libc and install any BSP extensions.
|
||||
*
|
||||
* NOTES:
|
||||
* Must not use libc (to do io) from here, since drivers are
|
||||
* not yet initialized.
|
||||
*
|
||||
*/
|
||||
|
||||
#define LIBC_HEAP_SIZE (64 * 1024)
|
||||
|
||||
void bsp_pretasking_hook(void)
|
||||
{
|
||||
extern int end;
|
||||
uint32_t heap_start;
|
||||
|
||||
heap_start = (uint32_t) &end;
|
||||
if (heap_start & (CPU_ALIGNMENT-1))
|
||||
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
|
||||
|
||||
bsp_libc_init((void *) heap_start, LIBC_HEAP_SIZE, 0);
|
||||
|
||||
#ifdef RTEMS_DEBUG
|
||||
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
|
||||
#endif
|
||||
}
|
||||
|
||||
extern int end; /* defined by linker */
|
||||
|
||||
/*
|
||||
* bsp_start
|
||||
*
|
||||
* This routine does the bulk of the system initialization.
|
||||
*/
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
/*
|
||||
* Allocate the memory for the RTEMS Work Space. This can come from
|
||||
* a variety of places: hard coded address, malloc'ed from outside
|
||||
* RTEMS world (e.g. simulator or primitive memory manager), or (as
|
||||
* typically done by stock BSPs) by subtracting the required amount
|
||||
* of work space from the last physical address on the CPU board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Need to "allocate" the memory for the RTEMS Workspace and
|
||||
* tell the RTEMS configuration where it is. This memory is
|
||||
* not malloc'ed. It is just "pulled from the air".
|
||||
*/
|
||||
|
||||
BSP_Configuration.work_space_start =
|
||||
(void *)((uint64_t)((&end) + LIBC_HEAP_SIZE + 0x2000) & ~0x7);
|
||||
|
||||
/*
|
||||
* initialize the CPU table for this BSP
|
||||
*/
|
||||
|
||||
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
|
||||
Cpu_table.postdriver_hook = bsp_postdriver_hook;
|
||||
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
|
||||
Cpu_table.clicks_per_microsecond = CPU_CLOCK_RATE_MHZ;
|
||||
|
||||
mips_install_isr_entries(); /* Install generic MIPS exception handler */
|
||||
|
||||
/* init_exc_vecs(); */ /* Install BSP specific exception handler */
|
||||
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,19 @@
|
||||
#
|
||||
# ghlinkcmds,v 1.2 1998/01/16 16:56:32 joel Exp
|
||||
#
|
||||
|
||||
-map
|
||||
-sec
|
||||
{
|
||||
.text 0x80010000 :
|
||||
.data align(16) :
|
||||
.rodata :
|
||||
.fini :
|
||||
# .sdata :
|
||||
.symtab :
|
||||
.strtab :
|
||||
.debug :
|
||||
# .sbss :
|
||||
.bss align(8) :
|
||||
.init 0xbfc00000 :
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,390 @@
|
||||
/*
|
||||
|
||||
Based upon IDT provided code with the following release:
|
||||
|
||||
This source code has been made available to you by IDT on an AS-IS
|
||||
basis. Anyone receiving this source is licensed under IDT copyrights
|
||||
to use it in any way he or she deems fit, including copying it,
|
||||
modifying it, compiling it, and redistributing it either with or
|
||||
without modifications. No license under IDT patents or patent
|
||||
applications is to be implied by the copyright license.
|
||||
|
||||
Any user of this software should understand that IDT cannot provide
|
||||
technical support for this software and will not be responsible for
|
||||
any consequences resulting from the use of this software.
|
||||
|
||||
Any person who transfers this source code or any derivative work must
|
||||
include the IDT copyright notice, this paragraph, and the preceeding
|
||||
two paragraphs in the transferred software.
|
||||
|
||||
COPYRIGHT IDT CORPORATION 1996
|
||||
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
|
||||
|
||||
idttlb.S,v 1.3 2000/10/24 21:50:37 joel Exp
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
** idttlb.s - fetch the registers associated with and the contents
|
||||
** of the tlb.
|
||||
**
|
||||
*/
|
||||
/* 950308: Ketan patched a few tlb functions that would not have worked.*/
|
||||
#include <rtems/mips/iregdef.h>
|
||||
#include <rtems/mips/idtcpu.h>
|
||||
#include <rtems/asm.h>
|
||||
|
||||
|
||||
.text
|
||||
|
||||
#if __mips == 1
|
||||
/*
|
||||
** ret_tlblo -- returns the 'entrylo' contents for the TLB
|
||||
** 'c' callable - as ret_tlblo(index) - where index is the
|
||||
** tlb entry to return the lo value for - if called from assembly
|
||||
** language then index should be in register a0.
|
||||
*/
|
||||
FRAME(ret_tlblo,sp,0,ra)
|
||||
.set noreorder
|
||||
mfc0 t0,C0_SR # save sr
|
||||
nop
|
||||
and t0,~SR_PE # dont inadvertantly clear PE
|
||||
mtc0 zero,C0_SR # clear interrupts
|
||||
mfc0 t1,C0_TLBHI # save pid
|
||||
sll a0,TLBINX_INXSHIFT # position index
|
||||
mtc0 a0,C0_INX # write to index register
|
||||
nop
|
||||
tlbr # put tlb entry in entrylo and hi
|
||||
nop
|
||||
mfc0 v0,C0_TLBLO # get the requested entry lo
|
||||
mtc0 t1,C0_TLBHI # restore pid
|
||||
mtc0 t0,C0_SR # restore status register
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
ENDFRAME(ret_tlblo)
|
||||
#endif
|
||||
#if __mips == 3
|
||||
/*
|
||||
** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB
|
||||
** 'c' callable - as ret_tlblo(index) - where index is the
|
||||
** tlb entry to return the lo value for - if called from assembly
|
||||
** language then index should be in register a0.
|
||||
*/
|
||||
FRAME(ret_tlblo0,sp,0,ra)
|
||||
mfc0 t0,C0_SR # save sr
|
||||
mtc0 zero,C0_SR # clear interrupts
|
||||
mfc0 t1,C0_TLBHI # save pid
|
||||
mtc0 a0,C0_INX # write to index register
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbr # put tlb entry in entrylo and hi
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mfc0 v0,C0_TLBLO0 # get the requested entry lo
|
||||
mtc0 t1,C0_TLBHI # restore pid
|
||||
mtc0 t0,C0_SR # restore status register
|
||||
j ra
|
||||
ENDFRAME(ret_tlblo0)
|
||||
|
||||
FRAME(ret_tlblo1,sp,0,ra)
|
||||
mfc0 t0,C0_SR # save sr
|
||||
mtc0 zero,C0_SR # clear interrupts
|
||||
mfc0 t1,C0_TLBHI # save pid
|
||||
mtc0 a0,C0_INX # write to index register
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbr # put tlb entry in entrylo and hi
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mfc0 v0,C0_TLBLO1 # get the requested entry lo
|
||||
mtc0 t1,C0_TLBHI # restore pid
|
||||
mtc0 t0,C0_SR # restore status register
|
||||
j ra
|
||||
ENDFRAME(ret_tlblo1)
|
||||
|
||||
/*
|
||||
** ret_pagemask(index) -- return pagemask contents of tlb entry "index"
|
||||
*/
|
||||
FRAME(ret_pagemask,sp,0,ra)
|
||||
mfc0 t0,C0_SR # save sr
|
||||
mtc0 zero,C0_SR # disable interrupts
|
||||
mfc0 t1,C0_TLBHI # save current pid
|
||||
mtc0 a0,C0_INX # drop it in C0 register
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbr # read entry to entry hi/lo
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mfc0 v0,C0_PAGEMASK # to return value
|
||||
mtc0 t1,C0_TLBHI # restore current pid
|
||||
mtc0 t0,C0_SR # restore sr
|
||||
j ra
|
||||
ENDFRAME(ret_pagemask)
|
||||
|
||||
/*
|
||||
** ret_tlbwired(void) -- return wired register
|
||||
*/
|
||||
FRAME(ret_tlbwired,sp,0,ra)
|
||||
mfc0 v0,C0_WIRED
|
||||
j ra
|
||||
ENDFRAME(ret_tlbwired)
|
||||
#endif
|
||||
|
||||
/*
|
||||
** ret_tlbhi -- return the tlb entry high content for tlb entry
|
||||
** index
|
||||
*/
|
||||
FRAME(ret_tlbhi,sp,0,ra)
|
||||
#if __mips == 1
|
||||
.set noreorder
|
||||
mfc0 t0,C0_SR # save sr
|
||||
nop
|
||||
and t0,~SR_PE
|
||||
mtc0 zero,C0_SR # disable interrupts
|
||||
mfc0 t1,C0_TLBHI # save current pid
|
||||
sll a0,TLBINX_INXSHIFT # position index
|
||||
mtc0 a0,C0_INX # drop it in C0 register
|
||||
nop
|
||||
tlbr # read entry to entry hi/lo
|
||||
nop
|
||||
mfc0 v0,C0_TLBHI # to return value
|
||||
mtc0 t1,C0_TLBHI # restore current pid
|
||||
mtc0 t0,C0_SR # restore sr
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
#endif
|
||||
#if __mips == 3
|
||||
mfc0 t0,C0_SR # save sr
|
||||
mtc0 zero,C0_SR # disable interrupts
|
||||
mfc0 t1,C0_TLBHI # save current pid
|
||||
mtc0 a0,C0_INX # drop it in C0 register
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbr # read entry to entry hi/lo0/lo1/mask
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mfc0 v0,C0_TLBHI # to return value
|
||||
mtc0 t1,C0_TLBHI # restore current pid
|
||||
mtc0 t0,C0_SR # restore sr
|
||||
j ra
|
||||
#endif
|
||||
ENDFRAME(ret_tlbhi)
|
||||
|
||||
/*
|
||||
** ret_tlbpid() -- return tlb pid contained in the current entry hi
|
||||
*/
|
||||
FRAME(ret_tlbpid,sp,0,ra)
|
||||
#if __mips == 1
|
||||
.set noreorder
|
||||
mfc0 v0,C0_TLBHI # fetch tlb high
|
||||
nop
|
||||
and v0,TLBHI_PIDMASK # isolate and position
|
||||
srl v0,TLBHI_PIDSHIFT
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
#endif
|
||||
#if __mips == 3
|
||||
mfc0 v0,C0_TLBHI # to return value
|
||||
nop
|
||||
and v0,TLBHI_PIDMASK
|
||||
j ra
|
||||
#endif
|
||||
ENDFRAME(ret_tlbpid)
|
||||
|
||||
/*
|
||||
** tlbprobe(address, pid) -- probe the tlb to see if address is currently
|
||||
** mapped
|
||||
** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000...
|
||||
** virtual page numbers for the r3000 are in
|
||||
** entry hi bits 31-12
|
||||
** a1 = pid - this is a process id ranging from 0 to 63
|
||||
** this process id is shifted left 6 bits and or'ed into
|
||||
** the entry hi register
|
||||
** returns an index value (0-63) if successful -1 -f not
|
||||
*/
|
||||
FRAME(tlbprobe,sp,0,ra)
|
||||
#if __mips == 1
|
||||
.set noreorder
|
||||
mfc0 t0,C0_SR /* fetch status reg */
|
||||
and a0,TLBHI_VPNMASK /* isolate just the vpn */
|
||||
and t0,~SR_PE /* don't inadvertantly clear pe */
|
||||
mtc0 zero,C0_SR
|
||||
mfc0 t1,C0_TLBHI
|
||||
sll a1,TLBHI_PIDSHIFT /* possition the pid */
|
||||
and a1,TLBHI_PIDMASK
|
||||
or a0,a1 /* build entry hi value */
|
||||
mtc0 a0,C0_TLBHI
|
||||
nop
|
||||
tlbp /* do the probe */
|
||||
nop
|
||||
mfc0 v1,C0_INX
|
||||
li v0,-1
|
||||
bltz v1,1f
|
||||
nop
|
||||
sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */
|
||||
1:
|
||||
mtc0 t1,C0_TLBHI /* restore tlb hi */
|
||||
mtc0 t0,C0_SR /* restore the status reg */
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
#endif
|
||||
#if __mips == 3
|
||||
mfc0 t0,C0_SR # save sr
|
||||
mtc0 zero,C0_SR # disable interrupts
|
||||
mfc0 t1,C0_TLBHI # save current pid
|
||||
and a0,TLBHI_VPN2MASK # construct tlbhi for probe
|
||||
and a1,TLBHI_PIDMASK
|
||||
or a0,a1
|
||||
mtc0 a0,C0_TLBHI
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbp # probe entry to entry hi/lo0/lo1/mask
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mfc0 v1,C0_INX
|
||||
li v0,-1
|
||||
bltz v1,1f
|
||||
move v0,v1
|
||||
1: mtc0 t1,C0_TLBHI # restore current pid
|
||||
mtc0 t0,C0_SR # restore sr
|
||||
j ra
|
||||
#endif
|
||||
ENDFRAME(tlbprobe)
|
||||
|
||||
/*
|
||||
** resettlb(index) Invalidate the TLB entry specified by index
|
||||
*/
|
||||
FRAME(resettlb,sp,0,ra)
|
||||
#if __mips == 1
|
||||
.set noreorder
|
||||
mfc0 t0,C0_TLBHI # fetch the current hi
|
||||
mfc0 v0,C0_SR # fetch the status reg.
|
||||
li t2,K0BASE&TLBHI_VPNMASK
|
||||
and v0,~SR_PE # dont inadvertantly clear PE
|
||||
mtc0 zero,C0_SR
|
||||
mtc0 t2,C0_TLBHI # set up tlbhi
|
||||
mtc0 zero,C0_TLBLO
|
||||
sll a0,TLBINX_INXSHIFT
|
||||
mtc0 a0,C0_INX
|
||||
nop
|
||||
tlbwi # do actual invalidate
|
||||
nop
|
||||
mtc0 t0,C0_TLBHI
|
||||
mtc0 v0,C0_SR
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
#endif
|
||||
#if __mips == 3
|
||||
li t2,K0BASE&TLBHI_VPN2MASK
|
||||
mfc0 t0,C0_TLBHI # save current TLBHI
|
||||
mfc0 v0,C0_SR # save SR and disable interrupts
|
||||
mtc0 zero,C0_SR
|
||||
mtc0 t2,C0_TLBHI # invalidate entry
|
||||
mtc0 zero,C0_TLBLO0
|
||||
mtc0 zero,C0_TLBLO1
|
||||
mtc0 a0,C0_INX
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbwi
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mtc0 t0,C0_TLBHI
|
||||
mtc0 v0,C0_SR
|
||||
j ra
|
||||
#endif
|
||||
ENDFRAME(resettlb)
|
||||
|
||||
#if __mips == 1
|
||||
/*
|
||||
** Setup TLB entry
|
||||
**
|
||||
** map_tlb(index, tlbhi, phypage)
|
||||
** a0 = TLB entry index
|
||||
** a1 = virtual page number and PID
|
||||
** a2 = physical page
|
||||
*/
|
||||
FRAME(map_tlb,sp,0,ra)
|
||||
.set noreorder
|
||||
sll a0,TLBINX_INXSHIFT
|
||||
mfc0 v0,C0_SR # fetch the current status
|
||||
mfc0 a3,C0_TLBHI # save the current hi
|
||||
and v0,~SR_PE # dont inadvertantly clear parity
|
||||
|
||||
mtc0 zero,C0_SR
|
||||
mtc0 a1,C0_TLBHI # set the hi entry
|
||||
mtc0 a2,C0_TLBLO # set the lo entry
|
||||
mtc0 a0,C0_INX # load the index
|
||||
nop
|
||||
tlbwi # put the hi/lo in tlb entry indexed
|
||||
nop
|
||||
mtc0 a3,C0_TLBHI # put back the tlb hi reg
|
||||
mtc0 v0,C0_SR # restore the status register
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
ENDFRAME(map_tlb)
|
||||
#endif
|
||||
#if __mips == 3
|
||||
/*
|
||||
** Setup R4000 TLB entry
|
||||
**
|
||||
** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd)
|
||||
** a0 = TLB entry index and page mask
|
||||
** a1 = virtual page number and PID
|
||||
** a2 = pte -- contents of even pte
|
||||
** a3 = pte -- contents of odd pte
|
||||
*/
|
||||
FRAME(map_tlb4000,sp,0,ra)
|
||||
and t2,a0,TLBPGMASK_MASK
|
||||
and a0,TLBINX_INXMASK
|
||||
mfc0 t1,C0_TLBHI # save current TLBPID
|
||||
mfc0 v0,C0_SR # save SR and disable interrupts
|
||||
mtc0 zero,C0_SR
|
||||
mtc0 t2,C0_PAGEMASK # set
|
||||
mtc0 a1,C0_TLBHI # set VPN and TLBPID
|
||||
mtc0 a2,C0_TLBLO0 # set PPN and access bits
|
||||
mtc0 a3,C0_TLBLO1 # set PPN and access bits
|
||||
mtc0 a0,C0_INX # set INDEX to wired entry
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
tlbwi # drop it in
|
||||
.set noreorder
|
||||
nop; nop; nop; nop; nop; nop; nop; nop
|
||||
.set reorder
|
||||
mtc0 t1,C0_TLBHI # restore TLBPID
|
||||
mtc0 v0,C0_SR # restore SR
|
||||
j ra
|
||||
ENDFRAME(map_tlb4000)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
** Set current TLBPID. This assumes PID is positioned correctly in reg.
|
||||
** a0.
|
||||
*/
|
||||
FRAME(set_tlbpid,sp,0,ra)
|
||||
.set noreorder
|
||||
mtc0 a0,C0_TLBHI
|
||||
j ra
|
||||
nop
|
||||
.set reorder
|
||||
ENDFRAME(set_tlbpid)
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* inittlb.c,v 1.2 1999/03/31 23:21:19 joel Exp
|
||||
*/
|
||||
|
||||
#include <rtems/mips/idtcpu.h>
|
||||
|
||||
extern void resettlb( int i );
|
||||
|
||||
void init_tlb(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < N_TLB_ENTRIES; i++ )
|
||||
resettlb(i);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
* linkcmds,v 1.6 2003/01/20 20:20:10 joel Exp
|
||||
*/
|
||||
|
||||
/*
|
||||
* Declare some sizes.
|
||||
*/
|
||||
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x80000000;
|
||||
_RamSize = DEFINED(_RamSize) ? _RamSize : 4M;
|
||||
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* 0x80000000 - 0x8001FFFF used by PMON (with 0x80010000 - 0x8001FFFF as heap for symbol storage)
|
||||
0x80020000 - 0x8002FFFF reserved for shared memory
|
||||
0x80030000 beginning of text (code) section
|
||||
*/
|
||||
.text 0x80030000 :
|
||||
{
|
||||
_ftext = . ;
|
||||
eprol = .;
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
PROVIDE (__runtime_reloc_start = .);
|
||||
*(.rel.sdata)
|
||||
PROVIDE (__runtime_reloc_stop = .);
|
||||
|
||||
/*
|
||||
* Special FreeBSD sysctl sections.
|
||||
*/
|
||||
. = ALIGN (16);
|
||||
__start_set_sysctl_set = .;
|
||||
*(set_sysctl_*);
|
||||
__stop_set_sysctl_set = ABSOLUTE(.);
|
||||
*(set_domain_*);
|
||||
*(set_pseudo_*);
|
||||
|
||||
*(.gcc_except_table)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
}
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP(*crti.o(.init))
|
||||
KEEP(*(.init))
|
||||
KEEP(*crtn.o(.init))
|
||||
}
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP(*crti.o(.fini))
|
||||
KEEP(*(.fini))
|
||||
KEEP(*crtn.o(.fini))
|
||||
}
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
}
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
|
||||
etext = .;
|
||||
_etext = .;
|
||||
}
|
||||
|
||||
.rdata : {
|
||||
*(.rdata)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r*)
|
||||
}
|
||||
_fdata = ALIGN(16);
|
||||
|
||||
.data : {
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
SORT(CONSTRUCTORS)
|
||||
}
|
||||
. = ALIGN(8);
|
||||
|
||||
.jcr : {
|
||||
KEEP (*(.jcr))
|
||||
}
|
||||
|
||||
_gp = ALIGN(16) + 0x8000;
|
||||
__global = _gp;
|
||||
|
||||
.sdata : {
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s*)
|
||||
}
|
||||
.lit8 : {
|
||||
*(.lit8)
|
||||
}
|
||||
.lit4 : {
|
||||
*(.lit4)
|
||||
}
|
||||
|
||||
edata = .;
|
||||
_edata = .;
|
||||
_fbss = .;
|
||||
|
||||
.sbss : {
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
}
|
||||
.bss : {
|
||||
_bss_start = . ;
|
||||
*(.bss)
|
||||
*(.reginfo)
|
||||
*(COMMON)
|
||||
. = ALIGN (64);
|
||||
_stack_limit = .;
|
||||
. += _StackSize;
|
||||
__stack = .;
|
||||
_stack_init = .;
|
||||
end = .;
|
||||
_end = .;
|
||||
}
|
||||
|
||||
|
||||
/* Debug sections. These should never be loadable, but they must have
|
||||
zero addresses for the debuggers to work correctly. */
|
||||
.line 0 : { *(.line) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
/* set_vector
|
||||
*
|
||||
* This routine installs an interrupt vector on the target Board/CPU.
|
||||
* This routine is allowed to be as board dependent as necessary.
|
||||
*
|
||||
* INPUT:
|
||||
* handler - interrupt handler entry point
|
||||
* vector - vector number
|
||||
* type - 0 indicates raw hardware connect
|
||||
* 1 indicates RTEMS interrupt connect
|
||||
*
|
||||
* RETURNS:
|
||||
* address of previous interrupt handler
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* setvec.c,v 1.8.6.1 2003/09/04 18:44:52 joel Exp
|
||||
*/
|
||||
|
||||
/*
|
||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
|
||||
* static char _sccsid[] = "@(#)setvec.c 04/25/96 1.2\n";
|
||||
*/
|
||||
|
||||
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
|
||||
mips_isr_entry set_vector( /* returns old vector */
|
||||
rtems_isr_entry handler, /* isr routine */
|
||||
rtems_vector_number vector, /* vector number */
|
||||
int type /* RTEMS or RAW intr */
|
||||
)
|
||||
{
|
||||
mips_isr_entry previous_isr;
|
||||
|
||||
if ( type )
|
||||
rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
|
||||
else {
|
||||
/* XXX: install non-RTEMS ISR as "raw" interupt */
|
||||
rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
|
||||
}
|
||||
return previous_isr;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,200 @@
|
||||
#
|
||||
# Timing Test Suite Results for the NO_BSP
|
||||
#
|
||||
# NOTE: This is just a template. The times are irrelevant since this BSP
|
||||
# can only be compiled -- not executed.
|
||||
#
|
||||
# times,v 1.2 1998/01/16 16:56:32 joel Exp
|
||||
#
|
||||
# @(#)times 08/01/96 1.4
|
||||
|
||||
NOTE: To obtain the execution time in microseconds, divide the number of
|
||||
cycles by the clock speed. For example, if rtems_semaphore create
|
||||
is reported to be 1164 cycles, then at 66 Mhz it takes 17.64
|
||||
microseconds or 8.75 microseconds at 133 Mhz.
|
||||
|
||||
Board: Algorithmics P4000i
|
||||
CPU: IDT 4650
|
||||
Clock Speed: 100MHz
|
||||
Memory Configuration: SRAM, DRAM, cache, etc
|
||||
Wait States:
|
||||
|
||||
Times Reported in: cycles
|
||||
Timer Source: on-CPU cycle counter
|
||||
|
||||
Column A:RTEMS compiled with 64 bit pointers and 64 bit unsigned32 types
|
||||
Column B:RTEMS compiled with 32 bit pointers and 32 bit unsigned32 types
|
||||
|
||||
# DESCRIPTION A B
|
||||
== ================================================================= ==== ====
|
||||
1 rtems_semaphore_create 788 759
|
||||
rtems_semaphore_delete 903 945
|
||||
rtems_semaphore_obtain: available 119 119
|
||||
rtems_semaphore_obtain: not available -- NO_WAIT 118 118
|
||||
rtems_semaphore_release: no waiting tasks 127 127
|
||||
|
||||
2 rtems_semaphore_obtain: not available -- caller blocks 842 840
|
||||
|
||||
3 rtems_semaphore_release: task readied -- preempts caller 777 751
|
||||
|
||||
4 rtems_task_restart: blocked task -- preempts caller 1611 1595
|
||||
rtems_task_restart: ready task -- preempts caller 1253 1395
|
||||
rtems_semaphore_release: task readied -- returns to caller 365 345
|
||||
rtems_task_create 798 797
|
||||
rtems_task_start 464 460
|
||||
rtems_task_restart: suspended task -- returns to caller 517 517
|
||||
rtems_task_delete: suspended task 529 595
|
||||
rtems_task_restart: ready task -- returns to caller 527 525
|
||||
rtems_task_restart: blocked task -- returns to caller 707 684
|
||||
rtems_task_delete: blocked task 609 675
|
||||
|
||||
5 rtems_task_suspend: calling task 549 549
|
||||
rtems_task_resume: task readied -- preempts caller 702 699
|
||||
|
||||
6 rtems_task_restart: calling task 291 291
|
||||
rtems_task_suspend: returns to caller 195 194
|
||||
rtems_task_resume: task readied -- returns to caller 198 198
|
||||
rtems_task_delete: ready task 734 736
|
||||
|
||||
7 rtems_task_restart: suspended task -- preempts caller 1049 990
|
||||
|
||||
8 rtems_task_set_priority: obtain current priority 94 94
|
||||
rtems_task_set_priority: returns to caller 418 355
|
||||
rtems_task_mode: obtain current mode 44 43
|
||||
rtems_task_mode: no reschedule 0 49
|
||||
rtems_task_mode: reschedule -- returns to caller 0 232
|
||||
rtems_task_mode: reschedule -- preempts caller 0 687
|
||||
rtems_task_set_note 0 101
|
||||
rtems_task_get_note 0 103
|
||||
rtems_clock_set 0 237
|
||||
rtems_clock_get 0 16
|
||||
|
||||
9 rtems_message_queue_create 3583 3432
|
||||
rtems_message_queue_send: no waiting tasks 252 252
|
||||
rtems_message_queue_urgent: no waiting tasks 252 252
|
||||
rtems_message_queue_receive: available 207 207
|
||||
rtems_message_queue_flush: no messages flushed 95 96
|
||||
rtems_message_queue_flush: messages flushed 110 110
|
||||
rtems_message_queue_delete 1044 1111
|
||||
|
||||
10 rtems_message_queue_receive: not available -- NO_WAIT 132 131
|
||||
rtems_message_queue_receive: not available -- caller blocks 884 892
|
||||
|
||||
11 rtems_message_queue_send: task readied -- preempts caller 397 817
|
||||
|
||||
12 rtems_message_queue_send: task readied -- returns to caller 397 397
|
||||
|
||||
13 rtems_message_queue_urgent: task readied -- preempts caller 816 817
|
||||
|
||||
14 rtems_message_queue_urgent: task readied -- returns to caller 397 398
|
||||
|
||||
15 rtems_event_receive: obtain current events 5 5
|
||||
rtems_event_receive: not available -- NO_WAIT 99 99
|
||||
rtems_event_receive: not available -- caller blocks 689 689
|
||||
rtems_event_send: no task readied 123 123
|
||||
rtems_event_receive: available 326 349
|
||||
rtems_event_send: task readied -- returns to caller 333 429
|
||||
|
||||
16 rtems_event_send: task readied -- preempts caller 843 838
|
||||
|
||||
17 rtems_task_set_priority: preempts caller 1002 991
|
||||
|
||||
18 rtems_task_delete: calling task 1171 1157
|
||||
|
||||
19 rtems_signal_catch 0 1306
|
||||
rtems_signal_send: returns to caller 0 1019
|
||||
rtems_signal_send: signal to self 0 496
|
||||
exit ASR overhead: returns to calling task 0 120
|
||||
exit ASR overhead: returns to preempting task 0 73
|
||||
|
||||
20 rtems_partition_create 1293 1306
|
||||
rtems_region_create 1010 1019
|
||||
rtems_partition_get_buffer: available 481 496
|
||||
rtems_partition_get_buffer: not available 120 120
|
||||
rtems_partition_return_buffer 587 460
|
||||
rtems_partition_delete 379 320
|
||||
rtems_region_get_segment: available 179 179
|
||||
rtems_region_get_segment: not available -- NO_WAIT 349 293
|
||||
rtems_region_return_segment: no waiting tasks 335 322
|
||||
rtems_region_get_segment: not available -- caller blocks 1603 1496
|
||||
rtems_region_return_segment: task readied -- preempts caller 1616 1533
|
||||
rtems_region_return_segment: task readied -- returns to caller 940 939
|
||||
rtems_region_delete 301 348
|
||||
rtems_io_initialize 9 10
|
||||
rtems_io_open 6 6
|
||||
rtems_io_close 6 6
|
||||
rtems_io_read 6 6
|
||||
rtems_io_write 6 5
|
||||
rtems_io_control 6 6
|
||||
|
||||
21 rtems_task_ident 1057 1058
|
||||
rtems_message_queue_ident 963 963
|
||||
rtems_semaphore_ident 1137 1136
|
||||
rtems_partition_ident 962 961
|
||||
rtems_region_ident 923 924
|
||||
rtems_port_ident 918 917
|
||||
rtems_timer_ident 942 941
|
||||
rtems_rate_monotonic_ident 924 925
|
||||
|
||||
22 rtems_message_queue_broadcast: task readied -- returns to caller 1084 1095
|
||||
rtems_message_queue_broadcast: no waiting tasks 147 148
|
||||
rtems_message_queue_broadcast: task readied -- preempts caller 1305 1268
|
||||
|
||||
23 rtems_timer_create 202 201
|
||||
rtems_timer_fire_after: inactive 261 261
|
||||
rtems_timer_fire_after: active 271 269
|
||||
rtems_timer_cancel: active 142 141
|
||||
rtems_timer_cancel: inactive 122 124
|
||||
rtems_timer_reset: inactive 222 222
|
||||
rtems_timer_reset: active 246 245
|
||||
rtems_timer_fire_when: inactive 312 311
|
||||
rtems_timer_fire_when: active 358 358
|
||||
rtems_timer_delete: active 263 263
|
||||
rtems_timer_delete: inactive 247 247
|
||||
rtems_task_wake_when 833 831
|
||||
|
||||
24 rtems_task_wake_after: yield -- returns to caller 99 98
|
||||
rtems_task_wake_after: yields -- preempts caller 479 478
|
||||
|
||||
25 rtems_clock_tick 313 318
|
||||
|
||||
26 _ISR_Disable 64 57
|
||||
_ISR_Flash 51 36
|
||||
_ISR_Enable 31 18
|
||||
_Thread_Disable_dispatch 53 37
|
||||
_Thread_Enable_dispatch 260 233
|
||||
_Thread_Set_state 446 463
|
||||
_Thread_Disptach (NO FP) 839 801
|
||||
context switch: no floating point contexts 673 653
|
||||
context switch: self 156 162
|
||||
context switch: to another task 84 70
|
||||
context switch: restore 1st FP task 1030 1013
|
||||
fp context switch: save idle, restore idle 969 948
|
||||
fp context switch: save idle, restore initialized 275 267
|
||||
fp context switch: save initialized, restore initialized 319 292
|
||||
_Thread_Resume 512 480
|
||||
_Thread_Unblock 121 139
|
||||
_Thread_Ready 199 203
|
||||
_Thread_Get 27 27
|
||||
_Semaphore_Get 20 21
|
||||
_Thread_Get: invalid id 5 5
|
||||
|
||||
27 interrupt entry overhead: returns to interrupted task 0 0
|
||||
interrupt exit overhead: returns to interrupted task 27 41
|
||||
interrupt entry overhead: returns to nested interrupt 0 0
|
||||
interrupt exit overhead: returns to nested interrupt 0 0
|
||||
interrupt entry overhead: returns to preempting task 0 0
|
||||
interrupt exit overhead: returns to preempting task 0 0
|
||||
|
||||
28 rtems_port_create 574 560
|
||||
rtems_port_external_to_internal 87 87
|
||||
rtems_port_internal_to_external 86 86
|
||||
rtems_port_delete 395 353
|
||||
|
||||
29 rtems_rate_monotonic_create 621 633
|
||||
rtems_rate_monotonic_period: initiate period -- returns to caller 773 694
|
||||
rtems_rate_monotonic_period: obtain status 295 284
|
||||
rtems_rate_monotonic_cancel 408 451
|
||||
rtems_rate_monotonic_delete: inactive 453 471
|
||||
rtems_rate_monotonic_delete: active 332 336
|
||||
rtems_rate_monotonic_period: conclude periods -- caller blocks 664 686
|
||||
Reference in New Issue
Block a user