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bsp/imxrt: Add new BSP

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Update #4180
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Christian Mauderer committed 2020-11-20 08:53:19 +01:00
1 parent 57b5b29ce4
commit 7141afbb0e
37 files changed
+5362 -36
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bsps/arm/imxrt/console/console.c
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bsps/arm/imxrt/dts/imxrt1050-evkb.c
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bsps/arm/imxrt/dts/imxrt1050-evkb.dts
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bsps/arm/imxrt/i2c/imxrt-lpi2c.c
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bsps/arm/imxrt/include/bsp.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsARMimxrt
*/
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_IMXRT_BSP_H
#define LIBBSP_ARM_IMXRT_BSP_H
/**
* @defgroup RTEMSBSPsARMimxrt NXP i.MXRT
*
* @ingroup RTEMSBSPsARM
*
* @brief NXP i.MXRT Board Support Package.
*
* @{
*/
#include <bspopts.h>
#include <rtems.h>
#include <bsp/default-initial-extension.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define BSP_FEATURE_IRQ_EXTENSION
#define BSP_FDT_IS_SUPPORTED
extern const unsigned char imxrt_dtb[];
extern const size_t imxrt_dtb_size;
void *imx_get_reg_of_node(const void *fdt, int node);
rtems_vector_number imx_get_irq_of_node(
const void *fdt,
int node,
size_t index
);
bool imxrt_fdt_node_is_enabled(const void *fdt, int node);
/*
* About 50% between `basepri` in arm_interrupt_disable and the maximum for this
* chip.
*/
#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4)
#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4)
#define BSP_ARMV7M_SYSTICK_FREQUENCY imxrt_systick_frequency()
uint32_t imxrt_systick_frequency(void);
void imxrt_lpspi_init(void);
void imxrt_lpi2c_init(void);
void imxrt_ffec_init(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
/* @} */
#endif /* LIBBSP_ARM_IMXRT_BSP_H */
bsps/arm/imxrt/include/bsp/flash-headers.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsARMimxrt
*
* @brief Header structures that are used by i.MXRT1050 for booting from flash.
*/
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_IMXRT_FLASH_HEADERS_H
#define LIBBSP_ARM_IMXRT_FLASH_HEADERS_H
#include <stdint.h>
#include <fsl_flexspi_nor_config.h>
#include <fsl_flexspi_nor_boot.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
__attribute__((section(".boot_hdr.dcd_data")))
extern const uint8_t imxrt_dcd_data[];
__attribute__((section(".boot_hdr.ivt")))
extern const ivt imxrt_image_vector_table;
__attribute__((section(".boot_hdr.boot_data")))
extern const BOOT_DATA_T imxrt_boot_data;
__attribute__((section(".boot_hdr.conf")))
extern const flexspi_nor_config_t imxrt_flexspi_config;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_IMXRT_FLASH_HEADERS_H */
bsps/arm/imxrt/include/bsp/irq.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsARMimxrt
*/
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_IMXRT_IRQ_H
#define LIBBSP_ARM_IMXRT_IRQ_H
#ifndef ASM
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
#endif /* ASM */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define BSP_INTERRUPT_VECTOR_MIN 0
#define BSP_INTERRUPT_VECTOR_MAX 159
#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_IMXRT_IRQ_H */
bsps/arm/imxrt/include/chip.h
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#include "MIMXRT1052.h"
#include "MIMXRT1052_features.h"
bsps/arm/imxrt/include/imxrt/imxrt1050-pinfunc.h
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bsps/arm/imxrt/include/imxrt/memory.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SMEMORYL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_IMXRT_IMXRT_MEMORY_H
#define LIBBSP_ARM_IMXRT_IMXRT_MEMORY_H
#ifdef __cplusplus
extern "C" {
#endif
extern char imxrt_memory_null_begin[];
extern char imxrt_memory_null_end[];
extern char imxrt_memory_null_size[];
extern char imxrt_memory_itcm_begin[];
extern char imxrt_memory_itcm_end[];
extern char imxrt_memory_itcm_size[];
extern char imxrt_memory_dtcm_begin[];
extern char imxrt_memory_dtcm_end[];
extern char imxrt_memory_dtcm_size[];
extern char imxrt_memory_ocram_begin[];
extern char imxrt_memory_ocram_end[];
extern char imxrt_memory_ocram_size[];
extern char imxrt_memory_peripheral_begin[];
extern char imxrt_memory_peripheral_end[];
extern char imxrt_memory_peripheral_size[];
extern char imxrt_memory_flexspi_config_begin[];
extern char imxrt_memory_flexspi_config_end[];
extern char imxrt_memory_flexspi_config_size[];
extern char imxrt_memory_flexspi_ivt_begin[];
extern char imxrt_memory_flexspi_ivt_end[];
extern char imxrt_memory_flexspi_ivt_size[];
extern char imxrt_memory_flexspi_begin[];
extern char imxrt_memory_flexspi_end[];
extern char imxrt_memory_flexspi_size[];
extern char imxrt_memory_flexspi_fifo_begin[];
extern char imxrt_memory_flexspi_fifo_end[];
extern char imxrt_memory_flexspi_fifo_size[];
extern char imxrt_memory_sdram_begin[];
extern char imxrt_memory_sdram_end[];
extern char imxrt_memory_sdram_size[];
extern char imxrt_memory_sdram_nocache_begin[];
extern char imxrt_memory_sdram_nocache_end[];
extern char imxrt_memory_sdram_nocache_size[];
#ifdef __cplusplus
}
#endif
#endif /* LIBBSP_ARM_IMXRT_IMXRT_MEMORY_H */
bsps/arm/imxrt/include/imxrt/mpu-config.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsARMimxrt
*
* @brief MPU configuration.
*/
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_IMXRT_IMXRT_MPU_CONFIG_H
#define LIBBSP_ARM_IMXRT_IMXRT_MPU_CONFIG_H
#include <bsp/start.h>
#include <rtems/score/armv7m.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
extern BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config
imxrt_config_mpu_region[];
extern BSP_START_DATA_SECTION const size_t imxrt_config_mpu_region_count;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_IMXRT_IMXRT_MPU_CONFIG_H */
bsps/arm/imxrt/include/tm27.h
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#include <rtems/tm27-default.h>
bsps/arm/imxrt/spi/imxrt-lpspi.c
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bsps/arm/imxrt/start/bspstart.c
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <rtems/sysinit.h>
#include <bsp.h>
#include <bsp/bootcard.h>
#include <bsp/fdt.h>
#include <bsp/imx-iomux.h>
#include <bsp/irq-generic.h>
#include <bsp/irq.h>
#include <bsp/linker-symbols.h>
#include <bsp/flash-headers.h>
#include <fsl_clock.h>
#include <libfdt.h>
uint32_t imxrt_systick_frequency(void)
{
return CLOCK_GetCpuClkFreq();
}
static void imxrt_disable_wait_mode(void)
{
/*
* Prevent processor from entering WAIT or SLEEP mode when a WFI is executed.
* This would switch off the normal interrupt controller and activate an
* alternative one. See "i.MX RT1050 Reference Manual, Rev. 4, 12/2019"
* chapter 14.6.3.2.1 "Entering WAIT mode".
*
* FIXME: For saving energy it would be a better solution to support the
* alternative interrupt controller. But that makes a bit of work necessary on
* every WFI.
*/
CLOCK_SetMode(kCLOCK_ModeRun);
}
void bsp_start(void)
{
imxrt_disable_wait_mode();
bsp_interrupt_initialize();
rtems_cache_coherent_add_area(
bsp_section_nocacheheap_begin,
(uintptr_t) bsp_section_nocacheheap_size
);
}
const void *bsp_fdt_get(void)
{
return imxrt_dtb;
}
bool imxrt_fdt_node_is_enabled(const void *fdt, int node)
{
int len;
const uint32_t *val;
val = fdt_getprop(fdt, node, "status", &len);
if (val != NULL &&
(strcmp((char*)val, "ok") == 0 || strcmp((char*)val, "okay") == 0)) {
return true;
}
return false;
}
void *imx_get_reg_of_node(const void *fdt, int node)
{
int len;
const uint32_t *val;
val = fdt_getprop(fdt, node, "reg", &len);
if (val == NULL || len < 4) {
return NULL;
}
return (void *) fdt32_to_cpu(val[0]);
}
rtems_vector_number imx_get_irq_of_node(
const void *fdt,
int node,
size_t index
)
{
int len;
const uint32_t *val;
val = fdt_getprop(fdt, node, "interrupts", &len);
if (val == NULL || len < (int) ((index) * 4)) {
return BSP_INTERRUPT_VECTOR_INVALID;
}
return fdt32_to_cpu(val[index]);
}
uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
{
return intr[0];
}
/* Make sure to pull in the flash headers */
__attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data;
__attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table;
__attribute__((used)) static const void *hdr_btd = &imxrt_boot_data;
__attribute__((used)) static const void *hdr_fsc = &imxrt_flexspi_config;
/* pull in some drivers */
__attribute__((used)) static const void *drv_iomux = &imx_iomux_configure_pins;
RTEMS_SYSINIT_ITEM(imxrt_lpspi_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
RTEMS_SYSINIT_ORDER_MIDDLE);
RTEMS_SYSINIT_ITEM(imxrt_lpi2c_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
RTEMS_SYSINIT_ORDER_MIDDLE);
RTEMS_SYSINIT_ITEM(imxrt_ffec_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
RTEMS_SYSINIT_ORDER_MIDDLE);
bsps/arm/imxrt/start/bspstarthooks.c
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/*
* Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/score/armv7m.h>
#include <bsp.h>
#include <imxrt/mpu-config.h>
#include <chip.h>
#include <fsl_pin_mux.h>
#include <fsl_clock_config.h>
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
/* FIXME: Initializing SDRAM is currently done by DCD. It would be more user
* friendly if that would be done here with a readable structure. */
if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
SCB_EnableICache();
}
if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
SCB_EnableDCache();
}
_ARMV7M_MPU_Setup(imxrt_config_mpu_region, imxrt_config_mpu_region_count);
}
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
{
bsp_start_copy_sections_compact();
SCB_CleanDCache();
SCB_InvalidateICache();
bsp_start_clear_bss();
BOARD_BootClockRUN();
BOARD_InitDEBUG_UARTPins();
/* Reduce frequency for I2C */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
}
bsps/arm/imxrt/start/flash-boot-data.c
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp/flash-headers.h>
#include <imxrt/memory.h>
#include <bspopts.h>
const BOOT_DATA_T imxrt_boot_data = {
.start = (uint32_t) imxrt_memory_flexspi_config_begin,
.size = IMXRT_MEMORY_FLEXSPI_FLASH_SIZE,
.plugin = PLUGIN_FLAG,
.placeholder = 0xFFFFFFFF,
};
bsps/arm/imxrt/start/flash-config.c
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp/flash-headers.h>
#include <bspopts.h>
const flexspi_nor_config_t imxrt_flexspi_config = {
.memConfig = {
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.columnAddressWidth = 3u,
.controllerMiscOption = (1 << kFlexSpiMiscOffset_DdrModeEnable) |
(1 << kFlexSpiMiscOffset_WordAddressableEnable) |
(1 << kFlexSpiMiscOffset_SafeConfigFreqEnable) |
(1 << kFlexSpiMiscOffset_DiffClkEnable),
.deviceType = kFlexSpiDeviceType_SerialRAM,
.sflashPadType = kSerialFlash_8Pads,
.serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = IMXRT_MEMORY_FLEXSPI_FLASH_SIZE,
.dataValidTime = {16u, 16u},
.lookupTable = {
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
},
.lutCustomSeq = {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
},
.pageSize = 0x200,
.sectorSize = 0x40000,
.blockSize = 0x40000,
.isUniformBlockSize = 1,
};
bsps/arm/imxrt/start/flash-dcd.c
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* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#include <bsp/flash-headers.h>
#include <stdint.h>
#include "dcd.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.dcd_data")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.dcd_data"
#endif
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: DCDx V2.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 0.0.0
board: IMXRT1050-EVKB
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
const uint8_t dcd_data[] = {
const uint8_t imxrt_dcd_data[] = {
/* HEADER */
/* Tag */
0xD2,
@@ -308,8 +281,3 @@ const uint8_t dcd_data[] = {
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
};
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
#else
const uint8_t dcd_data[] = {0x00};
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
#endif /* XIP_BOOT_HEADER_ENABLE */
bsps/arm/imxrt/start/flash-ivt.c
+39
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@@ -0,0 +1,39 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp/flash-headers.h>
#include <bspopts.h>
void _start(void);
const ivt imxrt_image_vector_table = {
.hdr = IVT_HEADER,
.entry = (uint32_t) _start - 1, /* remove thumb mode flag! */
.dcd = (uint32_t) &imxrt_dcd_data,
.boot_data = (uint32_t) &imxrt_boot_data,
.self = (uint32_t) &imxrt_image_vector_table,
};
bsps/arm/imxrt/start/imxrt-ffec-init.c
+86
View File
@@ -0,0 +1,86 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp.h>
#include <bsp/fdt.h>
#include <bsp/imx-gpio.h>
#include <chip.h>
#include <fsl_clock.h>
#include <libfdt.h>
#include <rtems/counter.h>
void imxrt_ffec_init(void)
{
volatile IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR;
const void *fdt;
int node;
fdt = bsp_fdt_get();
const clock_enet_pll_config_t config = {
.enableClkOutput = true,
.enableClkOutput25M = false,
.loopDivider = 1
};
CLOCK_InitEnetPll(&config);
iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec");
if (node >= 0) {
struct imx_gpio_pin reset;
struct imx_gpio_pin interrupt;
rtems_status_code sc;
sc = imx_gpio_init_from_fdt_property(
&reset, node, "phy-reset-gpios",
IMX_GPIO_MODE_OUTPUT, 0);
if (sc == RTEMS_SUCCESSFUL) {
sc = imx_gpio_init_from_fdt_property(
&interrupt, node, "rtems,phy-interrupt-gpios",
IMX_GPIO_MODE_INPUT, 0);
imx_gpio_set_output(&reset, 0);
if (sc == RTEMS_SUCCESSFUL) {
/* Force interrupt GPIO to high. Otherwise we
* get NAND_TREE mode of the PHY. */
interrupt.mode = IMX_GPIO_MODE_OUTPUT;
imx_gpio_init(&interrupt);
imx_gpio_set_output(&interrupt, 1);
}
rtems_counter_delay_nanoseconds(100000);
imx_gpio_set_output(&reset, 1);
rtems_counter_delay_nanoseconds(5);
if (sc == RTEMS_SUCCESSFUL) {
interrupt.mode = IMX_GPIO_MODE_INPUT;
imx_gpio_init(&interrupt);
}
}
}
}
bsps/arm/imxrt/start/linkcmds.flexspi
+35
View File
@@ -0,0 +1,35 @@
INCLUDE linkcmds.memory
REGION_ALIAS ("REGION_START", FLEXSPI);
REGION_ALIAS ("REGION_VECTOR", FLEXSPI);
REGION_ALIAS ("REGION_TEXT", FLEXSPI);
REGION_ALIAS ("REGION_TEXT_LOAD", FLEXSPI);
REGION_ALIAS ("REGION_RODATA", FLEXSPI);
REGION_ALIAS ("REGION_RODATA_LOAD", FLEXSPI);
REGION_ALIAS ("REGION_DATA", SDRAM);
REGION_ALIAS ("REGION_DATA_LOAD", FLEXSPI);
REGION_ALIAS ("REGION_FAST_TEXT", FLEXSPI);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", FLEXSPI);
REGION_ALIAS ("REGION_FAST_DATA", SDRAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", FLEXSPI);
REGION_ALIAS ("REGION_BSS", SDRAM);
REGION_ALIAS ("REGION_WORK", SDRAM);
REGION_ALIAS ("REGION_STACK", SDRAM);
REGION_ALIAS ("REGION_NOCACHE", SDRAM_NOCACHE);
REGION_ALIAS ("REGION_NOCACHE_LOAD", FLEXSPI);
bsp_vector_table_in_start_section = 1;
SECTIONS {
. = imxrt_memory_flexspi_begin;
.flash_config : ALIGN_WITH_INPUT {
KEEP(*(.boot_hdr.conf))
} > FLEXSPI_CONFIG AT > FLEXSPI_CONFIG
.flash_ivt : ALIGN_WITH_INPUT {
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > FLEXSPI_IVT AT > FLEXSPI_IVT
}
INCLUDE linkcmds.armv7m
bsps/arm/imxrt/start/linkcmds.sdram
+23
View File
@@ -0,0 +1,23 @@
INCLUDE linkcmds.memory
REGION_ALIAS ("REGION_START", SDRAM);
REGION_ALIAS ("REGION_VECTOR", SDRAM);
REGION_ALIAS ("REGION_TEXT", SDRAM);
REGION_ALIAS ("REGION_TEXT_LOAD", SDRAM);
REGION_ALIAS ("REGION_RODATA", SDRAM);
REGION_ALIAS ("REGION_RODATA_LOAD", SDRAM);
REGION_ALIAS ("REGION_DATA", SDRAM);
REGION_ALIAS ("REGION_DATA_LOAD", SDRAM);
REGION_ALIAS ("REGION_FAST_TEXT", SDRAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", SDRAM);
REGION_ALIAS ("REGION_FAST_DATA", SDRAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", SDRAM);
REGION_ALIAS ("REGION_BSS", SDRAM);
REGION_ALIAS ("REGION_WORK", SDRAM);
REGION_ALIAS ("REGION_STACK", SDRAM);
REGION_ALIAS ("REGION_NOCACHE", SDRAM_NOCACHE);
REGION_ALIAS ("REGION_NOCACHE_LOAD", SDRAM);
bsp_vector_table_in_start_section = 1;
INCLUDE linkcmds.armv7m
bsps/arm/imxrt/start/mpu-config.c
+75
View File
@@ -0,0 +1,75 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <imxrt/memory.h>
#include <imxrt/mpu-config.h>
#include <rtems/score/armv7m.h>
BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config
imxrt_config_mpu_region [] = {
{
.begin = imxrt_memory_sdram_begin,
.end = imxrt_memory_sdram_end,
.rasr = ARMV7M_MPU_RASR_AP(0x3)
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
.begin = imxrt_memory_ocram_begin,
.end = imxrt_memory_ocram_end,
.rasr = ARMV7M_MPU_RASR_AP(0x3)
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
.begin = imxrt_memory_flexspi_config_begin,
.end = imxrt_memory_flexspi_end,
.rasr = ARMV7M_MPU_RASR_AP(0x3)
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
.begin = imxrt_memory_sdram_nocache_begin,
.end = imxrt_memory_sdram_nocache_end,
.rasr = ARMV7M_MPU_RASR_AP(0x3)
| ARMV7M_MPU_RASR_TEX(0x2)
| ARMV7M_MPU_RASR_ENABLE,
}, {
.begin = imxrt_memory_peripheral_begin,
.end = imxrt_memory_peripheral_end,
.rasr = ARMV7M_MPU_RASR_XN
| ARMV7M_MPU_RASR_AP(0x3)
| ARMV7M_MPU_RASR_TEX(0x2)
| ARMV7M_MPU_RASR_ENABLE,
}, {
.begin = imxrt_memory_null_begin,
.end = imxrt_memory_null_end,
.rasr = ARMV7M_MPU_RASR_XN
| ARMV7M_MPU_RASR_AP(0x0)
| ARMV7M_MPU_RASR_ENABLE,
}
};
BSP_START_DATA_SECTION const size_t imxrt_config_mpu_region_count =
RTEMS_ARRAY_SIZE(imxrt_config_mpu_region);
bsps/arm/shared/pins/imx_iomux.c
+5
View File
@@ -72,6 +72,7 @@
#else /* __rtems__ */
#include <bsp.h>
#include <bsp/fdt.h>
#include <bsp/imx-iomux.h>
#include <rtems/sysinit.h>
#include <errno.h>
#include <libfdt.h>
@@ -163,6 +164,10 @@ imx_iomux_init(void)
node = fdt_node_offset_by_compatible(fdt, -1,
"fsl,imx6ul-iomuxc");
}
if (node < 0) {
node = fdt_node_offset_by_compatible(fdt, -1,
"nxp,imxrt1050-iomuxc");
}
sc = iomux_sc;
sc->regs = imx_get_reg_of_node(fdt, node);
bsps/include/bsp/fatal.h
+16 -1
View File
@@ -157,7 +157,22 @@ typedef enum {
RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE,
/* GRLIB fatal codes */
GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14)
GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14),
/* i.MXRT fatal codes */
IMXRT_FATAL_NO_CONSOLE = BSP_FATAL_CODE_BLOCK(15),
IMXRT_FATAL_LPUART_INVALID_FDT,
IMXRT_FATAL_LPUART_ALLOC_FAILED,
IMXRT_FATAL_LPUART_INSTALL_FAILED,
IMXRT_FATAL_LPSPI_INVALID_FDT,
IMXRT_FATAL_LPSPI_ALLOC_FAILED,
IMXRT_FATAL_LPSPI_HW_INIT_FAILED,
IMXRT_FATAL_LPSPI_REGISTER_FAILED,
IMXRT_FATAL_LPI2C_INVALID_FDT,
IMXRT_FATAL_LPI2C_ALLOC_FAILED,
IMXRT_FATAL_LPI2C_HW_INIT_FAILED,
IMXRT_FATAL_LPI2C_REGISTER_FAILED,
IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE,
} bsp_fatal_code;
RTEMS_NO_RETURN static inline void
spec/build/bsps/arm/imxrt/abi.yml
+20
View File
@@ -0,0 +1,20 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-string: null
- split: null
- env-append: null
build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
- -mthumb
- -mcpu=cortex-m7
- -mfpu=fpv5-d16
- -mfloat-abi=hard
default-by-variant: []
description: |
ABI flags
enabled-by: true
links: []
name: ABI_FLAGS
type: build
spec/build/bsps/arm/imxrt/bspimxrt.yml
+250
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File diff suppressed because it is too large. Load diff
spec/build/bsps/arm/imxrt/linkcmds.yml
+11
View File
@@ -0,0 +1,11 @@
build-type: config-file
content: |
INCLUDE ${IMXRT_DEFAULT_LINKCMDS}
enabled-by: true
install-path: ${BSP_LIBDIR}
links: []
target: linkcmds
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/linkcmdsmemory.yml
+67
View File
@@ -0,0 +1,67 @@
build-type: config-file
content: |
MEMORY {
NULL : ORIGIN = 0x00000000, LENGTH = ${IMXRT_MEMORY_NULL_SIZE:#010x}
ITCM : ORIGIN = ${IMXRT_MEMORY_NULL_SIZE:#010x}, LENGTH = 512k - ${IMXRT_MEMORY_NULL_SIZE:#010x}
DTCM : ORIGIN = 0x20000000, LENGTH = 512k
OCRAM : ORIGIN = 0x20200000, LENGTH = 512k
PERIPHERAL : ORIGIN = 0x40000000, LENGTH = 0x20000000
FLEXSPI_CONFIG : ORIGIN = 0x60000000, LENGTH = ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x}
FLEXSPI_IVT : ORIGIN = 0x60000000 + ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x}, LENGTH = ${IMXRT_MEMORY_FLASH_IVT_SIZE:#010x}
FLEXSPI : ORIGIN = 0x60000000 + ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x} + ${IMXRT_MEMORY_FLASH_IVT_SIZE:#010x}, LENGTH = ${IMXRT_MEMORY_FLEXSPI_FLASH_SIZE:#010x} - ${IMXRT_MEMORY_FLASH_CFG_SIZE:#010x} - ${IMXRT_MEMORY_FLASH_IVT_SIZE:#010x}
FLEXSPI_FIFO : ORIGIN = 0x7F800000, LENGTH = 8M
SDRAM : ORIGIN = ${IMXRT_MEMORY_SDRAM_BASE:#010x}, LENGTH = ${IMXRT_MEMORY_SDRAM_SIZE:#010x} - ${IMXRT_MEMORY_SDRAM_NOCACHE_SIZE:#010x}
SDRAM_NOCACHE : ORIGIN = ${IMXRT_MEMORY_SDRAM_BASE:#010x} + ${IMXRT_MEMORY_SDRAM_SIZE:#010x} - ${IMXRT_MEMORY_SDRAM_NOCACHE_SIZE:#010x}, LENGTH = ${IMXRT_MEMORY_SDRAM_NOCACHE_SIZE:#010x}
}
imxrt_memory_null_begin = ORIGIN (NULL);
imxrt_memory_null_end = ORIGIN (NULL) + LENGTH (NULL);
imxrt_memory_null_size = LENGTH (NULL);
imxrt_memory_itcm_begin = ORIGIN (ITCM);
imxrt_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM);
imxrt_memory_itcm_size = LENGTH (ITCM);
imxrt_memory_dtcm_begin = ORIGIN (DTCM);
imxrt_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM);
imxrt_memory_dtcm_size = LENGTH (DTCM);
imxrt_memory_ocram_begin = ORIGIN (OCRAM);
imxrt_memory_ocram_end = ORIGIN (OCRAM) + LENGTH (OCRAM);
imxrt_memory_ocram_size = LENGTH (OCRAM);
imxrt_memory_peripheral_begin = ORIGIN (PERIPHERAL);
imxrt_memory_peripheral_end = ORIGIN (PERIPHERAL) + LENGTH (PERIPHERAL);
imxrt_memory_peripheral_size = LENGTH (PERIPHERAL);
imxrt_memory_flexspi_config_begin = ORIGIN (FLEXSPI_CONFIG);
imxrt_memory_flexspi_config_end = ORIGIN (FLEXSPI_CONFIG) + LENGTH (FLEXSPI_CONFIG);
imxrt_memory_flexspi_config_size = LENGTH (FLEXSPI_CONFIG);
imxrt_memory_flexspi_ivt_begin = ORIGIN (FLEXSPI_IVT);
imxrt_memory_flexspi_ivt_end = ORIGIN (FLEXSPI_IVT) + LENGTH (FLEXSPI_IVT);
imxrt_memory_flexspi_ivt_size = LENGTH (FLEXSPI_IVT);
imxrt_memory_flexspi_begin = ORIGIN (FLEXSPI);
imxrt_memory_flexspi_end = ORIGIN (FLEXSPI) + LENGTH (FLEXSPI);
imxrt_memory_flexspi_size = LENGTH (FLEXSPI);
imxrt_memory_flexspi_fifo_begin = ORIGIN (FLEXSPI_FIFO);
imxrt_memory_flexspi_fifo_end = ORIGIN (FLEXSPI_FIFO) + LENGTH (FLEXSPI_FIFO);
imxrt_memory_flexspi_fifo_size = LENGTH (FLEXSPI_FIFO);
imxrt_memory_sdram_begin = ORIGIN (SDRAM);
imxrt_memory_sdram_end = ORIGIN (SDRAM) + LENGTH (SDRAM);
imxrt_memory_sdram_size = LENGTH (SDRAM);
imxrt_memory_sdram_nocache_begin = ORIGIN (SDRAM_NOCACHE);
imxrt_memory_sdram_nocache_end = ORIGIN (SDRAM_NOCACHE) + LENGTH (SDRAM_NOCACHE);
imxrt_memory_sdram_nocache_size = LENGTH (SDRAM_NOCACHE);
enabled-by: true
install-path: ${BSP_LIBDIR}
links: []
target: linkcmds.memory
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optlinkcmds.yml
+16
View File
@@ -0,0 +1,16 @@
actions:
- get-string: null
- env-assign: null
build-type: option
default: linkcmds.flexspi
default-by-variant: []
enabled-by: true
format: '{}'
links: []
name: IMXRT_DEFAULT_LINKCMDS
description: |
The default linker command file. Must be linkcmds.sdram or linkcmds.flexspi.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemflashcfgsz.yml
+19
View File
@@ -0,0 +1,19 @@
actions:
- get-integer: null
- env-assign: null
build-type: option
default: 0x1000
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_FLASH_CFG_SIZE
description: |
Size of the flash configuration area at the start of the FlexSPI / SEMC flash
in bytes. Either 4 KByte for FlexSPI NOR / SEMC NOR or 1 Kbyte for most other.
Take a look at the i.MX RT1050 Processor Reference Manual chapter 9.7 "Program
image" for details.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemflashivtsz.yml
+18
View File
@@ -0,0 +1,18 @@
actions:
- get-integer: null
- env-assign: null
build-type: option
default: 0x1000
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_FLASH_IVT_SIZE
description: |
Size of the image vector table, boot data structure, device configuration data
and similar program image header information. Take a look at the i.MX RT1050
Processor Reference Manual chapter 9.7 "Program image" for details.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemflexspisz.yml
+17
View File
@@ -0,0 +1,17 @@
actions:
- get-integer: null
- env-assign: null
- define-unquoted: IMXRT_MEMORY_FLEXSPI_FLASH_SIZE
build-type: option
default: 67108864
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_FLEXSPI_FLASH_SIZE
description: |
Size of the FlexSPI Flash area in bytes.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemnullsz.yml
+17
View File
@@ -0,0 +1,17 @@
actions:
- get-integer: null
- env-assign: null
build-type: option
default: 0x400
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_NULL_SIZE
description: |
Size of the NULL pointer protection area in bytes. This memory area reduces
the size of the ITCM available to the application.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemsdrambase.yml
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@@ -0,0 +1,16 @@
actions:
- get-integer: null
- env-assign: null
build-type: option
default: 0x80000000
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_SDRAM_BASE
description: |
Base address of the SDRAM.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemsdramnocachesz.yml
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actions:
- get-integer: null
- env-assign: null
build-type: option
default: 1048576
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_SDRAM_NOCACHE_SIZE
description: |
Size of the nocache area at the end of the SDRAM in bytes.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
spec/build/bsps/arm/imxrt/optmemsdramsz.yml
+16
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@@ -0,0 +1,16 @@
actions:
- get-integer: null
- env-assign: null
build-type: option
default: 33554432
default-by-variant: []
enabled-by: true
format: '{:#010x}'
links: []
name: IMXRT_MEMORY_SDRAM_SIZE
description: |
Size of the SDRAM in bytes.
type: build
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)