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imx_iomux: Don't set reserved bits in PAD_CTL

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On most i.MX* the upper bits in SW_PAD_CTL are reserved. On some chips,
like the i.MXRT1166, they are a domain write protection. Setting them to
1 can have unexpected side effects.

The device tree uses these bits for some flags. Make sure that they are
not accidentally written to some value.
This commit is contained in:
Christian Mauderer
2023-05-22 09:45:42 +02:00
parent 2fdd1d0246
commit 6f034c18e8
1 changed files with 10 additions and 0 deletions
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bsps/arm/shared/pins/imx_iomux.c
+10
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@@ -307,7 +307,17 @@ int imx_iomux_configure_pins(const void *fdt, uint32_t cfgxref)
WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
iomux_configure_input(sc, cfg->input_reg, cfg->input_val);
if ((cfg->padconf_val & PADCONF_NONE) == 0)
#ifndef __rtems__
WR4(sc, cfg->padconf_reg, cfg->padconf_val);
#else /* __rtems__ */
/*
* Need to mask the flags. On (for example) i.MXRT1166
* they are used for domain write protection. On other
* i.MX* these are Reserved.
*/
WR4(sc, cfg->padconf_reg, cfg->padconf_val
& ~(PADCONF_SION | PADCONF_NONE));
#endif /* __rtems__ */
#ifndef __rtems__
if (bootverbose) {
char name[32];