bsps/riscv: Add Microchip PolarFire SoC BSP variant

The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.

bsps/riscv/riscv/clock/clockdrv.c

@@ -95,6 +95,8 @@ static void riscv_clock_at_tick(riscv_timecounter *tc)
   uint64_t value;
   uint32_t cpu = rtems_scheduler_get_processor();
 
+  cpu = _RISCV_Map_cpu_index_to_hardid(cpu);
+
   clint = tc->clint;
 
   value = clint->mtimecmp[cpu].val_64;
@@ -172,6 +174,8 @@ static void riscv_clock_secondary_action(void *arg)
   uint64_t *cmpval = arg;
   uint32_t cpu = _CPU_SMP_Get_current_processor();
 
+  cpu = _RISCV_Map_cpu_index_to_hardid(cpu);
+
   riscv_clock_clint_init(clint, *cmpval, cpu);
 }
 #endif
@@ -214,7 +218,7 @@ static void riscv_clock_initialize(void)
   cmpval = riscv_clock_read_mtime(&clint->mtime);
   cmpval += interval;
 
-  riscv_clock_clint_init(clint, cmpval, 0);
+  riscv_clock_clint_init(clint, cmpval, RISCV_BOOT_HARTID);
   riscv_clock_secondary_initialization(clint, cmpval, interval);
 
   /* Initialize timecounter */

bsps/riscv/riscv/config/mpfs64imafdc.cfg

@@ -0,0 +1,9 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
+
+LDFLAGS = -Wl,--gc-sections
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections

bsps/riscv/riscv/include/bsp/riscv.h

@@ -34,17 +34,31 @@
 extern "C" {
 #endif
 
+static inline uint32_t _RISCV_Map_hardid_to_cpu_index(uint32_t hardid)
+{
+  return (hardid - RISCV_BOOT_HARTID);
+}
+
+static inline uint32_t _RISCV_Map_cpu_index_to_hardid(uint32_t cpu_index)
+{
+  return (cpu_index + RISCV_BOOT_HARTID);
+}
+
 extern volatile RISCV_CLINT_regs *riscv_clint;
 
 void *riscv_fdt_get_address(const void *fdt, int node);
 
 uint32_t riscv_get_core_frequency(void);
 
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+extern uint32_t riscv_hart_count;
+#else
 #ifdef RTEMS_SMP
 extern uint32_t riscv_hart_count;
 #else
 #define riscv_hart_count 1
 #endif
+#endif
 
 uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
 

bsps/riscv/riscv/irq/irq.c

@@ -136,6 +136,12 @@ static void riscv_clint_init(const void *fdt)
     Per_CPU_Control *cpu;
 
     hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
+#ifdef RTEMS_SMP
+    if (hart_index < RISCV_BOOT_HARTID) {
+      continue;
+    }
+
+    hart_index = _RISCV_Map_hardid_to_cpu_index(hart_index);
     if (hart_index >= rtems_configuration_get_maximum_processors()) {
       continue;
     }
@@ -143,6 +149,15 @@ static void riscv_clint_init(const void *fdt)
     cpu = _Per_CPU_Get_by_index(hart_index);
     cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
     cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];
+#else
+    if (hart_index != RISCV_BOOT_HARTID) {
+      continue;
+    }
+
+    cpu = _Per_CPU_Get_by_index(0);
+    cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
+    cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];
+#endif
   }
 }
 
@@ -183,8 +198,21 @@ static void riscv_plic_init(const void *fdt)
 
   for (i = 0; i < len; i += 8) {
     uint32_t hart_index;
+    uint8_t mie_regs;
+
+    /*
+     * Interrupt enable  registers with 32-bit alignment based on
+     * number of interrupts.
+     */
+    mie_regs =  (ndev + 0x1f) & ~(0x1f);
 
     hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
+#ifdef RTEMS_SMP
+    if (hart_index < RISCV_BOOT_HARTID) {
+      continue;
+    }
+
+    hart_index = _RISCV_Map_hardid_to_cpu_index(hart_index);
     if (hart_index >= rtems_configuration_get_maximum_processors()) {
       continue;
     }
@@ -199,6 +227,28 @@ static void riscv_plic_init(const void *fdt)
     cpu = _Per_CPU_Get_by_index(hart_index);
     cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8];
     cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0];
+
+    for (interrupt_index = 0; interrupt_index < mie_regs; ++interrupt_index) {
+      cpu->cpu_per_cpu.plic_m_ie[interrupt_index] = 0;
+    }
+#else
+    if (hart_index != RISCV_BOOT_HARTID) {
+      continue;
+    }
+
+    interrupt_index = fdt32_to_cpu(val[i / 4 + 1]);
+    if (interrupt_index != RISCV_INTERRUPT_EXTERNAL_MACHINE) {
+      continue;
+    }
+    plic->harts[i / 8].priority_threshold = 0;
+
+    cpu = _Per_CPU_Get_by_index(0);
+    cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8];
+    cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0];
+    for (interrupt_index = 0; interrupt_index < mie_regs; ++interrupt_index) {
+      cpu->cpu_per_cpu.plic_m_ie[interrupt_index] = 0;
+    }
+#endif
   }
 
   cpu = _Per_CPU_Get_by_index(0);
@@ -298,6 +348,7 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
     if (enable != NULL) {
       enable[group] |= bit;
     } else {
+#ifdef RTEMS_SMP
       uint32_t cpu_max;
       uint32_t cpu_index;
 
@@ -313,6 +364,16 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
           enable[group] |= bit;
         }
       }
+#else
+      Per_CPU_Control *cpu;
+
+      cpu = _Per_CPU_Get_by_index(0);
+      enable = cpu->cpu_per_cpu.plic_m_ie;
+
+      if (enable != NULL) {
+        enable[group] |= bit;
+      }
+#endif
     }
 
     rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
@@ -342,6 +403,7 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
     if (enable != NULL) {
       enable[group] &= ~bit;
     } else {
+#ifdef RTEMS_SMP
       uint32_t cpu_max;
       uint32_t cpu_index;
 
@@ -357,6 +419,16 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
           enable[group] &= ~bit;
         }
       }
+#else
+      Per_CPU_Control *cpu;
+
+      cpu = _Per_CPU_Get_by_index(0);
+      enable = cpu->cpu_per_cpu.plic_m_ie;
+
+      if (enable != NULL) {
+        enable[group] &= ~bit;
+      }
+#endif
     }
 
     rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
@@ -414,6 +486,7 @@ rtems_status_code bsp_interrupt_get_affinity(
     enable = riscv_plic_irq_to_cpu[interrupt_index - 1];
 
     if (enable != NULL) {
+#ifdef RTEMS_SMP
       uint32_t cpu_max;
       uint32_t cpu_index;
 
@@ -429,6 +502,14 @@ rtems_status_code bsp_interrupt_get_affinity(
           break;
         }
       }
+#else
+      Per_CPU_Control *cpu;
+
+      cpu = _Per_CPU_Get_by_index(0);
+
+      if (enable == cpu->cpu_per_cpu.plic_m_ie)
+        _Processor_mask_Set(affinity, 0);
+#endif
     } else {
       _Processor_mask_Assign(affinity, _SMP_Get_online_processors());
     }

bsps/riscv/riscv/start/bsp_fatal_halt.c

@@ -41,6 +41,9 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
 #if RISCV_ENABLE_HTIF_SUPPORT != 0
   htif_poweroff();
 #endif
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+  for(;;);
+#endif
 
   fdt = bsp_fdt_get();
   node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0");

bsps/riscv/riscv/start/bspsmp.c

@@ -49,7 +49,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self)
 
 uint32_t _CPU_SMP_Initialize(void)
 {
-  return riscv_hart_count;
+  return riscv_hart_count - RISCV_BOOT_HARTID;
 }
 
 bool _CPU_SMP_Start_processor(uint32_t cpu_index)

bsps/riscv/riscv/start/bspstart.c

@@ -74,6 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node)
   return (void *)(uintptr_t) addr;
 }
 
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+uint32_t riscv_hart_count;
+static uint32_t riscv_hart_phandles[5];
+#else
 #ifdef RTEMS_SMP
 uint32_t riscv_hart_count;
 
@@ -81,6 +85,7 @@ static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS];
 #else
 static uint32_t riscv_hart_phandles[1];
 #endif
+#endif
 
 static void riscv_find_harts(void)
 {
@@ -146,9 +151,13 @@ static void riscv_find_harts(void)
     riscv_hart_phandles[hart_index] = phandle;
   }
 
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+  riscv_hart_count = max_hart_index + 1;
+#else
 #ifdef RTEMS_SMP
   riscv_hart_count = max_hart_index + 1;
 #endif
+#endif
 }
 
 uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
@@ -166,7 +175,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
 
 static uint32_t get_core_frequency(void)
 {
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 || RISCV_ENABLE_MPFS_SUPPORT != 0
   uint32_t node;
   const char *fdt;
   const char *tlclk;
@@ -177,7 +186,13 @@ static uint32_t get_core_frequency(void)
   node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
   tlclk = fdt_getprop(fdt, node, "clock-output-names", &len);
 
-  if (strcmp(tlclk,"tlclk") != 0) {
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+  if (strcmp(tlclk,"tlclk") != 0)
+#endif
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+  if (strcmp(tlclk,"msspllclk") != 0)
+#endif
+  {
     bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE);
   }
 

bsps/riscv/shared/start/start.S

@@ -65,6 +65,8 @@ SYM(_start):
 	LADDR	sp, _ISR_Stack_area_begin
 	LADDR	t2, _ISR_Stack_size
 	csrr	s0, mhartid
+	li      t3, RISCV_BOOT_HARTID
+	sub     s0, s0, t3
 	LADDR	t0, _Per_CPU_Information
 	slli	t1, s0, PER_CPU_CONTROL_SIZE_LOG2
 	add	s1, t0, t1

cpukit/score/cpu/riscv/include/rtems/score/cpu.h

@@ -481,7 +481,7 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void )
     "=&r" ( mhartid )
   );
 
-  return (uint32_t) mhartid;
+  return (uint32_t) mhartid - RISCV_BOOT_HARTID;
 }
 
 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );

cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

@@ -325,7 +325,7 @@ typedef struct {
   uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS];
   uint32_t pending[1024];
   uint32_t enable[16320][32];
-  RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS];
+  RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RISCV_BOOT_HARTID];
 } RISCV_PLIC_regs;
 
 typedef struct {

spec/build/bsps/riscv/optextirqmax.yml

@@ -6,7 +6,10 @@ build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
 default: 64
-default-by-variant: []
+default-by-variant:
+- value: 187
+  variants:
+  - riscv/mpfs64.*
 description: |
   maximum number of external interrupts supported by the BSP (default 64)
 enabled-by: true

spec/build/bsps/riscv/optrambegin.yml

@@ -1,7 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
 - get-integer: null
-- assert-uint32: null
+- assert-uint64: null
 - assert-aligned: 1048576
 - env-assign: null
 - format-and-define: null
@@ -22,6 +22,9 @@ default-by-variant:
 - value: 1073741824
   variants:
   - riscv/griscv
+- value: 68719476736
+  variants:
+  - riscv/mpfs64.*
 description: ''
 enabled-by: true
 format: '{:#010x}'

spec/build/bsps/riscv/optramsize.yml

@@ -1,7 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
 - get-integer: null
-- assert-uint32: null
+- assert-uint64: null
 - assert-aligned: 1048576
 - env-assign: null
 - format-and-define: null
@@ -16,6 +16,9 @@ default-by-variant:
 - value: 16777216
   variants:
   - riscv/griscv
+- value: 268435456
+  variants:
+  - riscv/mpfs64.*
 description: ''
 enabled-by: true
 format: '{:#010x}'

spec/build/bsps/riscv/riscv/abi.yml

@@ -10,6 +10,12 @@ default:
 - -march=rv32imac
 - -mabi=ilp32
 default-by-variant:
+- value:
+  - -march=rv64imafdc
+  - -mabi=lp64d
+  - -mcmodel=medany
+  variants:
+  - riscv/mpfs64imafdc
 - value:
   - -march=rv64imafdc
   - -mabi=lp64d

spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: mpfs64imafdc
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build

spec/build/bsps/riscv/riscv/grp.yml

@@ -44,10 +44,16 @@ links:
   uid: ../../optfdtro
 - role: build-dependency
   uid: ../../optfdtuboot
+- role: build-dependency
+  uid: ../../optdtb
+- role: build-dependency
+  uid: ../../optdtbheaderpath
 - role: build-dependency
   uid: optfrdme310arty
 - role: build-dependency
   uid: opthtif
+- role: build-dependency
+  uid: optmpfs
 - role: build-dependency
   uid: optns16550max
 - role: build-dependency

spec/build/bsps/riscv/riscv/optmpfs.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: false
+default-by-variant:
+- value: true
+  variants:
+  - riscv/mpfs64.*
+description: |
+  enables support Microchip PolarFire SoC if defined to a non-zero value,otherwise it is disabled (disabled by default)
+enabled-by: true
+links: []
+name: RISCV_ENABLE_MPFS_SUPPORT
+type: build

spec/build/bsps/riscv/riscv/optns16550max.yml

@@ -10,6 +10,9 @@ default-by-variant:
 - value: null
   variants:
   - riscv/frdme310arty.*
+- value: 1
+  variants:
+  - riscv/mpfs64.*
 description: |
   maximum number of NS16550 devices supported by the console driver (2 by default)
 enabled-by: true

spec/build/cpukit/cpuopts.yml

@@ -33,6 +33,8 @@ links:
   uid: optinstall
 - role: build-dependency
   uid: optada
+- role: build-dependency
+  uid: optboothartid
 - role: build-dependency
   uid: optbuildlabel
 - role: build-dependency

spec/build/cpukit/optarchbits.yml

@@ -11,6 +11,7 @@ default-by-variant:
 - value:
   - '64'
   variants:
+  - riscv/mpfs64.*
   - riscv/noel64.*
   - riscv/rv64.*
 - value:

spec/build/cpukit/optboothartid.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 0
+default-by-variant:
+- value: 1
+  variants:
+  - riscv/mpfs64.*
+description: |
+  boot hartid (processor number) of risc-v cpu (default 0)
+enabled-by: true
+format: '{}'
+links: []
+name: RISCV_BOOT_HARTID
+type: build

spec/build/cpukit/optsmp.yml

@@ -31,6 +31,7 @@ enabled-by:
 - riscv/griscv
 - riscv/grv32imac
 - riscv/grv32imafdc
+- riscv/mpfs64imafdc
 - riscv/noel32imafd
 - riscv/noel64imac
 - riscv/noel64imafdc