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bsp/stm32h7: remove stm32h7b3i-dk related changes from start system files

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Sponsored-By:	Precidata
This commit is contained in:
Karel Gardas
2022-05-16 10:23:27 +02:00
committed by Sebastian Huber
parent d8017f203e
commit 6b051182a9
4 changed files with 7 additions and 82 deletions
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bsps/arm/stm32h7/start/stm32h7-config-clk.c
-4
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@@ -37,11 +37,7 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = {
| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
.SYSCLKDivider = RCC_SYSCLK_DIV1,
#ifdef STM32H7B3xxQ
.AHBCLKDivider = RCC_HCLK_DIV1,
#else
.AHBCLKDivider = RCC_HCLK_DIV2,
#endif
.APB3CLKDivider = RCC_APB3_DIV2,
.APB1CLKDivider = RCC_APB1_DIV2,
.APB2CLKDivider = RCC_APB2_DIV2,
bsps/arm/stm32h7/start/stm32h7-config-osc.c
-17
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@@ -32,22 +32,6 @@
#include <stm32h7/hal.h>
const RCC_OscInitTypeDef stm32h7_config_oscillator = {
#ifdef STM32H7B3xxQ
.OscillatorType = RCC_OSCILLATORTYPE_HSE,
.HSEState = RCC_HSE_ON,
.HSIState = RCC_HSI_OFF,
.CSIState = RCC_CSI_OFF,
.PLL.PLLState = RCC_PLL_ON,
.PLL.PLLSource = RCC_PLLSOURCE_HSE,
.PLL.PLLM = 12,
.PLL.PLLN = 280,
.PLL.PLLFRACN = 0,
.PLL.PLLP = 2,
.PLL.PLLR = 2,
.PLL.PLLQ = 2,
.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
.PLL.PLLRGE = RCC_PLL1VCIRANGE_1,
#else
.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
.HSEState = RCC_HSE_ON,
@@ -65,5 +49,4 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = {
.PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
.PLL.PLLFRACN = 0
#endif
};
bsps/arm/stm32h7/start/stm32h7-config-per.c
-17
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@@ -32,22 +32,6 @@
#include <stm32h7/hal.h>
const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
#ifdef STM32H7B3xxQ
/* for stm32h7b3i-dk BSP we provide only minimalistic peripheral
configuration just to make available U(S)ARTs working */
.PeriphClockSelection = RCC_PERIPHCLK_USART3
| RCC_PERIPHCLK_USART1,
.PLL2.PLL2M = 24,
.PLL2.PLL2N = 200,
.PLL2.PLL2P = 0,
.PLL2.PLL2Q = 2,
.PLL2.PLL2R = 0,
.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2,
.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM,
.PLL2.PLL2FRACN = 0,
.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
#else
.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
| RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
@@ -75,5 +59,4 @@ const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
.UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
.RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
.RngClockSelection = RCC_RNGCLKSOURCE_HSI48
#endif
};
bsps/arm/stm32h7/start/system_stm32h7xx.c
+7 -44
View File
@@ -51,11 +51,7 @@
#include <bsp/linker-symbols.h>
#endif /* __rtems__ */
#if !defined (HSE_VALUE)
#ifdef STM32H7B3xxQ
#define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
@@ -151,9 +147,9 @@
*/
void SystemInit (void)
{
#if defined (DATA_IN_D2_SRAM) || defined (DATA_IN_CD_AHB_SRAM)
#if defined (DATA_IN_D2_SRAM)
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM || DATA_IN_CD_AHB_SRAM */
#endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
@@ -188,26 +184,6 @@ void SystemInit (void)
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
#endif
#ifdef STM32H7B3xxQ
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x02020200;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x01FF0000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x01010280;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x01010280;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280;
#else
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
@@ -226,7 +202,7 @@ void SystemInit (void)
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
#endif
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
@@ -246,34 +222,25 @@ void SystemInit (void)
}
#endif
#ifndef __rtems__
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
#elif DATA_IN_CD_AHB_SRAM
/* in case of initialized data in CD AHB SRAM, enable the CD AHB SRAM clock */
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
#endif /* DATA_IN_D2_SRAM */
#ifndef __rtems__
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#endif /* DATA_IN_D2_SRAM */
#else /* __rtems__ */
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
RCC->AHB2ENR;
#endif /* __rtems__ */
#ifdef STM32H7B3xxQ
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
#endif
#ifndef __rtems__
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
@@ -287,11 +254,7 @@ void SystemInit (void)
/* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
#ifdef VECT_TAB_SRAM
#ifdef STM32H7B3xxQ
SCB->VTOR = CD_AXISRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal CD AXI-RAM */
#else
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
#endif
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif