sparc: Optimize _ISR_Handler()

Use _Thread_Do_dispatch() instead of _Thread_Dispatch().  Restore the
PSR[EF] state of the interrupted context via new system call
syscall_irqdis_fp in case floating-point support is enabled.

c/src/lib/libbsp/sparc/erc32/startup/spurious.c

@@ -164,6 +164,9 @@ void bsp_spurious_initialize()
         (( trap >= 0x11 ) && ( trap <= 0x1f )) ||
         (( trap >= 0x70 ) && ( trap <= 0x83 )) ||
         ( trap == 0x80 + SPARC_SWTRAP_IRQDIS ) ||
+#if SPARC_HAS_FPU == 1
+        ( trap == 0x80 + SPARC_SWTRAP_IRQDIS_FP ) ||
+#endif
         ( trap == 0x80 + SPARC_SWTRAP_IRQEN ))
       continue;
 

c/src/lib/libbsp/sparc/leon2/startup/spurious.c

@@ -151,6 +151,9 @@ void bsp_spurious_initialize()
         (( trap >= 0x11 ) && ( trap <= 0x1f )) ||
         (( trap >= 0x70 ) && ( trap <= 0x83 )) ||
         ( trap == 0x80 + SPARC_SWTRAP_IRQDIS ) ||
+#if SPARC_HAS_FPU == 1
+        ( trap == 0x80 + SPARC_SWTRAP_IRQDIS_FP ) ||
+#endif
         ( trap == 0x80 + SPARC_SWTRAP_IRQEN ))
       continue;
 

c/src/lib/libbsp/sparc/leon3/startup/spurious.c

@@ -156,6 +156,9 @@ void bsp_spurious_initialize()
         (( trap >= 0x11 ) && ( trap <= 0x1f )) ||
         (( trap >= 0x70 ) && ( trap <= 0x83 )) ||
         ( trap == 0x80 + SPARC_SWTRAP_IRQDIS ) ||
+#if SPARC_HAS_FPU == 1
+        ( trap == 0x80 + SPARC_SWTRAP_IRQDIS_FP ) ||
+#endif
         ( trap == 0x80 + SPARC_SWTRAP_IRQEN ))
       continue;
 

c/src/lib/libbsp/sparc/shared/start/start.S

@@ -207,9 +207,14 @@ SYM(CLOCK_SPEED):
    */
   IRQDIS_TRAP(SYM(syscall_irqdis));             ! 89 IRQ Disable syscall trap
   IRQEN_TRAP(SYM(syscall_irqen));               ! 8A IRQ Enable syscall trap
-
+#if SPARC_HAS_FPU == 1
+  IRQDIS_TRAP(SYM(syscall_irqdis_fp));          ! 8B IRQ disable
+                                                ! and set PSR[EF] syscall trap
+#else
   SOFT_TRAP;                                    ! 8B
+#endif
   SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 8C - 8F
+
   SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 90 - 93
   SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 94 - 97
   SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 98 - 9B

c/src/lib/libcpu/sparc/syscall/syscall.S

@@ -95,6 +95,43 @@ SYM(syscall_irqen):
 	jmp	%l2				! Return to after TA 10.
 	 rett	%l2 + 4
 
+#if SPARC_HAS_FPU == 1
+	/*
+	 *  system call - Interrupt disable and set PSR[EF] according to caller
+	 *                specified %g1
+	 *
+	 *  On entry:
+	 *
+	 *    g1 = the desired PSR[EF] value (from caller)
+	 *    l0 = psr (from trap table)
+	 *    l1 = pc
+	 *    l2 = npc
+	 *    l3 = psr | SPARC_PSR_PIL_MASK
+	 *
+	 *  On exit:
+	 *    g1 = old psr (to user)
+	 */
+
+.align 32				! Align to 32-byte cache-line
+	PUBLIC(syscall_irqdis_fp)
+
+SYM(syscall_irqdis_fp):
+	/*
+	 * We cannot use an intermediate value for operations with the PSR[EF]
+	 * bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
+	 */
+	sethi	%hi(SPARC_PSR_EF_MASK), %l4
+
+	andn	%l3, %l4, %l3			! Clear PSR[EF]
+	and	%g1, %l4, %g1			! Select PSR[EF] only from %g1
+	or	%l3, %g1, %l3			! Set PSR[EF] according to %g1
+	mov	%l3, %psr			! Set PSR. Write delay 3 instr
+	or	%l0, SPARC_PSR_ET_MASK, %g1	! return old PSR with ET=1
+	nop					! PSR write delay
+	jmp	%l2				! Return to after TA 9.
+	 rett	%l2 + 4
+#endif
+
 #if defined(RTEMS_PARAVIRT)
 
         PUBLIC(_SPARC_Get_PSR)

cpukit/score/cpu/sparc/rtems/score/sparc.h

@@ -153,6 +153,9 @@ extern "C" {
 #define SPARC_SWTRAP_SYSCALL 0
 #define SPARC_SWTRAP_IRQDIS 9
 #define SPARC_SWTRAP_IRQEN 10
+#if SPARC_HAS_FPU == 1
+#define SPARC_SWTRAP_IRQDIS_FP 11
+#endif
 
 #ifndef ASM