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added variant to gen68360 BSP

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added genmcf548x BSP
This commit is contained in:
Thomas Doerfler
2008-07-11 10:00:41 +00:00
parent 1898d72d9c
commit 69effbb4e1
31 changed files with 6150 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libbsp/m68k/ChangeLog
+4
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@@ -1,3 +1,7 @@
2008-07-11 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* genmcf548x: added BSP
2008-06-27 Joel Sherrill <joel.sherrill@OARcorp.com>
* acinclude.m4: Regenerated.
c/src/lib/libbsp/m68k/acinclude.m4
+2
View File
@@ -12,6 +12,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
AC_CONFIG_SUBDIRS([gen68340]);;
gen68360 )
AC_CONFIG_SUBDIRS([gen68360]);;
genmcf548x )
AC_CONFIG_SUBDIRS([genmcf548x]);;
idp )
AC_CONFIG_SUBDIRS([idp]);;
mcf5206elite )
c/src/lib/libbsp/m68k/gen68360/ChangeLog
+10
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@@ -1,3 +1,13 @@
2008-07-09 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* Makefile.am, spi/m360_spidrv.c, spi/m360_spidrv.h:
added SPI driver
2008-07-09 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* README:
added pgh360 BSP variant
2008-05-23 Joel Sherrill <joel.sherrill@OARcorp.com>
* console/console.c: Eliminate copies of switches to convert termios
c/src/lib/libbsp/m68k/gen68360/Makefile.am
-1
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@@ -11,7 +11,6 @@ dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
nodist_include_HEADERS = include/bspopts.h
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
c/src/lib/libbsp/m68k/gen68360/README
+11
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@@ -29,6 +29,8 @@
# can be used with the Arnewsh SBC360 card.
# - If the preprocessor symbol M68360_ATLAS_HSB is defined,
# the BSP is compiled for an Atlas HSB card.
# - If the preprocessor symbol M68360_IMD_PGH is defined,
# the BSP is compiled for an IMD PGH360 card.
# - Otherwise, the BSP is compiled for a generic 68360 system
# as described in Chapter 9 of the MC68360 User's Manual. This
# version works with the Atlas ACE360 card.
@@ -39,6 +41,7 @@ BOARD: Generic 68360 as described in Motorola MC68360 User's Manual
BOARD: Atlas Computer Equipment Inc. High Speed Bridge (HSB)
BOARD: Atlas Computer Equipment Inc. Advanced Communication Engine (ACE)
BOARD: Arnewsh SBC360 68040/68360 card
BOARD: IMD PGH Board (custom)
BUS: none
CPU FAMILY: Motorola CPU32+, Motorola 68040
COPROCESSORS: none
@@ -83,6 +86,13 @@ bus width: 8-bit PROM/FLASH, 32-bit DRAM
ROM: To 1 MByte, 180 nsec (3 wait states), chip select 0
RAM: 4 or 16 MBytes of 60 nsec parity DRAM (1Mx36) to RAS1*/CAS1*
Board description (IMD PGH)
---------------------------
clock rate: 25 MHz
bus width: 8-bit PROM/FLASH, 32-bit DRAM
ROM: 512KByte, 180 nsec (3 wait states), chip select 0
RAM: 16 MBytes of 60 nsec no-parity DRAM (1Mx32) to RAS1*/CAS1*
Host System
-----------
OPENSTEP 4.2 (Intel and Motorola), Solaris 2.5, Linux 2.0.29
@@ -292,3 +302,4 @@ The board support package has been tested with:
Arnewsh Inc.
P.O. Box 270352
Fort Collins, CO 80527-0352
A custom 68360 board (PGH360) produced by IMD
c/src/lib/libbsp/m68k/gen68360/include/bsp.h
+23
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@@ -90,6 +90,8 @@ void *M360AllocateBufferDescriptors( int count );
void *M360AllocateRiscTimers( int count );
extern char M360DefaultWatchdogFeeder;
extern int m360_clock_rate; /* BRG clock rate, defined in console.c */
m68k_isr_entry set_vector(
rtems_isr_entry handler,
rtems_vector_number vector,
@@ -102,6 +104,7 @@ m68k_isr_entry set_vector(
extern char _RamBase[];
extern char _HeapSize[];
/*
* Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB)
*/
@@ -111,6 +114,26 @@ extern char _HeapSize[];
#define ATLASHSB_LED4 0x20010004L
#define ATLASHSB_ROM_U6 0xFF080000L /* U6 flash ROM socket */
/*
* definitions for PGH360 board
*/
#if defined(PGH360)
/*
* logical SPI addresses of SPI slaves available
*/
#define PGH360_SPI_ADDR_EEPROM 0
#define PGH360_SPI_ADDR_DISP4_DATA 1
#define PGH360_SPI_ADDR_DISP4_CTRL 2
/*
* Port B bit locations of SPI slave selects
*/
#define PGH360_PB_SPI_DISP4_RS_MSK (1<<15)
#define PGH360_PB_SPI_DISP4_CE_MSK (1<<14)
#define PGH360_PB_SPI_EEP_CE_MSK (1<< 0)
#endif /* defined(PGH360) */
#ifdef __cplusplus
}
#endif
c/src/lib/libbsp/m68k/gen68360/spi/m360_spi.c
+852
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File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/m68k/gen68360/spi/m360_spi.h
+146
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@@ -0,0 +1,146 @@
/*===============================================================*\
| Project: RTEMS support for MC68360 |
+-----------------------------------------------------------------+
| Copyright (c) 2008 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| this file contains the MC68360 SPI driver declarations |
\*===============================================================*/
#ifndef _M360_SPIDRV_H
#define _M360_SPIDRV_H
#include <rtems/m68k/m68360.h>
#include <rtems/libi2c.h>
#include <rtems/irq.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct m360_spi_softc {
int initialized;
rtems_id irq_sema_id;
rtems_isr_entry old_handler;
m360BufferDescriptor_t *rx_bd;
m360BufferDescriptor_t *tx_bd;
} m360_spi_softc_t ;
typedef struct {
rtems_libi2c_bus_t bus_desc;
m360_spi_softc_t softc;
} m360_spi_desc_t;
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
rtems_status_code m360_spi_init
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| initialize the driver |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
rtems_libi2c_bus_t *bh /* bus specifier structure */
);
/*-------------------------------------------------------------------------*\
| Return Value: |
| o = ok or error code |
\*=========================================================================*/
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
int m360_spi_read_bytes
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| receive some bytes from SPI device |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
rtems_libi2c_bus_t *bh, /* bus specifier structure */
unsigned char *buf, /* buffer to store bytes */
int len /* number of bytes to receive */
);
/*-------------------------------------------------------------------------*\
| Return Value: |
| number of bytes received or (negative) error code |
\*=========================================================================*/
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
int m360_spi_write_bytes
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| send some bytes to SPI device |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
rtems_libi2c_bus_t *bh, /* bus specifier structure */
unsigned char *buf, /* buffer to send */
int len /* number of bytes to send */
);
/*-------------------------------------------------------------------------*\
| Return Value: |
| number of bytes sent or (negative) error code |
\*=========================================================================*/
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
rtems_status_code m360_spi_set_tfr_mode
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| set SPI to desired baudrate/clock mode/character mode |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
rtems_libi2c_bus_t *bh, /* bus specifier structure */
const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */
);
/*-------------------------------------------------------------------------*\
| Return Value: |
| rtems_status_code |
\*=========================================================================*/
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
int m360_spi_ioctl
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| perform selected ioctl function for SPI |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
rtems_libi2c_bus_t *bh, /* bus specifier structure */
int cmd, /* ioctl command code */
void *arg /* additional argument array */
);
/*-------------------------------------------------------------------------*\
| Return Value: |
| rtems_status_code |
\*=========================================================================*/
#ifdef __cplusplus
}
#endif
#endif /* _M360_SPIDRV_H */
c/src/lib/libbsp/m68k/gen68360/spi/mc68360_spidrv.c
+627
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File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
+175
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@@ -14,6 +14,13 @@
#include <bsp.h>
#include <rtems/m68k/m68360.h>
/*
* Declare the m360 structure here for the benefit of the debugger
*/
volatile m360_t m360;
/*
* Send a command to the CPM RISC processer
*/
@@ -335,6 +342,174 @@ void _Init68360 (void)
* BCLRO* arbitration level 3
*/
#elif defined(PGH360)
/*
* Step 6: Is this a power-up reset?
* For now we just ignore this and do *all* the steps
* Someday we might want to:
* if (Hard, Loss of Clock, Power-up)
* Do all steps
* else if (Double bus fault, watchdog or soft reset)
* Skip to step 12
* else (must be a CPU32+ reset command)
* Skip to step 14
*/
/*
* Step 7: Deal with clock synthesizer
* HARDWARE:
* Change if you're not using an external 25 MHz oscillator.
*/
m360.clkocr = 0x8e; /* No more writes, CLKO1=1/3, CLKO2=off */
/*
* adjust crystal to average between 4.19 MHz and 4.00 MHz
* reprogram pll
*/
m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
/* LPSTOP slowdown, PLL /128*??? */
m360.cdvcr = 0x8000; /* No more writes, no clock division */
/*
* Step 8: Initialize system protection
* Enable watchdog
* Watchdog causes system reset
* 128 sec. watchdog timeout
* Enable double bus fault monitor
* Enable bus monitor external
* 128 clocks for external timeout
*/
m360.sypcr = 0xEF;
/*
* also initialize the SWP bit in PITR to 1
*/
m360.pitr |= 0x0200;
/*
* and trigger SWSR twice to ensure, that interval starts right now
*/
m360.swsr = 0x55;
m360.swsr = 0xAA;
m360.swsr = 0x55;
m360.swsr = 0xAA;
/*
* Step 9: Clear parameter RAM and reset communication processor module
*/
for (i = 0 ; i < 192 ; i += sizeof (long)) {
*((long *)((char *)&m360 + 0xC00 + i)) = 0;
*((long *)((char *)&m360 + 0xD00 + i)) = 0;
*((long *)((char *)&m360 + 0xE00 + i)) = 0;
*((long *)((char *)&m360 + 0xF00 + i)) = 0;
}
M360ExecuteRISC (M360_CR_RST);
/*
* Step 10: Write PEPAR
* SINTOUT not used (CPU32+ mode)
* CF1MODE=00 (CONFIG1 input)
* IPIPE1
* WE0-3
* OE* output
* CAS2* / CAS3*
* CAS0* / CAS1*
* CS7*
* AVEC*
* HARDWARE:
* Change if you are using a different memory configuration
* (static RAM, external address multiplexing, etc).
*/
m360.pepar = 0x0080;
/*
* Step 11: Remap Chip Select 0 (CS0*), set up GMR
* no DRAM support
* HARDWARE:
* Change if you are using a different memory configuration
*/
m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN | M360_GMR_RCYC(0) |
M360_GMR_PGS(6) | M360_GMR_DPS_32BIT | M360_GMR_DWQ |
M360_GMR_GAMX;
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
M360_MEMC_BR_V;
m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
M360_MEMC_OR_8BIT;
/*
* Step 12: Initialize the system RAM
* Set up option/base registers
* 16 MB DRAM
* 1 wait state
* HARDWARE:
* Change if you are using a different memory configuration
* NOTE: no Page mode possible for EDO RAMs (?)
*/
ramSize = 16 * 1024 * 1024;
m360.memc[7].or = M360_MEMC_OR_TCYC(1) | M360_MEMC_OR_16MB |
M360_MEMC_OR_FCMC(0) | /* M360_MEMC_OR_PGME | */
M360_MEMC_OR_32BIT | M360_MEMC_OR_DRAM;
m360.memc[7].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
/*
* FIXME: here we should wait for 8 refresh cycles...
*/
/*
* Step 12a: test the ram, if wanted
* FIXME: when do we call this?
* -> only during firmware execution
* -> perform intesive test only on request
* -> ensure, that results are stored properly
*/
#if 0 /* FIXME: activate RAM tests again */
{
void *ram_base, *ram_end, *code_loc;
extern char ramtest_start,ramtest_end;
ram_base = &ramtest_start;
ram_end = &ramtest_end;
code_loc = (void *)ramtest_exec;
if ((ram_base < ram_end) &&
!((ram_base <= code_loc) && (code_loc < ram_end))) {
ramtest_exec(ram_base,ram_end);
}
}
#endif
/*
* Step 13: Copy the exception vector table to system RAM
*/
m68k_get_vbr (vbr);
for (i = 0; i < 256; ++i)
M68Kvec[i] = vbr[i];
m68k_set_vbr (M68Kvec);
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)
* Disable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register):
* SCC1 requests at SCCa position
* SCC2 requests at SCCb position
* SCC3 requests at SCCc position
* SCC4 requests at SCCd position
* Interrupt request level 4
* Maintain original priority order
* Vector base 128
* SCCs priority grouped at top of table
*/
m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128);
/*
* Step 15: Set module configuration register
* Disable timers during FREEZE
* Enable bus monitor during FREEZE
* BCLRO* arbitration level 3
* No show cycles
* User/supervisor access
* Bus clear interupt service level 7
* SIM60 interrupt sources higher priority than CPM
*/
m360.mcr = 0x4C7F;
#elif (defined (GEN68360_WITH_SRAM))
/*
***************************************************
c/src/lib/libbsp/m68k/genmcf548x/ChangeLog
+14
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@@ -0,0 +1,14 @@
2008-07-10 Peter Rasmussen <peter.rasmussen@embedded-brains.de>
* Makefile.am, preinstall.am,
bsp_specs, ChangeLog,
README,
clock/clock.c,
console/console.c,
include/bsp.h,
include/coverhd.h, include/tm27.h,
network/network.c,
start/start.S,
startup/bspclean.c,
startup/bspstart.c, startup/init548x.c,
startup/linkcmds, startup/linkcmds.m5484FireEngine.flash: New files.
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
+73
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@@ -0,0 +1,73 @@
##
## $Id$
##
ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
nodist_include_HEADERS = include/bspopts.h
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
include_HEADERS += include/coverhd.h
EXTRA_DIST = start/start.S
start.$(OBJEXT): start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds
noinst_PROGRAMS += startup.rel
startup_rel_SOURCES = startup/bspclean.c \
../../shared/bsplibc.c ../../shared/bsppost.c \
../../m68k/shared/m68kpretaskinghook.c \
startup/init548x.c startup/bspstart.c \
../../shared/bootcard.c \
../../shared/sbrk.c ../../m68k/shared/setvec.c \
../../shared/gnatinstallhandler.c
startup_rel_CPPFLAGS = $(AM_CPPFLAGS)
startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += clock.rel
clock_rel_SOURCES = clock/clock.c
clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += console.rel
console_rel_SOURCES = console/console.c
console_rel_CPPFLAGS = $(AM_CPPFLAGS)
console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
noinst_PROGRAMS += timer.rel
timer_rel_SOURCES = timer/timer.c
timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
if HAS_NETWORKING
network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
noinst_PROGRAMS += network.rel
network_rel_SOURCES = network/network.c
network_rel_CPPFLAGS = $(AM_CPPFLAGS) \
$(network_CPPFLAGS)
network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
endif
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES =
libbsp_a_LIBADD = startup.rel clock.rel console.rel timer.rel
if HAS_NETWORKING
libbsp_a_LIBADD += network.rel
endif
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/misc.rel
include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../../automake/local.am
c/src/lib/libbsp/m68k/genmcf548x/README
+180
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@@ -0,0 +1,180 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: README |
+-----------------------------------------------------------------+
| This is the README for the generic MCF548x BSP. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
Description: Generic mcf548x BSP
============
CPU: MCF548x, 200MHz
XLB: 100 MHz, which is the main clock for all onchip peripherals
RAM: 64M (m5484FireEngine)
Boot-Flash: 2M (m5484FireEngine)
Code-Flash: 16M (m5484FireEngine)
Core-SRAM: 8K
Core-SysRAM: 32K
The genmcf548x supports the Fresscale m5484FireEngine EVB.
ACKNOWLEDGEMENTS:
=================
This BSP is based on the
av5282 BSP
and the work of
D. Peter Siddons
Brett Swimley
Jay Monkman
Eric Norum
Mike Bertosh
BSP INFO:
=========
BSP NAME: genmcf548x
BOARD: m5484FireEngine (freescale),
CPU FAMILY: ColdFire 548x
CPU: MCF5484
FPU: MCF548x FPU, context switch supported by RTEMS multitasking
EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context)
PERIPHERALS
===========
TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose)
RESOLUTION: System tick 10 millieconds (via SLT0)
SERIAL PORTS: Internal PSC 0-3
NETWORKING: Internal 10/100MHz FEC (not supported yet)
DRIVER INFORMATION
==================
CLOCK DRIVER: SLT0
TIMER DRIVER: SLT1 (diagnostics)
TTY DRIVER: PSC0-3
STDIO
=====
PORT: PSC0 (UART mode) terminal
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
MODES: Interrupt driven (polled mode alternatively)
Memory map as set up by BSP initialization
m5484FireEngine:
+--------------------------------------------------+
0000 0000 | 64 MByte SDRAM (external) | 03FF FFFF
. .
. .
. .
m5484FireEngine:
| | 0FFF FFFF
+--------------------------------------------------+
1000 0000 | internal per. registers via MBAR | 1003 FFFF
. .
. .
. .
| |
+--------------------------------------------------+
2000 0000 | 8K core SRAM (internal) | 2000 1FFF
. .
. .
. .
m5484FireEngine:
| |
+--------------------------------------------------+
E000 0000 | 16M code flash (external) | E0FF FFFF
. .
. .
. .
| |
+--------------------------------------------------+
FF80 0000 | External 8 MByte Flash memory | FF9F FFFF
. .
. .
. .
| | FFFF FFFF
+--------------------------------------------------+
============================================================================
Interrupt map
+-----+-----------------------------------------------------------------------+
| | PRIORITY |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
|LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 7 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 6 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 5 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 4 | | | | | | | | SLT0 |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 3 | PSC 0 | PSC 1 | PSC 2 | PSC 3 | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 2 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
============================================================================
TIMING TESTS
**************************
tbd.
c/src/lib/libbsp/m68k/genmcf548x/aclocal.m4
Vendored
+940
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c/src/lib/libbsp/m68k/genmcf548x/bsp_specs
+13
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@@ -0,0 +1,13 @@
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s}}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
c/src/lib/libbsp/m68k/genmcf548x/clock/clock.c
+104
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@@ -0,0 +1,104 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: clock.c |
+-----------------------------------------------------------------+
| The file contains the clock driver code of generic MCF548x BSP. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
/*
* Use first slice timer (SLT0) as the system clock.
*
*/
#include <rtems.h>
#include <bsp.h>
#include <mcf548x/mcf548x.h>
/*
* Use SLT 0
*/
#define CLOCK_VECTOR (64+54)
/*
* Periodic interval timer interrupt handler
*/
#define Clock_driver_support_at_tick() \
do { \
MCF548X_SLT_SSR0 = MCF548X_SLT_SSR_ST; \
} while (0) \
/*
* Attach clock interrupt handler
*/
#define Clock_driver_support_install_isr( _new, _old ) \
do { \
_old = (rtems_isr_entry)set_vector(_new, CLOCK_VECTOR, 1); \
} while(0)
/*
* Turn off the clock
*/
#define Clock_driver_support_shutdown_hardware() \
do { \
MCF548X_SLT_SCR0 &= ~(MCF548X_SLT_SCR_TEN | MCF548X_SLT_SCR_RUN | MCF548X_SLT_SCR_IEN); \
} while(0)
/*
* Set up the clock hardware
*
* We need to have 1 interrupt every 10,000 microseconds
* XLB clock 100 MHz / MCF548X_SLT_SLTCNT0 = XLB clock/100
*/
#define Clock_driver_support_initialize_hardware() \
do { \
int level; \
MCF548X_INTC_ICR54 = MCF548X_INTC_ICRn_IL(SLT0_IRQ_LEVEL) | \
MCF548X_INTC_ICRn_IP(SLT0_IRQ_PRIORITY); \
rtems_interrupt_disable( level ); \
MCF548X_INTC_IMRH &= ~(MCF548X_INTC_IMRH_INT_MASK54 | \
MCF548X_INTC_IMRL_MASKALL); \
rtems_interrupt_enable( level ); \
MCF548X_SLT_SLTCNT0 = get_CPU_clock_speed()/100; \
MCF548X_SLT_SCR0 |= (MCF548X_SLT_SCR_TEN | MCF548X_SLT_SCR_RUN | MCF548X_SLT_SCR_IEN); \
} while (0)
#include "../../../shared/clockdrv_shell.c"
c/src/lib/libbsp/m68k/genmcf548x/configure.ac
+29
View File
@@ -0,0 +1,29 @@
## Process this file with autoconf to produce a configure script.
##
## $Id$
AC_PREREQ(2.60)
AC_INIT([rtems-c-src-lib-libbsp-m68k-genmcf548x],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.10])
RTEMS_BSP_CONFIGURE
RTEMS_PROG_CC_FOR_TARGET
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET([BSP_CPU_CLOCK_SPEED],[m5484FireEngine],[100000000])
RTEMS_BSPOPTS_SET([BSP_CPU_CLOCK_SPEED],[*],[100000000])
RTEMS_BSPOPTS_HELP([BSP_CPU_CLOCK_SPEED],
[Use a clock speed of 100000000 for the m5484FireEngine board])
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile])
AC_OUTPUT
c/src/lib/libbsp/m68k/genmcf548x/console/console.c
+886
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h
+136
View File
@@ -0,0 +1,136 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: bsp.h |
+-----------------------------------------------------------------+
| The file contains the BSP header of generic MCF548x BSP. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
#ifndef __GENMCF548X_BSP_H
#define __GENMCF548X_BSP_H
#ifdef __cplusplus
extern "C" {
#endif
#include <bspopts.h>
#include <rtems.h>
#include <rtems/iosupp.h>
#include <rtems/console.h>
#include <rtems/clockdrv.h>
#include <rtems/iosupp.h>
#include <rtems/bspIo.h>
/***************************************************************************/
/** Hardware data structure headers **/
#include <mcf548x/mcf548x.h>
/***************************************************************************/
/** Network driver configuration **/
struct rtems_bsdnet_ifconfig;
extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching );
#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach
/***************************************************************************/
/** User Definable configuration **/
/* define which port the console should use - all other ports are then defined as general purpose */
#define CONSOLE_PORT 0
#define RAM_END 0x4000000 /* 64 MB */
/* externals */
/* constants */
/* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration;
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/* functions */
uint32_t get_CPU_clock_speed(void);
void bsp_cleanup(void);
m68k_isr_entry set_vector(
rtems_isr_entry handler,
rtems_vector_number vector,
int type
);
/*
* Interrupt assignments
* Highest-priority listed first
*/
#define FEC_IRQ_LEVEL 4
#define FEC_IRQ_RX_PRIORITY 7
#define FEC_IRQ_TX_PRIORITY 6
#define SLT0_IRQ_LEVEL 4
#define SLT0_IRQ_PRIORITY 0
#define PSC0_IRQ_LEVEL 3
#define PSC0_IRQ_PRIORITY 7
#define PSC1_IRQ_LEVEL 3
#define PSC1_IRQ_PRIORITY 6
#define PSC2_IRQ_LEVEL 3
#define PSC2_IRQ_PRIORITY 5
#define PSC3_IRQ_LEVEL 3
#define PSC3_IRQ_PRIORITY 4
#ifdef __cplusplus
}
#endif
#endif
c/src/lib/libbsp/m68k/genmcf548x/include/bspopts.h.in
+19
View File
@@ -0,0 +1,19 @@
/* include/bspopts.h.in. Generated from configure.ac by autoheader. */
/* Use a clock speed of 100000000 for the m5484FireEngine board */
#undef BSP_CPU_CLOCK_SPEED
/* Define to the address where bug reports for this package should be sent. */
#undef PACKAGE_BUGREPORT
/* Define to the full name of this package. */
#undef PACKAGE_NAME
/* Define to the full name and version of this package. */
#undef PACKAGE_STRING
/* Define to the one symbol short name of this package. */
#undef PACKAGE_TARNAME
/* Define to the version of this package. */
#undef PACKAGE_VERSION
c/src/lib/libbsp/m68k/genmcf548x/include/coverhd.h
+105
View File
@@ -0,0 +1,105 @@
/* coverhd.h
*
* This include file has defines to represent the overhead associated
* with calling a particular directive from C. These are used in the
* Timing Test Suite to ignore the overhead required to pass arguments
* to directives. On some CPUs and/or target boards, this overhead
* is significant and makes it difficult to distinguish internal
* RTEMS execution time from that used to call the directive.
* This file should be updated after running the C overhead timing
* test. Once this update has been performed, the RTEMS Time Test
* Suite should be rebuilt to account for these overhead times in the
* timing results.
*
* NOTE: If these are all zero, then the times reported include
* all calling overhead including passing of arguments.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef __COVERHD_h
#define __COVERHD_h
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0
#define CALLING_OVERHEAD_TASK_CREATE 0
#define CALLING_OVERHEAD_TASK_IDENT 0
#define CALLING_OVERHEAD_TASK_START 0
#define CALLING_OVERHEAD_TASK_RESTART 0
#define CALLING_OVERHEAD_TASK_DELETE 0
#define CALLING_OVERHEAD_TASK_SUSPEND 0
#define CALLING_OVERHEAD_TASK_RESUME 0
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0
#define CALLING_OVERHEAD_TASK_MODE 0
#define CALLING_OVERHEAD_TASK_GET_NOTE 0
#define CALLING_OVERHEAD_TASK_SET_NOTE 0
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0
#define CALLING_OVERHEAD_INTERRUPT_CATCH 0
#define CALLING_OVERHEAD_CLOCK_GET 1
#define CALLING_OVERHEAD_CLOCK_SET 1
#define CALLING_OVERHEAD_CLOCK_TICK 0
#define CALLING_OVERHEAD_TIMER_CREATE 0
#define CALLING_OVERHEAD_TIMER_IDENT 0
#define CALLING_OVERHEAD_TIMER_DELETE 0
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1
#define CALLING_OVERHEAD_TIMER_RESET 0
#define CALLING_OVERHEAD_TIMER_CANCEL 0
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0
#define CALLING_OVERHEAD_EVENT_SEND 0
#define CALLING_OVERHEAD_EVENT_RECEIVE 0
#define CALLING_OVERHEAD_SIGNAL_CATCH 0
#define CALLING_OVERHEAD_SIGNAL_SEND 0
#define CALLING_OVERHEAD_PARTITION_CREATE 0
#define CALLING_OVERHEAD_PARTITION_IDENT 0
#define CALLING_OVERHEAD_PARTITION_DELETE 0
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0
#define CALLING_OVERHEAD_REGION_CREATE 0
#define CALLING_OVERHEAD_REGION_IDENT 0
#define CALLING_OVERHEAD_REGION_DELETE 0
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0
#define CALLING_OVERHEAD_PORT_CREATE 0
#define CALLING_OVERHEAD_PORT_IDENT 0
#define CALLING_OVERHEAD_PORT_DELETE 0
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
#define CALLING_OVERHEAD_IO_INITIALIZE 0
#define CALLING_OVERHEAD_IO_OPEN 0
#define CALLING_OVERHEAD_IO_CLOSE 0
#define CALLING_OVERHEAD_IO_READ 0
#define CALLING_OVERHEAD_IO_WRITE 0
#define CALLING_OVERHEAD_IO_CONTROL 0
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0
#endif
c/src/lib/libbsp/m68k/genmcf548x/include/tm27.h
+29
View File
@@ -0,0 +1,29 @@
/*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Stuff for Time Test 27
* Don't bother with hardware -- just use a software-interrupt
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 )
#define Cause_tm27_intr() asm volatile ("trap #3");
#define Clear_tm27_intr() /* empty */
#define Lower_tm27_intr() /* empty */
#endif
c/src/lib/libbsp/m68k/genmcf548x/network/network.c
+20
View File
@@ -0,0 +1,20 @@
#include <bsp.h>
#include <stdio.h>
#include <errno.h>
#include <stdarg.h>
#include <string.h>
#include <rtems.h>
#include <rtems/error.h>
#include <rtems/rtems_bsdnet.h>
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
c/src/lib/libbsp/m68k/genmcf548x/preinstall.am
+58
View File
@@ -0,0 +1,58 @@
## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
all-local: $(TMPINSTALL_FILES)
TMPINSTALL_FILES =
CLEANFILES = $(TMPINSTALL_FILES)
all-am: $(PREINSTALL_FILES)
PREINSTALL_FILES =
CLEANFILES += $(PREINSTALL_FILES)
$(PROJECT_LIB)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_LIB)
@: > $(PROJECT_LIB)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
$(PROJECT_INCLUDE)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)
@: > $(PROJECT_INCLUDE)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
c/src/lib/libbsp/m68k/genmcf548x/start/start.S
+436
View File
@@ -0,0 +1,436 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: start.S |
+-----------------------------------------------------------------+
| The file contains the assembly part of MCF548x init code |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
/*===============================================================*\
| Includes |
\*===============================================================*/
#include <rtems/asm.h>
/*===============================================================*\
| External references |
\*===============================================================*/
.extern __MBAR
.extern _CoreSramBase0
.extern _CoreSramBase1
.extern _CoreSramSize1
.extern mcf548x_init
.extern boot_card
.extern _SpInit
.extern _InitPc
/*===============================================================*\
| Global symbols |
\*===============================================================*/
.global interrupt_vector_table
.global spurious_int_count
.global start
/*===============================================================*\
| Exception Table |
\*===============================================================*/
.section ".vectors","ax" /* begin of vectors section */
PUBLIC (InterruptVectorTable)
SYM(InterruptVectorTable):
INITSP: .long _SpInit /* Initial SP */
INITPC: .long _InitPc /* Initial PC */
vector002: .long asm_default_interrupt /* Access Error */
vector003: .long asm_default_interrupt /* Address Error */
vector004: .long asm_default_interrupt /* Illegal Instruction */
vector005: .long asm_default_interrupt /* Reserved */
vector006: .long asm_default_interrupt /* Reserved */
vector007: .long asm_default_interrupt /* Reserved */
vector008: .long asm_default_interrupt /* Privilege Violation */
vector009: .long asm_default_interrupt /* Trace */
vector010: .long asm_default_interrupt /* Unimplemented A-Line */
vector011: .long asm_default_interrupt /* Unimplemented F-Line */
vector012: .long asm_default_interrupt /* Debug Interrupt */
vector013: .long asm_default_interrupt /* Reserved */
vector014: .long asm_default_interrupt /* Format Error */
vector015: .long asm_default_interrupt /* Unitialized Int. */
vector016: .long asm_default_interrupt /* Reserved */
vector017: .long asm_default_interrupt /* Reserved */
vector018: .long asm_default_interrupt /* Reserved */
vector019: .long asm_default_interrupt /* Reserved */
vector020: .long asm_default_interrupt /* Reserved */
vector021: .long asm_default_interrupt /* Reserved */
vector022: .long asm_default_interrupt /* Reserved */
vector023: .long asm_default_interrupt /* Reserved */
vector024: .long asm_spurious_interrupt /* Spurious Interrupt */
vector025: .long asm_default_interrupt /* Autovector Level 1 */
vector026: .long asm_default_interrupt /* Autovector Level 2 */
vector027: .long asm_default_interrupt /* Autovector Level 3 */
vector028: .long asm_default_interrupt /* Autovector Level 4 */
vector029: .long asm_default_interrupt /* Autovector Level 5 */
vector030: .long asm_default_interrupt /* Autovector Level 6 */
vector031: .long asm_default_interrupt /* Autovector Level 7 */
vector032: .long asm_default_interrupt /* TRAP #0 */
vector033: .long asm_default_interrupt /* TRAP #1 */
vector034: .long asm_default_interrupt /* TRAP #2 */
vector035: .long asm_default_interrupt /* TRAP #3 */
vector036: .long asm_default_interrupt /* TRAP #4 */
vector037: .long asm_default_interrupt /* TRAP #5 */
vector038: .long asm_default_interrupt /* TRAP #6 */
vector039: .long asm_default_interrupt /* TRAP #7 */
vector040: .long asm_default_interrupt /* TRAP #8 */
vector041: .long asm_default_interrupt /* TRAP #9 */
vector042: .long asm_default_interrupt /* TRAP #10 */
vector043: .long asm_default_interrupt /* TRAP #11 */
vector044: .long asm_default_interrupt /* TRAP #12 */
vector045: .long asm_default_interrupt /* TRAP #13 */
vector046: .long asm_default_interrupt /* TRAP #14 */
vector047: .long asm_default_interrupt /* TRAP #15 */
vector048: .long asm_default_interrupt /* Reserved */
vector049: .long asm_default_interrupt /* Reserved */
vector050: .long asm_default_interrupt /* Reserved */
vector051: .long asm_default_interrupt /* Reserved */
vector052: .long asm_default_interrupt /* Reserved */
vector053: .long asm_default_interrupt /* Reserved */
vector054: .long asm_default_interrupt /* Reserved */
vector055: .long asm_default_interrupt /* Reserved */
vector056: .long asm_default_interrupt /* Reserved */
vector057: .long asm_default_interrupt /* Reserved */
vector058: .long asm_default_interrupt /* Reserved */
vector059: .long asm_default_interrupt /* Reserved */
vector060: .long asm_default_interrupt /* Reserved */
vector061: .long asm_default_interrupt /* Reserved */
vector062: .long asm_default_interrupt /* Reserved */
vector063: .long asm_default_interrupt /* Reserved */
vector064: .long asm_default_interrupt
vector065: .long asm_default_interrupt
vector066: .long asm_default_interrupt
vector067: .long asm_default_interrupt
vector068: .long asm_default_interrupt
vector069: .long asm_default_interrupt
vector070: .long asm_default_interrupt
vector071: .long asm_default_interrupt
vector072: .long asm_default_interrupt
vector073: .long asm_default_interrupt
vector074: .long asm_default_interrupt
vector075: .long asm_default_interrupt
vector076: .long asm_default_interrupt
vector077: .long asm_default_interrupt
vector078: .long asm_default_interrupt
vector079: .long asm_default_interrupt
vector080: .long asm_default_interrupt
vector081: .long asm_default_interrupt
vector082: .long asm_default_interrupt
vector083: .long asm_default_interrupt
vector084: .long asm_default_interrupt
vector085: .long asm_default_interrupt
vector086: .long asm_default_interrupt
vector087: .long asm_default_interrupt
vector088: .long asm_default_interrupt
vector089: .long asm_default_interrupt
vector090: .long asm_default_interrupt
vector091: .long asm_default_interrupt
vector092: .long asm_default_interrupt
vector093: .long asm_default_interrupt
vector094: .long asm_default_interrupt
vector095: .long asm_default_interrupt
vector096: .long asm_default_interrupt
vector097: .long asm_default_interrupt
vector098: .long asm_default_interrupt
vector099: .long asm_default_interrupt
vector100: .long asm_default_interrupt
vector101: .long asm_default_interrupt
vector102: .long asm_default_interrupt
vector103: .long asm_default_interrupt
vector104: .long asm_default_interrupt
vector105: .long asm_default_interrupt
vector106: .long asm_default_interrupt
vector107: .long asm_default_interrupt
vector108: .long asm_default_interrupt
vector109: .long asm_default_interrupt
vector110: .long asm_default_interrupt
vector111: .long asm_default_interrupt
vector112: .long asm_default_interrupt
vector113: .long asm_default_interrupt
vector114: .long asm_default_interrupt
vector115: .long asm_default_interrupt
vector116: .long asm_default_interrupt
vector117: .long asm_default_interrupt
vector118: .long asm_default_interrupt
vector119: .long asm_default_interrupt
vector120: .long asm_default_interrupt
vector121: .long asm_default_interrupt
vector122: .long asm_default_interrupt
vector123: .long asm_default_interrupt
vector124: .long asm_default_interrupt
vector125: .long asm_default_interrupt
vector126: .long asm_default_interrupt
vector127: .long asm_default_interrupt
vector128: .long asm_default_interrupt
vector129: .long asm_default_interrupt
vector130: .long asm_default_interrupt
vector131: .long asm_default_interrupt
vector132: .long asm_default_interrupt
vector133: .long asm_default_interrupt
vector134: .long asm_default_interrupt
vector135: .long asm_default_interrupt
vector136: .long asm_default_interrupt
vector137: .long asm_default_interrupt
vector138: .long asm_default_interrupt
vector139: .long asm_default_interrupt
vector140: .long asm_default_interrupt
vector141: .long asm_default_interrupt
vector142: .long asm_default_interrupt
vector143: .long asm_default_interrupt
vector144: .long asm_default_interrupt
vector145: .long asm_default_interrupt
vector146: .long asm_default_interrupt
vector147: .long asm_default_interrupt
vector148: .long asm_default_interrupt
vector149: .long asm_default_interrupt
vector150: .long asm_default_interrupt
vector151: .long asm_default_interrupt
vector152: .long asm_default_interrupt
vector153: .long asm_default_interrupt
vector154: .long asm_default_interrupt
vector155: .long asm_default_interrupt
vector156: .long asm_default_interrupt
vector157: .long asm_default_interrupt
vector158: .long asm_default_interrupt
vector159: .long asm_default_interrupt
vector160: .long asm_default_interrupt
vector161: .long asm_default_interrupt
vector162: .long asm_default_interrupt
vector163: .long asm_default_interrupt
vector164: .long asm_default_interrupt
vector165: .long asm_default_interrupt
vector166: .long asm_default_interrupt
vector167: .long asm_default_interrupt
vector168: .long asm_default_interrupt
vector169: .long asm_default_interrupt
vector170: .long asm_default_interrupt
vector171: .long asm_default_interrupt
vector172: .long asm_default_interrupt
vector173: .long asm_default_interrupt
vector174: .long asm_default_interrupt
vector175: .long asm_default_interrupt
vector176: .long asm_default_interrupt
vector177: .long asm_default_interrupt
vector178: .long asm_default_interrupt
vector179: .long asm_default_interrupt
vector180: .long asm_default_interrupt
vector181: .long asm_default_interrupt
vector182: .long asm_default_interrupt
vector183: .long asm_default_interrupt
vector184: .long asm_default_interrupt
vector185: .long asm_default_interrupt
vector186: .long asm_default_interrupt
vector187: .long asm_default_interrupt
vector188: .long asm_default_interrupt
vector189: .long asm_default_interrupt
vector190: .long asm_default_interrupt
vector191: .long asm_default_interrupt
vector192: .long asm_default_interrupt
vector193: .long asm_default_interrupt
vector194: .long asm_default_interrupt
vector195: .long asm_default_interrupt
vector196: .long asm_default_interrupt
vector197: .long asm_default_interrupt
vector198: .long asm_default_interrupt
vector199: .long asm_default_interrupt
vector200: .long asm_default_interrupt
vector201: .long asm_default_interrupt
vector202: .long asm_default_interrupt
vector203: .long asm_default_interrupt
vector204: .long asm_default_interrupt
vector205: .long asm_default_interrupt
vector206: .long asm_default_interrupt
vector207: .long asm_default_interrupt
vector208: .long asm_default_interrupt
vector209: .long asm_default_interrupt
vector210: .long asm_default_interrupt
vector211: .long asm_default_interrupt
vector212: .long asm_default_interrupt
vector213: .long asm_default_interrupt
vector214: .long asm_default_interrupt
vector215: .long asm_default_interrupt
vector216: .long asm_default_interrupt
vector217: .long asm_default_interrupt
vector218: .long asm_default_interrupt
vector219: .long asm_default_interrupt
vector220: .long asm_default_interrupt
vector221: .long asm_default_interrupt
vector222: .long asm_default_interrupt
vector223: .long asm_default_interrupt
vector224: .long asm_default_interrupt
vector225: .long asm_default_interrupt
vector226: .long asm_default_interrupt
vector227: .long asm_default_interrupt
vector228: .long asm_default_interrupt
vector229: .long asm_default_interrupt
vector230: .long asm_default_interrupt
vector231: .long asm_default_interrupt
vector232: .long asm_default_interrupt
vector233: .long asm_default_interrupt
vector234: .long asm_default_interrupt
vector235: .long asm_default_interrupt
vector236: .long asm_default_interrupt
vector237: .long asm_default_interrupt
vector238: .long asm_default_interrupt
vector239: .long asm_default_interrupt
vector240: .long asm_default_interrupt
vector241: .long asm_default_interrupt
vector242: .long asm_default_interrupt
vector243: .long asm_default_interrupt
vector244: .long asm_default_interrupt
vector245: .long asm_default_interrupt
vector246: .long asm_default_interrupt
vector247: .long asm_default_interrupt
vector248: .long asm_default_interrupt
vector249: .long asm_default_interrupt
vector250: .long asm_default_interrupt
vector251: .long asm_default_interrupt
vector252: .long asm_default_interrupt
vector253: .long asm_default_interrupt
vector254: .long asm_default_interrupt
vector255: .long asm_default_interrupt
/*===============================================================*\
| Start of code |
\*===============================================================*/
PUBLIC (start)
SYM(start):
move.w #0x3700,sr /* disable interrupts */
jmp start_init
/*===============================================================*\
| Sspurious interrupt counter |
\*===============================================================*/
.align 4
.data /* begin of data section */
PUBLIC (spurious_int_count)
SYM(spurious_int_count):
.long 0 /* spurious interrupt counter */
/*===============================================================*\
| Function: Default exception handler |
+-----------------------------------------------------------------+
| - stop and disable all interrupts |
| - loop forever |
\*===============================================================*/
.text /* start of text section */
.align 4
PUBLIC (asm_default_interrupt)
SYM(asm_default_interrupt):
nop
stop #0x3700 /* stop */
bra.w asm_default_interrupt /* loop forever */
/*===============================================================*\
| Function: Exception handler for spurious interrupts |
+-----------------------------------------------------------------+
| - count spurious interrupts |
\*===============================================================*/
.align 4
PUBLIC (asm_spurious_interrupt)
SYM(asm_spurious_interrupt):
add.l #1,spurious_int_count
rte
/*===============================================================*\
| Function: start_init |
+-----------------------------------------------------------------+
| - Disable all intterupts |
| - Setup the internal SRAM |
| - Initialize mcf548x peripherals |
| - Set initial stack pointer |
| - Boot RTEMS
\*===============================================================*/
.align 4
PUBLIC (start_init)
SYM(start_init):
move.l #0x01040100,d0 /* invalidate instruction/data/branch cache, disable all caches */
movec d0,cacr
move.l #_CoreSramBase0,d0 /* initialize RAMBAR0 */
add.l #0x21,d0 /* for code & data */
movec d0,rambar0
move.l #_CoreSramBase1,d0 /* initialize RAMBAR1 */
add.l #0x21,d0 /* for code & data */
movec d0,rambar1 /* movec d0,RAMBAR1 */
move.l #__MBAR,d0 /* initialize MBAR */
movec d0,mbar
move.l #_CoreSramBase1,d0 /* set sp to end of Core SRAM temporarily */
add.l #_CoreSramSize1,d0
move.l d0,sp
move.l #0,d0 /* initialize frame pointer */
movea.l d0,a6
jsr mcf548x_init /* Initialize mcf548x peripherals */
move.l #_SpInit,sp /* relocate sp */
clrl d0 /* clear d0 */
movel d0,a7@- /* environp == NULL */
movel d0,a7@- /* argv == NULL */
movel d0,a7@- /* argc == 0 */
jsr boot_card /* boot rtems */
movel a7@+,d0
movel a7@+,d0
movel a7@+,d0
exit_multitasking:
nop
nop
halt
bra exit_multitasking
.end /* end of start.S module */
c/src/lib/libbsp/m68k/genmcf548x/startup/bspclean.c
+60
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@@ -0,0 +1,60 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: bspclean.c |
+-----------------------------------------------------------------+
| The file contains the BSP cleanup code of the generic MCF548x |
| BSP. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
#include <rtems.h>
#include <bsp.h>
#include <rtems/bspIo.h>
void bsp_cleanup( void )
{
printk("\nRTEMS exited!\n");
for ( ;; )
{
asm volatile ( " nop " );
asm volatile ( " nop " );
}
}
c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
+323
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@@ -0,0 +1,323 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: bspstart.c |
+-----------------------------------------------------------------+
| The file contains the startup code of generic MCF548x BSP |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
#include <bsp.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <string.h>
char *HeapStart, *HeapEnd;
unsigned long _HeapSize;
extern uint32_t _CPU_cacr_shadow;
extern char _SdramBase[];
extern char _BootFlashBase[];
extern char _CodeFlashBase[];
extern char _SdramSize[];
extern char _BootFlashSize[];
extern char _CodeFlashSize[];
/*
* CPU-space access
*/
#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
#define m68k_set_acr0(_acr0) asm volatile ("movec %0,#0x0004" : : "d" (_acr0))
#define m68k_set_acr1(_acr1) asm volatile ("movec %0,#0x0005" : : "d" (_acr1))
#define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2))
#define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3))
/*
* Set initial cacr mode, mainly enables branch/intruction/data cache and switch off FPU.
*/
static uint32_t cacr_mode = (0 |
MCF548X_CACR_DEC | /* enable data cache */
MCF548X_CACR_BEC | /* enable branch cache */
MCF548X_CACR_IEC | /* enable instruction cache */
MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH) | /* set data cache mode to write-through */
MCF548X_CACR_DESB | /* enable data store buffer */
MCF548X_CACR_DDSP | /* data access only in supv. mode */
MCF548X_CACR_IDSP | /* instr. access only in supv. mode */
MCF548X_CACR_DF); /* disable FPU */
/*
* Coldfire cacr maintenance functions
*/
void _CPU_cacr_set_mode(uint32_t new_cacr_mode)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
cacr_mode = new_cacr_mode;
m68k_set_cacr(new_cacr_mode);
rtems_interrupt_enable(level);
}
/*
* There is no complete cache lock (only 2 ways of 4 can be locked)
*/
void _CPU_cache_freeze_data(void)
{
}
void _CPU_cache_unfreeze_data(void)
{
}
void _CPU_cache_freeze_instruction(void)
{
}
void _CPU_cache_unfreeze_instruction(void)
{
}
void _CPU_cache_enable_instruction(void)
{
cacr_mode &= ~(MCF548X_CACR_IDCM);
_CPU_cacr_set_mode(cacr_mode);
}
void _CPU_cache_disable_instruction(void)
{
cacr_mode |= MCF548X_CACR_IDCM;
_CPU_cacr_set_mode(cacr_mode);
}
void _CPU_cache_invalidate_entire_instruction(void)
{
cacr_mode |= MCF548X_CACR_ICINVA;
_CPU_cacr_set_mode(cacr_mode);
}
void _CPU_cache_invalidate_1_instruction_line(const void *addr)
{
asm volatile ("cpushl %%ic,(%0)" :: "a" (addr));
}
void _CPU_cache_enable_data(void)
{
cacr_mode &= ~MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
_CPU_cacr_set_mode(cacr_mode);
}
void _CPU_cache_disable_data(void)
{
cacr_mode |= MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
_CPU_cacr_set_mode(cacr_mode);
}
void _CPU_cache_invalidate_entire_data(void)
{
cacr_mode |= MCF548X_CACR_DCINVA;
_CPU_cacr_set_mode(cacr_mode);
}
void _CPU_cache_invalidate_1_data_line(const void *addr)
{
asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
}
void _CPU_cache_flush_1_data_line(const void *addr)
{
asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
}
void _CPU_cache_flush_entire_data(void)
{
register uint32_t way_cnt, set_cnt, addr;
asm volatile("nop");
for(way_cnt=0; way_cnt<4; way_cnt++)
{
for(addr=0,set_cnt=0; set_cnt<512; set_cnt++,addr+=0x10)
{
asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
}
addr=way_cnt;
}
}
/*
* Use the shared implementations of the following routines
*/
void bsp_predriver_hook()
{
/* Do nothing */
}
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, uint32_t, int );
void bsp_pretasking_hook(void); /* m68k version */
void bsp_calc_mem_layout()
{
/*
* these labels (!) are defined in the linker command file
* or when the linker is invoked
* NOTE: the information(size) is the address of the object,
* not the object otself
*/
extern char _TopRamReserved [];
extern char _WorkspaceBase [];
/*
* compute the memory layout:
* - first unused address is Workspace start
* - Heap starts at end of workspace
* - Heap ends at end of memory - reserved memory area
*/
Configuration.work_space_start = _WorkspaceBase;
HeapStart = ((char *)Configuration.work_space_start +
Configuration.work_space_size);
HeapEnd = (void *)(RAM_END - (uint32_t)_TopRamReserved);
_HeapSize = HeapEnd - HeapStart;
}
/*
* Coldfire acr and mmu settings
*/
void acr_mmu_mapping(void)
{
/*
* Cache disabled for internal register area (256 kB).
* Choose the smallest maskable size of 1MB.
*/
m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR)) |
MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF)) |
MCF548X_ACR_E |
MCF548X_ACR_SP /* supervisor protection */ |
MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
MCF548X_ACR_CM(CM_OFF_PRECISE));
#ifdef M5484FIREENGINE
/*
* Cache enabled for entire SDRAM (64 MB)
*/
m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase)) |
MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1)) |
MCF548X_ACR_E |
MCF548X_ACR_SP /* supervisor protection */ |
MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
/*
* Cache enabled for entire boot flash (2 MB)
*/
m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase)) |
MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1)) |
MCF548X_ACR_E |
MCF548X_ACR_SP /* supervisor protection */ |
MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
MCF548X_ACR_CM(CM_ON_COPYBACK));
/*
* Cache enabled for entire code flash (16 MB)
*/
m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase)) |
MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1)) |
MCF548X_ACR_E |
MCF548X_ACR_SP /* supervisor protection */ |
MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
MCF548X_ACR_CM(CM_ON_COPYBACK));
#endif
}
/*
* bsp_start
*
* This routine does the bulk of the system initialisation.
*/
void bsp_start( void )
{
extern char _RamSize[];
extern unsigned long _M68k_Ramsize;
_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
/*
* Allocate the memory for the RTEMS Work Space and Heap. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
bsp_calc_mem_layout();
/*
* do mapping of acr's and/or mmu
*/
acr_mmu_mapping();
/*
* Load the shadow variable of cacr with initial mode and write it to the cacr.
* Interrupts are still disabled, so there is no need for surrounding rtems_interrupt_enable()/rtems_interrupt_disable()
*/
_CPU_cacr_shadow = cacr_mode;
m68k_set_cacr(_CPU_cacr_shadow);
}
/*
* Get the XLB clock speed
*/
uint32_t get_CPU_clock_speed(void)
{
return (uint32_t)BSP_CPU_CLOCK_SPEED;
}
c/src/lib/libbsp/m68k/genmcf548x/startup/init548x.c
+317
View File
@@ -0,0 +1,317 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: init548x.c |
+-----------------------------------------------------------------+
| The file contains the c part of MCF548x init code |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
#include <rtems.h>
#include <bsp.h>
#define SYSTEM_PERIOD 10 /* system bus period in ns */
/* SDRAM Timing Parameters */
#define SDRAM_TWR 2 /* in clocks */
#define SDRAM_CASL 2.5 /* in clocks */
#define SDRAM_TRCD 20 /* in ns */
#define SDRAM_TRP 20 /* in ns */
#define SDRAM_TRFC 75 /* in ns */
#define SDRAM_TREFI 7800 /* in ns */
extern uint8_t _DataRom[];
extern uint8_t _DataRam[];
extern uint8_t _DataEnd[];
extern uint8_t _BssStart[];
extern uint8_t _BssEnd[];
extern uint8_t _BootFlashBase[];
extern uint8_t _CodeFlashBase[];
extern uint8_t _RamBase[];
extern uint32_t InterruptVectorTable[];
extern uint32_t _VectorRam[];
void gpio_init(void);
void fbcs_init(void);
void sdramc_init(void);
void mcf548x_init(void);
void mcf548x_init(void)
{
uint32_t n;
uint8_t *dp, *sp;
/* set XLB arbiter timeouts */
#ifdef M5484FIREENGINE
/* set XLB arbiter timeouts */
MCF548X_XLB_ADRTO = 0x00000100;
MCF548X_XLB_DATTO = 0x00000100;
MCF548X_XLB_BUSTO = 0x00000100;
#endif
gpio_init();
fbcs_init();
sdramc_init();
/* Copy the vector table to RAM */
if (_VectorRam != InterruptVectorTable)
{
for( n = 0; n < 256; n++)
{
_VectorRam[n] = InterruptVectorTable[n];
}
}
m68k_set_vbr((uint32_t)_VectorRam);
/* Move initialized data from ROM to RAM. */
if (_DataRom != _DataRam)
{
n = _DataEnd - _DataRam;
sp = (uint8_t *)_DataRom;
dp = (uint8_t *)_DataRam;
while(n--)
*dp++ = *sp++;
}
/* Zero uninitialized data */
if (_BssStart != _BssEnd)
{
n = _BssEnd - _BssStart;
sp = (uint8_t *)_BssStart;
while (n--)
*sp++ = 0;
}
}
/********************************************************************/
void
fbcs_init (void)
{
#ifdef M5484FIREENGINE
volatile uint32_t cscr, clk_ratio, fb_period, ws;
/* boot flash already valid ? */
if(!(MCF548X_FBCS_CSMR0 & MCF548X_FBCS_CSMR_V))
{
/*
* Boot Flash
*/
MCF548X_FBCS_CSAR0 = MCF548X_FBCS_CSAR_BA((uint32_t)(_BootFlashBase));
cscr = (0
| MCF548X_FBCS_CSCR_ASET(1)
| MCF548X_FBCS_CSCR_WRAH(0)
| MCF548X_FBCS_CSCR_RDAH(0)
| MCF548X_FBCS_CSCR_AA
| MCF548X_FBCS_CSCR_PS_16);
/*
* Determine the necessary wait states based on the defined system
* period (XLB clock period) and the CLKIN to XLB ratio.
* The boot flash has a max access time of 110ns.
*/
clk_ratio = (MCF548X_PCI_PCIGSCR >> 24) & 0x7;
fb_period = SYSTEM_PERIOD * clk_ratio;
ws = 110 / fb_period;
MCF548X_FBCS_CSCR0 = cscr | MCF548X_FBCS_CSCR_WS(ws);
MCF548X_FBCS_CSMR0 = (0
| MCF548X_FBCS_CSMR_BAM_2M
| MCF548X_FBCS_CSMR_V);
}
/* code flash already valid ? */
if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V))
{
/*
* Code Flash
*/
MCF548X_FBCS_CSAR1 = MCF548X_FBCS_CSAR_BA((uint32_t)(_CodeFlashBase));
/*
* Determine the necessary wait states based on the defined system
* period (XLB clock period) and the CLKIN to XLB ratio.
* The user/code flash has a max access time of 120ns.
*/
ws = 120 / fb_period;
MCF548X_FBCS_CSCR1 = cscr | MCF548X_FBCS_CSCR_WS(ws);
MCF548X_FBCS_CSMR1 = (0
| MCF548X_FBCS_CSMR_BAM_16M
| MCF548X_FBCS_CSMR_V);
}
#endif
}
/********************************************************************/
void
sdramc_init (void)
{
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(MCF548X_SDRAMC_SDCR & MCF548X_SDRAMC_SDCR_REF))
{
/*
* Basic configuration and initialization
*/
MCF548X_SDRAMC_SDRAMDS = (0
| MCF548X_SDRAMC_SDRAMDS_SB_E(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF548X_SDRAMC_SDRAMDS_SB_C(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF548X_SDRAMC_SDRAMDS_SB_A(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF548X_SDRAMC_SDRAMDS_SB_S(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
| MCF548X_SDRAMC_SDRAMDS_SB_D(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
);
MCF548X_SDRAMC_CS0CFG = (0
| MCF548X_SDRAMC_CSnCFG_CSBA((uint32_t)(_RamBase))
| MCF548X_SDRAMC_CSnCFG_CSSZ(MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE)
);
MCF548X_SDRAMC_SDCFG1 = (0
| MCF548X_SDRAMC_SDCFG1_SRD2RW(7)
| MCF548X_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
| MCF548X_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
| MCF548X_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5))
| MCF548X_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5))
| MCF548X_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5))
| MCF548X_SDRAMC_SDCFG1_WTLAT(3)
);
MCF548X_SDRAMC_SDCFG2 = (0
| MCF548X_SDRAMC_SDCFG2_BRD2PRE(4)
| MCF548X_SDRAMC_SDCFG2_BWT2RW(6)
| MCF548X_SDRAMC_SDCFG2_BRD2WT(7)
| MCF548X_SDRAMC_SDCFG2_BL(7)
);
/*
* Precharge and enable write to SDMR
*/
MCF548X_SDRAMC_SDCR = (0
| MCF548X_SDRAMC_SDCR_MODE_EN
| MCF548X_SDRAMC_SDCR_CKE
| MCF548X_SDRAMC_SDCR_DDR
| MCF548X_SDRAMC_SDCR_MUX(1)
| MCF548X_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
| MCF548X_SDRAMC_SDCR_IPALL
);
/*
* Write extended mode register
*/
MCF548X_SDRAMC_SDMR = (0
| MCF548X_SDRAMC_SDMR_BNKAD_LEMR
| MCF548X_SDRAMC_SDMR_AD(0x0)
| MCF548X_SDRAMC_SDMR_CMD
);
/*
* Write mode register and reset DLL
*/
MCF548X_SDRAMC_SDMR = (0
| MCF548X_SDRAMC_SDMR_BNKAD_LMR
| MCF548X_SDRAMC_SDMR_AD(0x163)
| MCF548X_SDRAMC_SDMR_CMD
);
/*
* Execute a PALL command
*/
MCF548X_SDRAMC_SDCR |=MCF548X_SDRAMC_SDCR_IPALL;
/*
* Perform two REF cycles
*/
MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
/*
* Write mode register and clear reset DLL
*/
MCF548X_SDRAMC_SDMR = (0
| MCF548X_SDRAMC_SDMR_BNKAD_LMR
| MCF548X_SDRAMC_SDMR_AD(0x063)
| MCF548X_SDRAMC_SDMR_CMD
);
/*
* Enable auto refresh and lock SDMR
*/
MCF548X_SDRAMC_SDCR &= ~MCF548X_SDRAMC_SDCR_MODE_EN;
MCF548X_SDRAMC_SDCR |= (0
| MCF548X_SDRAMC_SDCR_REF
| MCF548X_SDRAMC_SDCR_DQS_OE(0xF)
);
}
}
/********************************************************************/
void
gpio_init(void)
{
#ifdef M5484FIREENGINE
/*
* Enable Ethernet signals so that, if a cable is plugged into
* the ports, the lines won't be floating and potentially cause
* erroneous transmissions
*/
MCF548X_GPIO_PAR_FECI2CIRQ = (0
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17
);
MCF548X_GPIO_PAR_FECI2CIRQ = (0
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII
| MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07
);
#endif
}
c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds
+232
View File
@@ -0,0 +1,232 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: linkcmd |
+-----------------------------------------------------------------+
| The file contains the linker directives for the generic MCF548x |
| BSP to be used with an m5484FireEngine EVB to load and execute |
| code in the RAM. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
/*
* Location and size of on-chip devices
*/
_SdramBase = DEFINED(_SdramBase) ? _SdramBase : 0x00000000;
_SdramSize = DEFINED(_SdramSize) ? _SdramSize : (64 * 1024 * 1024);
_SysSramBase = DEFINED(_SysSramBase) ? _SysSramBase : __MBAR + 0x00010000;
_SysSramSize = DEFINED(_SysSramSize) ? _SysSramSize : (32 * 1024);
_McdapiBase = DEFINED(_McdapiBase) ? _McdapiBase : _SysSramBase;
_McdapiSize = DEFINED(_McdapiSize) ? _McdapiSize : (12 * 1024);
_CoreSramBase0 = DEFINED(_CoreSramBase0) ? _CoreSramBase0 : 0x20000000;
_CoreSramBase1 = DEFINED(_CoreSramBase1) ? _CoreSramBase1 : 0x20001000;
_CoreSramSize0 = DEFINED(_CoreSramSize0) ? _CoreSramSize0 : (4 * 1024);
_CoreSramSize1 = DEFINED(_CoreSramSize1) ? _CoreSramSize1 : (4 * 1024);
_BootFlashBase = DEFINED(_BootFlashBase) ? _BootFlashBase : 0xFF800000;
_BootFlashSize = DEFINED(_BootFlashSize) ? _BootFlashSize : (2 * 1024 * 1024);
_CodeFlashBase = DEFINED(_CodeFlashBase) ? _CodeFlashBase : 0xE0000000;
_CodeFlashSize = DEFINED(_CodeFlashSize) ? _CodeFlashSize : (16 * 1024 * 1024);
_VectorRam = DEFINED(_VectorRam) ? _VectorRam : _SdramBase;
_DataRam = DEFINED(_DataRam) ? _DataRam : _data_dest_start;
_DataRom = DEFINED(_DataRom) ? _DataRom : _data_src_start;
_DataEnd = DEFINED(_DataEnd) ? _DataEnd : _data_dest_end;
_BssStart = DEFINED(_BssStart) ? _BssStart : _clear_start;
_BssEnd = DEFINED(_BssEnd) ? _BssEnd : _clear_end;
_SpInit = DEFINED(_SpInit) ? _SpInit : _EndInitStackSpace;
_InitPc = DEFINED(_InitPc) ? _InitPc : _SdramBase + 0x400;
_InitStackSize = DEFINED(StackSize) ? StackSize : 0x800; /* 2 kB */
_TopRamReserved = DEFINED(_TopRamReserved) ? _TopRamReserved : 0;
_RamBase = DEFINED(_SdramBase) ? _SdramBase : _SdramBase;
_RamSize = DEFINED(_SdramSize) ? _SdramSize : _SdramSize;
_VBR = DEFINED(_VBR) ? _VBR : _RamBase;
__MBAR = DEFINED(__MBAR) ? __MBAR : 0x10000000;
ENTRY(start)
MEMORY
{
sdram : ORIGIN = 0x400 , LENGTH = 64M - 0x400
code_flash : ORIGIN = 0xE0000000, LENGTH = 16M
boot_flash : ORIGIN = 0xFF800000, LENGTH = 2M
}
SECTIONS
{
_header_offset = 0;
/*
* Text, data and bss segments .vectors
*/
.vectors : {
*(.vectors*)
} >sdram
.text : {
*(.text*)
*(.ram_code)
/*
* C++ constructors/destructors
*/
*(.gnu.linkonce.t.*)
/*
* Initialization and finalization code.
*
* Various files can provide initialization and finalization
* functions. crtbegin.o and crtend.o are two instances. The
* body of these functions are in .init and .fini sections. We
* accumulate the bodies here, and prepend function prologues
* from crti.o and function epilogues from crtn.o. crti.o must
* be linked first; crtn.o must be linked last. Because these
* are wildcards, it doesn't matter if the user does not
* actually link against crti.o and crtn.o; the linker won't
* look for a file to match a wildcard. The wildcard also
* means that it doesn't matter which directory crti.o and
* crtn.o are in.
*/
PROVIDE (_init = .);
*crti.o(.init)
*(.init)
*crtn.o(.init)
PROVIDE (_fini = .);
*crti.o(.fini)
*(.fini)
*crtn.o(.fini)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/*
* C++ constructors/destructors
*
* gcc uses crtbegin.o to find the start of the constructors
* and destructors so we make sure it is first. Because this
* is a wildcard, it doesn't matter if the user does not
* actually link against crtbegin.o; the linker won't look for
* a file to match a wildcard. The wildcard also means that
* it doesn't matter which directory crtbegin.o is in. The
* constructor and destructor list are terminated in
* crtend.o. The same comments apply to it.
*/
. = ALIGN (16);
*crtbegin.o(.ctors)
*(.ctors)
*crtend.o(.ctors)
*crtbegin.o(.dtors)
*(.dtors)
*crtend.o(.dtors)
/*
* Exception frame info
*/
. = ALIGN (16);
*(.eh_frame)
/*
* Read-only data
*/
. = ALIGN (16);
_rodata_start = . ;
*(.rodata*)
*(.gnu.linkonce.r*)
. = ALIGN (16);
*(.console_gdb_xfer)
*(.bootstrap_data)
. = ALIGN(16);
_estuff = .;
PROVIDE (_etext = .);
} >sdram
.data : {
/*.data : {*/
PROVIDE( _data_dest_start = . );
PROVIDE( _copy_start = .);
*(.data*)
*(.gnu.linkonce.d*)
*(.gcc_except_table)
*(.jcr)
. = ALIGN (16);
PROVIDE (_edata = .);
PROVIDE (_copy_end = .);
PROVIDE (_data_dest_end = . );
} >sdram
_data_src_start = _etext; /*LOADADDR(.data);*/
_data_src_end = _data_src_start + SIZEOF(.data);
.bss : {
PROVIDE (_clear_start = .);
*(.bss*)
*(COMMON)
. = ALIGN (16);
PROVIDE (end = .);
PROVIDE (_clear_end = .);
. = ALIGN (4);
PROVIDE (_StartInitStackSpace = .);
/*. = _StartInitStackSpace + _InitStackSize;*/
. += _InitStackSize;
PROVIDE (_EndInitStackSpace = .);
PROVIDE (_WorkspaceBase = .);
} >sdram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
PROVIDE (end_of_all = .);
}
c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds.m5484FireEngine.flash
+232
View File
@@ -0,0 +1,232 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: linkcmd.m5484FireEngine.flash |
+-----------------------------------------------------------------+
| The file contains the linker directives for the generic MCF548x |
| BSP to be used with an m5484FireEngine EVB to load and execute |
| code in the boot FLASH. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
/*
* Location and size of on-chip devices
*/
_SdramBase = DEFINED(_SdramBase) ? _SdramBase : 0x00000000;
_SdramSize = DEFINED(_SdramSize) ? _SdramSize : (64 * 1024 * 1024);
_SysSramBase = DEFINED(_SysSramBase) ? _SysSramBase : __MBAR + 0x00010000;
_SysSramSize = DEFINED(_SysSramSize) ? _SysSramSize : (32 * 1024);
_McdapiBase = DEFINED(_McdapiBase) ? _McdapiBase : _SysSramBase;
_McdapiSize = DEFINED(_McdapiSize) ? _McdapiSize : (12 * 1024);
_CoreSramBase0 = DEFINED(_CoreSramBase0) ? _CoreSramBase0 : 0x20000000;
_CoreSramBase1 = DEFINED(_CoreSramBase1) ? _CoreSramBase1 : 0x20001000;
_CoreSramSize0 = DEFINED(_CoreSramSize0) ? _CoreSramSize0 : (4 * 1024);
_CoreSramSize1 = DEFINED(_CoreSramSize1) ? _CoreSramSize1 : (4 * 1024);
_BootFlashBase = DEFINED(_BootFlashBase) ? _BootFlashBase : 0xFF800000;
_BootFlashSize = DEFINED(_BootFlashSize) ? _BootFlashSize : (2 * 1024 * 1024);
_CodeFlashBase = DEFINED(_CodeFlashBase) ? _CodeFlashBase : 0xE0000000;
_CodeFlashSize = DEFINED(_CodeFlashSize) ? _CodeFlashSize : (16 * 1024 * 1024);
_VectorRam = DEFINED(_VectorRam) ? _VectorRam : _SdramBase;
_DataRam = DEFINED(_DataRam) ? _DataRam : _data_dest_start;
_DataRom = DEFINED(_DataRom) ? _DataRom : _data_src_start;
_DataEnd = DEFINED(_DataEnd) ? _DataEnd : _data_dest_end;
_BssStart = DEFINED(_BssStart) ? _BssStart : _clear_start;
_BssEnd = DEFINED(_BssEnd) ? _BssEnd : _clear_end;
_SpInit = DEFINED(_SpInit) ? _SpInit : _EndInitStackSpace;
_InitPc = DEFINED(_InitPc) ? _InitPc : _SdramBase + 0x400;
_InitStackSize = DEFINED(StackSize) ? StackSize : 0x2000; /* 8 kB */
_TopRamReserved = DEFINED(_TopRamReserved) ? _TopRamReserved : 0;
_RamBase = DEFINED(_SdramBase) ? _SdramBase : _SdramBase;
_RamSize = DEFINED(_SdramSize) ? _SdramSize : _SdramSize;
_VBR = DEFINED(_VBR) ? _VBR : _RamBase;
__MBAR = DEFINED(__MBAR) ? __MBAR : 0x10000000;
ENTRY(start)
MEMORY
{
sdram : ORIGIN = 0x400 , LENGTH = 64M - 0x400
code_flash : ORIGIN = 0xE0000000, LENGTH = 16M
boot_flash : ORIGIN = 0xFF800000, LENGTH = 2M
}
SECTIONS
{
_header_offset = 0;
/*
* Text, data and bss segments .vectors
*/
.vectors : {
*(.vectors*)
} >boot_flash
.text : {
*(.text*)
*(.ram_code)
/*
* C++ constructors/destructors
*/
*(.gnu.linkonce.t.*)
/*
* Initialization and finalization code.
*
* Various files can provide initialization and finalization
* functions. crtbegin.o and crtend.o are two instances. The
* body of these functions are in .init and .fini sections. We
* accumulate the bodies here, and prepend function prologues
* from crti.o and function epilogues from crtn.o. crti.o must
* be linked first; crtn.o must be linked last. Because these
* are wildcards, it doesn't matter if the user does not
* actually link against crti.o and crtn.o; the linker won't
* look for a file to match a wildcard. The wildcard also
* means that it doesn't matter which directory crti.o and
* crtn.o are in.
*/
PROVIDE (_init = .);
*crti.o(.init)
*(.init)
*crtn.o(.init)
PROVIDE (_fini = .);
*crti.o(.fini)
*(.fini)
*crtn.o(.fini)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/*
* C++ constructors/destructors
*
* gcc uses crtbegin.o to find the start of the constructors
* and destructors so we make sure it is first. Because this
* is a wildcard, it doesn't matter if the user does not
* actually link against crtbegin.o; the linker won't look for
* a file to match a wildcard. The wildcard also means that
* it doesn't matter which directory crtbegin.o is in. The
* constructor and destructor list are terminated in
* crtend.o. The same comments apply to it.
*/
. = ALIGN (16);
*crtbegin.o(.ctors)
*(.ctors)
*crtend.o(.ctors)
*crtbegin.o(.dtors)
*(.dtors)
*crtend.o(.dtors)
/*
* Exception frame info
*/
. = ALIGN (16);
*(.eh_frame)
/*
* Read-only data
*/
. = ALIGN (16);
_rodata_start = . ;
*(.rodata*)
*(.gnu.linkonce.r*)
. = ALIGN (16);
*(.console_gdb_xfer)
*(.bootstrap_data)
. = ALIGN(16);
_estuff = .;
PROVIDE (_etext = .);
} >boot_flash
.data : AT(LOADADDR(.text) + SIZEOF(.text)) {
/*.data : {*/
PROVIDE( _data_dest_start = . );
PROVIDE( _copy_start = .);
*(.data*)
*(.gnu.linkonce.d*)
*(.gcc_except_table)
*(.jcr)
. = ALIGN (16);
PROVIDE (_edata = .);
PROVIDE (_copy_end = .);
PROVIDE (_data_dest_end = . );
} >sdram
_data_src_start = _etext; /*LOADADDR(.data);*/
_data_src_end = _data_src_start + SIZEOF(.data);
.bss : {
PROVIDE (_clear_start = .);
*(.bss*)
*(COMMON)
. = ALIGN (16);
PROVIDE (end = .);
PROVIDE (_clear_end = .);
. = ALIGN (4);
PROVIDE (_StartInitStackSpace = .);
/*. = _StartInitStackSpace + _InitStackSize;*/
. += _InitStackSize;
PROVIDE (_EndInitStackSpace = .);
PROVIDE (_WorkspaceBase = .);
} >sdram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
PROVIDE (end_of_all = .);
}
c/src/lib/libbsp/m68k/genmcf548x/timer/timer.c
+94
View File
@@ -0,0 +1,94 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: timer.c |
+-----------------------------------------------------------------+
| The file contains the diagnostic timer code of generic MCF548x |
| BSP. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
/*
* Timer Init
*
* Use the second slice timer (SLT1) as the diagnostic timer.
*/
#include <rtems.h>
#include <bsp.h>
#include <mcf548x/mcf548x.h>
rtems_boolean Timer_driver_Find_average_overhead;
static uint32_t microsecond_timer_value = 0;
void Timer_initialize(void)
{
MCF548X_SLT_SLTCNT1 = 0xFFFFFFFF;
MCF548X_SLT_SCR1 |= (MCF548X_SLT_SCR_TEN | MCF548X_SLT_SCR_RUN);
}
/*
* Return timer value in microsecond units
* XLB clock 100 MHz / 1us is equal to 100 counts
*/
int
Read_timer(void)
{
microsecond_timer_value = (0xFFFFFFFF - MCF548X_SLT_SCNT1)/100;
return microsecond_timer_value;
}
/*
* Empty function call used in loops to measure basic cost of looping
* in Timing Test Suite.
*/
rtems_status_code
Empty_function(void)
{
return RTEMS_SUCCESSFUL;
}
void
Set_find_average_overhead(rtems_boolean find_flag)
{
Timer_driver_Find_average_overhead = find_flag;
}