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cpukit: Add basic riscv32 architecture port v3
Limitations: * NO FPU support [TODO] Update #3109
This commit is contained in:
Hesham Almatary authored and 
Hesham Almatary committed
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@@ -0,0 +1,26 @@
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include $(top_srcdir)/automake/compile.am
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include_rtemsdir = $(includedir)/rtems
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include_rtems_HEADERS = rtems/asm.h
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include_rtems_scoredir = $(includedir)/rtems/score
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include_rtems_score_HEADERS = rtems/score/cpu.h
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include_rtems_score_HEADERS += rtems/score/cpuatomic.h
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include_rtems_score_HEADERS += rtems/score/cpuimpl.h
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include_rtems_score_HEADERS += rtems/score/cpu_asm.h
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include_rtems_score_HEADERS += rtems/score/types.h
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include_rtems_score_HEADERS += rtems/score/riscv.h
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include_rtems_score_HEADERS += rtems/score/riscv-utility.h
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noinst_LIBRARIES = libscorecpu.a
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libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
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libscorecpu_a_SOURCES = cpu.c
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libscorecpu_a_SOURCES += riscv-exception-handler.S
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libscorecpu_a_SOURCES += riscv-exception-default.c
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libscorecpu_a_SOURCES += riscv-exception-frame-print.c
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libscorecpu_a_SOURCES += riscv-context-switch.S
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libscorecpu_a_SOURCES += riscv-context-initialize.c
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libscorecpu_a_SOURCES += riscv-context-validate.S
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libscorecpu_a_SOURCES += riscv-context-volatile-clobber.S
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/automake/local.am
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@@ -0,0 +1,124 @@
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/*
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* riscv32 CPU Dependent Source
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*
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* Copyright (c) 2015 University of York.
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* Hesham ALmatary <hesham@alumni.york.ac.uk>
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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#include <rtems/score/cpu.h>
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/* bsp_start_vector_table_begin is the start address of the vector table
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* containing addresses to ISR Handlers. It's defined at the BSP linkcmds
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* and may differ from one BSP to another.
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*/
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extern char bsp_start_vector_table_begin[];
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void init(void);
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void fini(void);
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void _init()
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{
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}
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void _fini()
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{
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}
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/**
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* @brief Performs processor dependent initialization.
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*/
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void _CPU_Initialize(void)
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{
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/* Do nothing */
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}
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void _CPU_ISR_Set_level(uint32_t level)
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{
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/* Do nothing */
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}
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uint32_t _CPU_ISR_Get_level( void )
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{
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/* Do nothing */
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return 0;
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}
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void _CPU_ISR_install_raw_handler(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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/* Do nothing */
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}
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void _CPU_ISR_install_vector(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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proc_ptr *table =
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(proc_ptr *) bsp_start_vector_table_begin;
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proc_ptr current_handler;
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ISR_Level level;
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_ISR_Local_disable( level );
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current_handler = table [vector];
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/* The current handler is now the old one */
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if (old_handler != NULL) {
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*old_handler = (proc_ptr) current_handler;
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}
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/* Write only if necessary to avoid writes to a maybe read-only
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* memory */
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if (current_handler != new_handler) {
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table [vector] = new_handler;
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}
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_ISR_Local_enable( level );
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}
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void _CPU_Install_interrupt_stack( void )
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{
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/* Do nothing */
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}
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void *_CPU_Thread_Idle_body( uintptr_t ignored )
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{
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do {
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} while (1);
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return NULL;
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}
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@@ -0,0 +1,67 @@
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/*
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*
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* Copyright (c) 2015 University of York.
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* Hesham Almatary <hesham@alumni.york.ac.uk>
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*
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* COPYRIGHT (c) 1989-2006.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <string.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/riscv-utility.h>
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#include <rtems/score/interr.h>
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void _CPU_Context_Initialize(
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Context_Control *context,
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void *stack_area_begin,
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size_t stack_area_size,
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uint32_t new_level,
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void (*entry_point)( void ),
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bool is_fp,
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void *tls_area
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)
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{
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uintptr_t stack = ((uintptr_t) stack_area_begin);
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/* Account for red-zone */
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uintptr_t stack_high = stack + stack_area_size - RISCV_GCC_RED_ZONE_SIZE;
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memset(context, 0, sizeof(*context));
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/* Stack Pointer - sp/x2 */
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context->x[2] = stack_high;
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/* Frame Pointer - fp/x8 */
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context->x[8] = stack_high;
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/* Return Address - ra/x1 */
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context->x[1] = (uintptr_t) entry_point;
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/* Enable interrupts and FP */
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context->mstatus = MSTATUS_FS | MSTATUS_MIE;
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}
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@@ -0,0 +1,139 @@
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/*
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* riscv32 CPU Dependent Source
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*
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* Copyright (c) 2015 University of York.
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* Hesham ALmatary <hesham@alumni.york.ac.uk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/score/cpu.h>
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.section .text, "ax"
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.align 4
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# define LREG lw
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# define SREG sw
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PUBLIC(_CPU_Context_switch)
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PUBLIC(_CPU_Context_restore)
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PUBLIC(_CPU_Context_restore_fp)
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PUBLIC(_CPU_Context_save_fp)
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PUBLIC(restore)
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SYM(_CPU_Context_switch):
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/* Disable interrupts and store all registers */
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csrr t0, mstatus
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SREG t0, (32 * CPU_SIZEOF_POINTER)(a0)
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csrci mstatus, MSTATUS_MIE
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SREG x1, (1 * CPU_SIZEOF_POINTER)(a0)
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SREG x2, (2 * CPU_SIZEOF_POINTER)(a0)
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SREG x3, (3 * CPU_SIZEOF_POINTER)(a0)
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SREG x4, (4 * CPU_SIZEOF_POINTER)(a0)
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SREG x5, (5 * CPU_SIZEOF_POINTER)(a0)
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SREG x6, (6 * CPU_SIZEOF_POINTER)(a0)
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SREG x7, (7 * CPU_SIZEOF_POINTER)(a0)
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SREG x8, (8 * CPU_SIZEOF_POINTER)(a0)
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SREG x9, (9 * CPU_SIZEOF_POINTER)(a0)
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SREG x10, (10 * CPU_SIZEOF_POINTER)(a0)
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SREG x11, (11 * CPU_SIZEOF_POINTER)(a0)
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SREG x12, (12 * CPU_SIZEOF_POINTER)(a0)
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SREG x13, (13 * CPU_SIZEOF_POINTER)(a0)
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SREG x14, (14 * CPU_SIZEOF_POINTER)(a0)
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SREG x15, (15 * CPU_SIZEOF_POINTER)(a0)
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SREG x16, (16 * CPU_SIZEOF_POINTER)(a0)
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SREG x17, (17 * CPU_SIZEOF_POINTER)(a0)
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SREG x18, (18 * CPU_SIZEOF_POINTER)(a0)
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SREG x19, (19 * CPU_SIZEOF_POINTER)(a0)
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SREG x20, (20 * CPU_SIZEOF_POINTER)(a0)
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SREG x21, (21 * CPU_SIZEOF_POINTER)(a0)
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SREG x22, (22 * CPU_SIZEOF_POINTER)(a0)
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SREG x23, (23 * CPU_SIZEOF_POINTER)(a0)
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SREG x24, (24 * CPU_SIZEOF_POINTER)(a0)
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SREG x25, (25 * CPU_SIZEOF_POINTER)(a0)
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SREG x26, (26 * CPU_SIZEOF_POINTER)(a0)
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SREG x27, (27 * CPU_SIZEOF_POINTER)(a0)
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SREG x28, (28 * CPU_SIZEOF_POINTER)(a0)
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SREG x29, (28 * CPU_SIZEOF_POINTER)(a0)
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SREG x30, (30 * CPU_SIZEOF_POINTER)(a0)
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SREG x31, (31 * CPU_SIZEOF_POINTER)(a0)
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SYM(restore):
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LREG x1, (1 * CPU_SIZEOF_POINTER)(a1)
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LREG x2, (2 * CPU_SIZEOF_POINTER)(a1)
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LREG x3, (3 * CPU_SIZEOF_POINTER)(a1)
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LREG x4, (4 * CPU_SIZEOF_POINTER)(a1)
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LREG x5, (5 * CPU_SIZEOF_POINTER)(a1)
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LREG x6, (6 * CPU_SIZEOF_POINTER)(a1)
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LREG x7, (7 * CPU_SIZEOF_POINTER)(a1)
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LREG x8, (8 * CPU_SIZEOF_POINTER)(a1)
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LREG x9, (9 * CPU_SIZEOF_POINTER)(a1)
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LREG x10, (10 * CPU_SIZEOF_POINTER)(a1)
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/* Skip a1/x11 */
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LREG x12, (12 * CPU_SIZEOF_POINTER)(a1)
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LREG x13, (13 * CPU_SIZEOF_POINTER)(a1)
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LREG x14, (14 * CPU_SIZEOF_POINTER)(a1)
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LREG x15, (15 * CPU_SIZEOF_POINTER)(a1)
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LREG x16, (16 * CPU_SIZEOF_POINTER)(a1)
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LREG x17, (17 * CPU_SIZEOF_POINTER)(a1)
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LREG x18, (18 * CPU_SIZEOF_POINTER)(a1)
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LREG x19, (19 * CPU_SIZEOF_POINTER)(a1)
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LREG x20, (20 * CPU_SIZEOF_POINTER)(a1)
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LREG x21, (21 * CPU_SIZEOF_POINTER)(a1)
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LREG x22, (22 * CPU_SIZEOF_POINTER)(a1)
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LREG x23, (23 * CPU_SIZEOF_POINTER)(a1)
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LREG x24, (24 * CPU_SIZEOF_POINTER)(a1)
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LREG x25, (25 * CPU_SIZEOF_POINTER)(a1)
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LREG x26, (26 * CPU_SIZEOF_POINTER)(a1)
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LREG x27, (27 * CPU_SIZEOF_POINTER)(a1)
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LREG x28, (28 * CPU_SIZEOF_POINTER)(a1)
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LREG x29, (29 * CPU_SIZEOF_POINTER)(a1)
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LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
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/* Load mstatus */
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LREG x31, (32 * CPU_SIZEOF_POINTER)(a1)
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csrw mstatus, x31
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LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
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LREG x11, (11 * CPU_SIZEOF_POINTER)(a1)
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ret
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SYM(_CPU_Context_restore):
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mv a1, a0
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j restore
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/* TODO no FP support for riscv32 yet */
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SYM(_CPU_Context_restore_fp):
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nop
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SYM(_CPU_Context_save_fp):
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nop
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File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,50 @@
|
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/*
|
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* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <rtems/asm.h>
|
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.section .text
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PUBLIC(_CPU_Context_volatile_clobber)
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SYM(_CPU_Context_volatile_clobber):
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.macro clobber_register reg
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addi t0, t0, -1
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mv \reg, t0
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.endm
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clobber_register a0
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clobber_register a1
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clobber_register a2
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clobber_register a3
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clobber_register a4
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clobber_register a5
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clobber_register a6
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ret
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@@ -0,0 +1,39 @@
|
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/*
|
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* Copyright (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <rtems/score/cpu.h>
|
||||
#include <rtems/fatal.h>
|
||||
#include <stdio.h>
|
||||
|
||||
void _RISCV_Exception_default(uint32_t vector, CPU_Exception_frame *frame);
|
||||
|
||||
void _RISCV_Exception_default(uint32_t vector, CPU_Exception_frame *frame)
|
||||
{
|
||||
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
|
||||
}
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include <rtems/score/cpu.h>
|
||||
#include <rtems/bspIo.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
|
||||
{
|
||||
int i;
|
||||
|
||||
for ( i = 0; i < 32; ++i ) {
|
||||
printk( "x%02i = 0x%016" PRIx32 "\n", i, frame->x[i]);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,120 @@
|
||||
/**
|
||||
* @file rtems/asm.h
|
||||
*
|
||||
* This include file attempts to address the problems
|
||||
* caused by incompatible flavors of assemblers and
|
||||
* toolsets. It primarily addresses variations in the
|
||||
* use of leading underscores on symbols and the requirement
|
||||
* that register names be preceded by a %.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: The spacing in the use of these macros
|
||||
* is critical to them working as advertised.
|
||||
*
|
||||
* This file is based on similar code found in newlib available
|
||||
* from ftp.cygnus.com. The file which was used had no copyright
|
||||
* notice. This file is freely distributable as long as the source
|
||||
* of the file is noted. This file is:
|
||||
*
|
||||
* Copyright (c) 2015 University of York.
|
||||
* Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||
*
|
||||
*
|
||||
* COPYRIGHT (c) 1994-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_ASM_H
|
||||
#define __RISCV_ASM_H
|
||||
|
||||
/*
|
||||
* Indicate we are in an assembly file and get the basic CPU definitions.
|
||||
*/
|
||||
|
||||
#ifndef ASM
|
||||
#define ASM
|
||||
#endif
|
||||
#include <rtems/score/cpuopts.h>
|
||||
#include <rtems/score/riscv.h>
|
||||
|
||||
/*
|
||||
* Recent versions of GNU cpp define variables which indicate the
|
||||
* need for underscores and percents. If not using GNU cpp or
|
||||
* the version does not support this, then you will obviously
|
||||
* have to define these as appropriate.
|
||||
*/
|
||||
|
||||
#ifndef __USER_LABEL_PREFIX__
|
||||
#define __USER_LABEL_PREFIX__ _
|
||||
#endif
|
||||
|
||||
#ifndef __REGISTER_PREFIX__
|
||||
#define __REGISTER_PREFIX__
|
||||
#endif
|
||||
|
||||
/* ANSI concatenation macros. */
|
||||
|
||||
#define CONCAT1(a, b) CONCAT2(a, b)
|
||||
#define CONCAT2(a, b) a ## b
|
||||
|
||||
/* Use the right prefix for global labels. */
|
||||
|
||||
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
|
||||
|
||||
/* Use the right prefix for registers. */
|
||||
|
||||
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
|
||||
|
||||
/*
|
||||
* define macros for all of the registers on this CPU
|
||||
*
|
||||
* EXAMPLE: #define d0 REG (d0)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Define macros to handle section beginning and ends.
|
||||
*/
|
||||
#define BEGIN_CODE_DCL .text
|
||||
#define END_CODE_DCL
|
||||
#define BEGIN_DATA_DCL .data
|
||||
#define END_DATA_DCL
|
||||
#define BEGIN_CODE .text
|
||||
#define END_CODE
|
||||
#define BEGIN_DATA
|
||||
#define END_DATA
|
||||
#define BEGIN_BSS
|
||||
#define END_BSS
|
||||
#define END
|
||||
|
||||
/*
|
||||
* Following must be tailor for a particular flavor of the C compiler.
|
||||
* They may need to put underscores in front of the symbols.
|
||||
*/
|
||||
|
||||
#define PUBLIC(sym) .global SYM (sym)
|
||||
#define EXTERN(sym) .extern SYM (sym)
|
||||
#define TYPE_FUNC(sym) .type SYM (sym), %function
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,90 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief riscv32 Assembly File
|
||||
*
|
||||
* Very loose template for an include file for the cpu_asm.? file
|
||||
* if it is implemented as a ".S" file (preprocessed by cpp) instead
|
||||
* of a ".s" file (preprocessed by gm4 or gasp).
|
||||
*/
|
||||
|
||||
/*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_CPU_ASM_H
|
||||
#define _RTEMS_SCORE_CPU_ASM_H
|
||||
|
||||
/* pull in the generated offsets */
|
||||
|
||||
/*
|
||||
#include <rtems/score/offsets.h>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hardware General Registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Hardware Floating Point Registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Hardware Control Registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Calling Convention
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Temporary registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Floating Point Registers - SW Conventions
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
/*
|
||||
* Temporary floating point registers
|
||||
*/
|
||||
|
||||
/* put something here */
|
||||
|
||||
#endif
|
||||
|
||||
/* end of file */
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* COPYRIGHT (c) 2012-2013 Deng Hengyi.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
|
||||
#define _RTEMS_SCORE_ATOMIC_CPU_H
|
||||
|
||||
#include <rtems/score/cpustdatomic.h>
|
||||
|
||||
#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
|
||||
@@ -0,0 +1,51 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief CPU Port Implementation API
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_CPUIMPL_H
|
||||
#define _RTEMS_SCORE_CPUIMPL_H
|
||||
|
||||
#include <rtems/score/cpu.h>
|
||||
|
||||
#define CPU_PER_CPU_CONTROL_SIZE 0
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* _RTEMS_SCORE_CPUIMPL_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,66 @@
|
||||
/**
|
||||
* @file rtems/score/riscv.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains information pertaining to the riscv32 processor.
|
||||
*
|
||||
* COPYRIGHT (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* Based on code with the following copyright...
|
||||
* COPYRIGHT (c) 1989-1999, 2010.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_RISCV_H
|
||||
#define _RTEMS_SCORE_RISCV_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This file contains the information required to build
|
||||
* RTEMS for a particular member of the RISCV family.
|
||||
* It does this by setting variables to indicate which
|
||||
* implementation dependent features are present in a particular
|
||||
* member of the family.
|
||||
*
|
||||
* This is a good place to list all the known CPU models
|
||||
* that this port supports and which RTEMS CPU model they correspond
|
||||
* to.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Define the name of the CPU family and specific model.
|
||||
*/
|
||||
|
||||
#define CPU_NAME "RISCV"
|
||||
#define CPU_MODEL_NAME "RISCV"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _RTEMS_SCORE_RISCV_H */
|
||||
@@ -0,0 +1,70 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief riscv32 Architecture Types API
|
||||
*/
|
||||
|
||||
/*
|
||||
* This include file contains type definitions pertaining to the
|
||||
* RISC-V processor family.
|
||||
*
|
||||
* COPYRIGHT (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_SCORE_TYPES_H
|
||||
#define _RTEMS_SCORE_TYPES_H
|
||||
|
||||
#include <rtems/score/basedefs.h>
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @addtogroup ScoreCPU
|
||||
*/
|
||||
/**@{**/
|
||||
|
||||
/*
|
||||
* This section defines the basic types for this processor.
|
||||
*/
|
||||
|
||||
/** Type that can store a 32-bit integer or a pointer. */
|
||||
typedef uintptr_t CPU_Uint32ptr;
|
||||
|
||||
typedef uint16_t Priority_bit_map_Word;
|
||||
typedef void riscv_isr;
|
||||
typedef void ( *riscv_isr_entry )( void );
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !ASM */
|
||||
|
||||
#endif
|
||||
Reference in new issue
Block a user