mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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add MC_DMA support to MCF548x
This commit is contained in:
Thomas Doerfler
@@ -1,3 +1,11 @@
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2009-10-15 Thomas Doefler <thomas.doerfler@embedded-brains.de>
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* Makefile.am, mcf548x/mcdma/MCD_dma.h, mcf548x/mcdma/MCD_dmaApi.c,
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* mcf548x/mcdma/MCD_progCheck.h, mcf548x/mcdma/MCD_tasks.c,
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* mcf548x/mcdma/MCD_tasksInit.c, mcf548x/mcdma/MCD_tasksInit.h,
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* mcf548x/mcdma/ReleaseNotes.txt, mcf548x/mcdma/mcdma_glue.c,
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* mcf548x/mcdma/mcdma_glue.h: add MC_DMA support
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2009-10-08 Thomas Doefler <thomas.doerfler@embedded-brains.de>
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* mcf5282/include/mcf5282.h: add missing (x) params to four
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@@ -168,6 +168,16 @@ if mcf548x
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## mcf548x/include
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include_mcf548xdir = $(includedir)/mcf548x
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include_mcf548x_HEADERS = mcf548x/include/mcf548x.h
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## mcf548x/mcdma
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noinst_PROGRAMS += mcf548x/mcdma.rel
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include_mcf548x_HEADERS += mcf548x/mcdma/MCD_progCheck.h mcf548x/mcdma/MCD_dma.h \
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mcf548x/mcdma/MCD_tasksInit.h mcf548x/mcdma/mcdma_glue.h
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mcf548x_mcdma_rel_SOURCES = mcf548x/mcdma/MCD_dmaApi.c mcf548x/mcdma/MCD_tasksInit.c \
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mcf548x/mcdma/MCD_tasks.c mcf548x/mcdma/mcdma_glue.c
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mcf548x_mcdma_rel_CPPFLAGS = $(AM_CPPFLAGS)
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mcf548x_mcdma_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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endif
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include $(srcdir)/preinstall.am
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@@ -0,0 +1,362 @@
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/*
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* File: MCD_dma.h
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* Purpose: Main header file for multi-channel DMA API.
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*
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* Notes:
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*/
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#ifndef _MCD_API_H
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#define _MCD_API_H
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/*
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* Turn Execution Unit tasks ON (#define) or OFF (#undef)
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*/
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#define MCD_INCLUDE_EU
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/*
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* Number of DMA channels
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*/
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#define NCHANNELS 16
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/*
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* Total number of variants
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*/
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#ifdef MCD_INCLUDE_EU
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#define NUMOFVARIANTS 6
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#else
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#define NUMOFVARIANTS 4
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#endif
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/*
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* Define sizes of the various tables
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*/
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#define TASK_TABLE_SIZE (NCHANNELS*32)
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#define VAR_TAB_SIZE (128)
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#define CONTEXT_SAVE_SIZE (128)
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#define FUNCDESC_TAB_SIZE (256)
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#ifdef MCD_INCLUDE_EU
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#define FUNCDESC_TAB_NUM 16
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#else
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#define FUNCDESC_TAB_NUM 1
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#endif
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#ifndef DEFINESONLY
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/*
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* Portability typedefs
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*/
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typedef int s32;
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typedef unsigned int u32;
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typedef short s16;
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typedef unsigned short u16;
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typedef char s8;
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typedef unsigned char u8;
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/*
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* These structures represent the internal registers of the
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* multi-channel DMA
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*/
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struct dmaRegs_s {
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u32 taskbar; /* task table base address register */
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u32 currPtr;
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u32 endPtr;
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u32 varTablePtr;
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u16 dma_rsvd0;
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u16 ptdControl; /* ptd control */
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u32 intPending; /* interrupt pending register */
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u32 intMask; /* interrupt mask register */
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u16 taskControl[16]; /* task control registers */
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u8 priority[32]; /* priority registers */
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u32 initiatorMux; /* initiator mux control */
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u32 taskSize0; /* task size control register 0. */
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u32 taskSize1; /* task size control register 1. */
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u32 dma_rsvd1; /* reserved */
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u32 dma_rsvd2; /* reserved */
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u32 debugComp1; /* debug comparator 1 */
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u32 debugComp2; /* debug comparator 2 */
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u32 debugControl; /* debug control */
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u32 debugStatus; /* debug status */
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u32 ptdDebug; /* priority task decode debug */
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u32 dma_rsvd3[31]; /* reserved */
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};
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typedef volatile struct dmaRegs_s dmaRegs;
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#endif
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/*
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* PTD contrl reg bits
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*/
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#define PTD_CTL_TSK_PRI 0x8000
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#define PTD_CTL_COMM_PREFETCH 0x0001
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/*
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* Task Control reg bits and field masks
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*/
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#define TASK_CTL_EN 0x8000
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#define TASK_CTL_VALID 0x4000
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#define TASK_CTL_ALWAYS 0x2000
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#define TASK_CTL_INIT_MASK 0x1f00
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#define TASK_CTL_ASTRT 0x0080
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#define TASK_CTL_HIPRITSKEN 0x0040
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#define TASK_CTL_HLDINITNUM 0x0020
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#define TASK_CTL_ASTSKNUM_MASK 0x000f
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/*
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* Priority reg bits and field masks
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*/
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#define PRIORITY_HLD 0x80
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#define PRIORITY_PRI_MASK 0x07
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/*
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* Debug Control reg bits and field masks
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*/
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#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
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#define DBG_CTL_AUTO_ARM 0x00008000
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#define DBG_CTL_BREAK 0x00004000
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#define DBG_CTL_COMP1_TYP_MASK 0x00003800
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#define DBG_CTL_COMP2_TYP_MASK 0x00000070
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#define DBG_CTL_EXT_BREAK 0x00000004
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#define DBG_CTL_INT_BREAK 0x00000002
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/*
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* PTD Debug reg selector addresses
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* This reg must be written with a value to show the contents of
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* one of the desired internal register.
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*/
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#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
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#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
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have initiators asserted */
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/*
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* General return values
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*/
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#define MCD_OK 0
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#define MCD_ERROR -1
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#define MCD_TABLE_UNALIGNED -2
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#define MCD_CHANNEL_INVALID -3
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/*
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* MCD_initDma input flags
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*/
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#define MCD_RELOC_TASKS 0x00000001
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#define MCD_NO_RELOC_TASKS 0x00000000
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#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
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/*
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* MCD_dmaStatus Status Values for each channel
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*/
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#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
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#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
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#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
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#define MCD_PAUSED 4 /* DMA active but it is currently paused */
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#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
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#define MCD_DONE 6 /* the most recent DMA has completed. */
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/*
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* MCD_startDma parameter defines
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*/
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/*
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* Constants for the funcDesc parameter
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*/
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/* Byte swapping: */
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#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
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#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
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#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
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each 32-bit data value being DMAed.*/
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#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
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16-bit half of each 32-bit data value DMAed */
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#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
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#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
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/* CRCing: */
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#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
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#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
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#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
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#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
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#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
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#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
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#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
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/*
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* Constants for the flags parameter
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*/
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#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
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#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
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#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
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#define MCD_TT_FLAGS_MASK 0x000000ff
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#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
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#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
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#define MCD_CHAIN_DMA /* TBD */
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#define MCD_EU_DMA /* TBD */
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#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
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#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
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/* these flags are valid for MCD_startDma and the chained buffer descriptors */
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#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
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#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
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#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
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#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
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last byte of data in buffer */
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#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
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prior to performing the DMA. */
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/* Defines for the FEC buffer descriptor control/status word*/
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#define MCD_FEC_BUF_READY 0x8000
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#define MCD_FEC_WRAP 0x2000
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#define MCD_FEC_INTERRUPT 0x1000
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#define MCD_FEC_END_FRAME 0x0800
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/*
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* Defines for general intuitiveness
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*/
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#define MCD_TRUE 1
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#define MCD_FALSE 0
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/*
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* Three different cases for destination and source.
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*/
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#define MINUS1 -1
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#define ZERO 0
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#define PLUS1 1
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#ifndef DEFINESONLY
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/* Task Table Entry struct*/
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typedef struct {
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u32 TDTstart; /* task descriptor table start */
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u32 TDTend; /* task descriptor table end */
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u32 varTab; /* variable table start */
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u32 FDTandFlags; /* function descriptor table start and flags */
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volatile u32 descAddrAndStatus;
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volatile u32 modifiedVarTab;
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u32 contextSaveSpace; /* context save space start */
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u32 literalBases;
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} TaskTableEntry;
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/* Chained buffer descriptor */
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typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
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struct MCD_bufDesc_struct {
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u32 flags; /* flags describing the DMA */
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u32 csumResult; /* checksum from checksumming performed since last checksum reset */
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s8 *srcAddr; /* the address to move data from */
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s8 *destAddr; /* the address to move data to */
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s8 *lastDestAddr; /* the last address written to */
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u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
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MCD_bufDesc *next; /* next buffer descriptor in chain */
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u32 info; /* private information about this descriptor; DMA does not affect it */
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};
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/* Progress Query struct */
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typedef volatile struct MCD_XferProg_struct {
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s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
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s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
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u32 dmaSize; /* the amount of data transferred for the current buffer */
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MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
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} MCD_XferProg;
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/* FEC buffer descriptor */
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typedef volatile struct MCD_bufDescFec_struct {
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u16 statCtrl;
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u16 length;
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u32 dataPointer;
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} MCD_bufDescFec;
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/*************************************************************************/
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/*
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* API function Prototypes - see MCD_dmaApi.c for further notes
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*/
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/*
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* MCD_startDma starts a particular kind of DMA .
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*/
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int MCD_startDma (
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int channel, /* the channel on which to run the DMA */
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s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
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s16 srcIncr, /* the amount to increment the source address per transfer */
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s8 *destAddr, /* the address to move data to */
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s16 destIncr, /* the amount to increment the destination address per transfer */
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u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
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u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
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u32 initiator, /* what device initiates the DMA */
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int priority, /* priority of the DMA */
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u32 flags, /* flags describing the DMA */
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u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
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);
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/*
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* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
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* registers, relocating and creating the appropriate task structures, and
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* setting up some global settings
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*/
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int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
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/*
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* MCD_dmaStatus() returns the status of the DMA on the requested channel.
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*/
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int MCD_dmaStatus (int channel);
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/*
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* MCD_XferProgrQuery() returns progress of DMA on requested channel
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*/
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int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
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/*
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* MCD_killDma() halts the DMA on the requested channel, without any
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* intention of resuming the DMA.
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*/
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int MCD_killDma (int channel);
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/*
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* MCD_continDma() continues a DMA which as stopped due to encountering an
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* unready buffer descriptor.
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*/
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int MCD_continDma (int channel);
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/*
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* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
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* running on that channel).
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*/
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int MCD_pauseDma (int channel);
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/*
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* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
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* running on that channel).
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*/
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int MCD_resumeDma (int channel);
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/*
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* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
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*/
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int MCD_csumQuery (int channel, u32 *csum);
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/*
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* MCD_getCodeSize provides the packed size required by the microcoded task
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* and structures.
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*/
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int MCD_getCodeSize(void);
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/*
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* MCD_getVersion provides a pointer to a version string and returns a
|
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* version number.
|
||||
*/
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int MCD_getVersion(char **longVersion);
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||||
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||||
/* macro for setting a location in the variable table */
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#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
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/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
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so I'm avoiding surrounding it with "do {} while(0)" */
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#endif /* DEFINESONLY */
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#endif /* _MCD_API_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,5 @@
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||||
/* This file is autogenerated. Do not change */
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#define CURRBD 4
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#define DCOUNT 6
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||||
#define DESTPTR 5
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#define SRCPTR 7
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,224 @@
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/*
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* File: MCD_tasksInit.c
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||||
* Purpose: Functions for initializing variable tables of different
|
||||
* types of tasks.
|
||||
*
|
||||
* Notes:
|
||||
*/
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||||
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||||
/*
|
||||
* Do not edit!
|
||||
*/
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||||
|
||||
#include "MCD_dma.h"
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||||
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||||
extern dmaRegs *MCD_dmaBar;
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||||
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||||
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||||
/*
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||||
* Task 0
|
||||
*/
|
||||
|
||||
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
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||||
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||||
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
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||||
MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
|
||||
MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
|
||||
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
|
||||
MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 1
|
||||
*/
|
||||
|
||||
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 2
|
||||
*/
|
||||
|
||||
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
|
||||
MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
|
||||
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
|
||||
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
|
||||
MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
|
||||
MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 3
|
||||
*/
|
||||
|
||||
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 4
|
||||
*/
|
||||
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 5
|
||||
*/
|
||||
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
|
||||
MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
|
||||
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
|
||||
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
#ifndef MCD_TSK_INIT_H
|
||||
#define MCD_TSK_INIT_H 1
|
||||
|
||||
/*
|
||||
* Do not edit!
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Task 0
|
||||
*/
|
||||
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 1
|
||||
*/
|
||||
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 2
|
||||
*/
|
||||
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 3
|
||||
*/
|
||||
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 4
|
||||
*/
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 5
|
||||
*/
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
#endif /* MCD_TSK_INIT_H */
|
||||
@@ -0,0 +1,26 @@
|
||||
Multi-channel DMA API Release Notes
|
||||
|
||||
Version 0.3
|
||||
|
||||
* MCD_INCLUDE_EU functionality supported(microcode changes for all tasks
|
||||
except ethernet).
|
||||
* Fixed bug when using MCD_END_FRAME which would cause the DMA to transfer
|
||||
zero bytes and then complete.
|
||||
* Code cleanup.
|
||||
|
||||
|
||||
Version 0.2 (Slight Update)
|
||||
|
||||
* Modified casts and task table implementations that were causing
|
||||
warnings (and even errors on certain compilers)
|
||||
* Cosmetic changes to clean up MCD_dmaApi.c and MCD_dma.h
|
||||
* Fixed table declarations so that MCD_tasks.c will compile if
|
||||
MCD_INCLUDE_EU is defined (Note: EU functionality still not supported)
|
||||
|
||||
Version 0.1 (Initial release)
|
||||
|
||||
Alpha version
|
||||
MCD_INCLUDE_EU functionality not supported.
|
||||
MCD_INCLUDE_JBIG not supported.
|
||||
|
||||
|
||||
@@ -0,0 +1,225 @@
|
||||
/*===============================================================*\
|
||||
| Project: RTEMS generic MCF548x BSP |
|
||||
+-----------------------------------------------------------------+
|
||||
| Copyright (c) 2004-2009 |
|
||||
| Embedded Brains GmbH |
|
||||
| Obere Lagerstr. 30 |
|
||||
| D-82178 Puchheim |
|
||||
| Germany |
|
||||
| rtems@embedded-brains.de |
|
||||
+-----------------------------------------------------------------+
|
||||
| The license and distribution terms for this file may be |
|
||||
| found in the file LICENSE in this distribution or at |
|
||||
| |
|
||||
| http://www.rtems.com/license/LICENSE. |
|
||||
| |
|
||||
+-----------------------------------------------------------------+
|
||||
| this file contains glue functions to the Freescale MC_DMA API |
|
||||
\*===============================================================*/
|
||||
#include <rtems.h>
|
||||
#include <rtems/error.h>
|
||||
#include <bsp.h>
|
||||
#include <mcf548x/mcf548x.h>
|
||||
#include <mcf548x/MCD_dma.h>
|
||||
|
||||
#define MCDMA_INT_ENABLE(reg,chan) (reg &= ~(1 << (chan)))
|
||||
#define MCDMA_INT_DISABLE(reg,chan) (reg |= (1 << (chan)))
|
||||
#define MCDMA_CLEAR_IEVENT(reg,chan) (reg = (1 << (chan)))
|
||||
|
||||
#define MCDMA_INT_BIT_IMPL 0x0000FFFF /* implemented IRQ sources (bitmask for IPEND... */
|
||||
#define MCDMA_IRQ_VECTOR (48+64)
|
||||
#define MCDMA_IRQ_LEVEL (2)
|
||||
#define MCDMA_IRQ_PRIORITY (2)
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_irq_enable
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| enable interrupt for given task number |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
int mcdma_channo /* task number to enable */
|
||||
)
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
if (0 != ((1UL<<mcdma_channo) & MCDMA_INT_BIT_IMPL)) {
|
||||
rtems_interrupt_disable(level);
|
||||
/*
|
||||
* valid task number
|
||||
* enable interrupt in mcdma mask
|
||||
*/
|
||||
MCDMA_INT_ENABLE(MCF548X_DMA_DIMR,mcdma_channo);
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
}
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_irq_disable
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| disable interrupt for given task number |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
int mcdma_channo /* task number to disable */
|
||||
)
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
if (0 != ((1UL<<mcdma_channo) & MCDMA_INT_BIT_IMPL)) {
|
||||
rtems_interrupt_disable(level);
|
||||
/*
|
||||
* valid task number
|
||||
* disable interrupt in mcdma mask
|
||||
*/
|
||||
MCDMA_INT_DISABLE(MCF548X_DMA_DIMR,mcdma_channo);
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
void (*the_handler)(void *param);
|
||||
void *the_param;
|
||||
} mcdma_glue_irq_handlers_t;
|
||||
|
||||
mcdma_glue_irq_handlers_t mcdma_glue_irq_handlers[32];
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_irq_install
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| install given function as mcdma interrupt handler |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
int mcdma_channo, /* task number for handler */
|
||||
void (*the_handler)(void *), /* function to call */
|
||||
void *the_param
|
||||
)
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
{
|
||||
if (0 != ((1UL<<mcdma_channo) & MCDMA_INT_BIT_IMPL)) {
|
||||
/*
|
||||
* valid task number
|
||||
* install handler
|
||||
*/
|
||||
mcdma_glue_irq_handlers[mcdma_channo].the_handler = the_handler;
|
||||
mcdma_glue_irq_handlers[mcdma_channo].the_param = the_param;
|
||||
}
|
||||
}
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
rtems_isr mcdma_glue_irq_dispatcher
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| general mcdma interrupt handler/dispatcher |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
rtems_vector_number v /* irq specific handle (not used) */
|
||||
|
||||
)
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
{
|
||||
uint32_t pending;
|
||||
int curr_channo;
|
||||
|
||||
pending = MCF548X_DMA_DIPR & ~MCF548X_DMA_DIMR;
|
||||
curr_channo = 0;
|
||||
while (pending != 0) {
|
||||
if ((pending & (1UL<<curr_channo)) != 0) {
|
||||
if (mcdma_glue_irq_handlers[curr_channo].the_handler == NULL) {
|
||||
/*
|
||||
* This should never happen. we have a pending IRQ but no handler
|
||||
* let's clear this pending bit
|
||||
*/
|
||||
MCDMA_CLEAR_IEVENT(MCF548X_DMA_DIPR,curr_channo);
|
||||
}
|
||||
else {
|
||||
/*
|
||||
* call proper handler
|
||||
*/
|
||||
mcdma_glue_irq_handlers[curr_channo].the_handler
|
||||
(mcdma_glue_irq_handlers[curr_channo].the_param);
|
||||
}
|
||||
/*
|
||||
* clear this bit in our pending copy
|
||||
* and go to next bit
|
||||
*/
|
||||
pending &= ~(1<<curr_channo);
|
||||
}
|
||||
curr_channo++;
|
||||
}
|
||||
}
|
||||
|
||||
static bool mcdma_glue_is_initialized = false;
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_init
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| initialize the mcdma module (if not yet done): |
|
||||
| - load code |
|
||||
| - initialize registers |
|
||||
| - initialize bus arbiter |
|
||||
| - initialize interrupt control |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void *sram_base /* base address for SRAM, to be used for DMA task */
|
||||
)
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
{
|
||||
rtems_isr_entry old_handler;
|
||||
if (!mcdma_glue_is_initialized) {
|
||||
mcdma_glue_is_initialized = true;
|
||||
|
||||
MCD_initDma((dmaRegs *)&MCF548X_DMA_TASKBAR,
|
||||
sram_base,
|
||||
MCD_TT_FLAGS_DEF);
|
||||
|
||||
/*
|
||||
* initialize interrupt dispatcher
|
||||
*/
|
||||
if(rtems_interrupt_catch(mcdma_glue_irq_dispatcher,
|
||||
MCDMA_IRQ_VECTOR,
|
||||
&old_handler)) {
|
||||
rtems_panic ("Can't attach MFC548x MCDma interrupt handler\n");
|
||||
}
|
||||
MCF548X_INTC_ICRn(MCDMA_IRQ_VECTOR - 64) =
|
||||
MCF548X_INTC_ICRn_IL(MCDMA_IRQ_LEVEL) |
|
||||
MCF548X_INTC_ICRn_IP(MCDMA_IRQ_PRIORITY);
|
||||
|
||||
MCF548X_INTC_IMRH &= ~(1 << (MCDMA_IRQ_VECTOR % 32));
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,106 @@
|
||||
/*===============================================================*\
|
||||
| Project: RTEMS generic MFC548x BSP |
|
||||
+-----------------------------------------------------------------+
|
||||
| Copyright (c) 2004-2009 |
|
||||
| Embedded Brains GmbH |
|
||||
| Obere Lagerstr. 30 |
|
||||
| D-82178 Puchheim |
|
||||
| Germany |
|
||||
| rtems@embedded-brains.de |
|
||||
+-----------------------------------------------------------------+
|
||||
| The license and distribution terms for this file may be |
|
||||
| found in the file LICENSE in this distribution or at |
|
||||
| |
|
||||
| http://www.rtems.com/license/LICENSE. |
|
||||
| |
|
||||
+-----------------------------------------------------------------+
|
||||
| this file declares glue functions to the Freescale Mcdma API |
|
||||
\*===============================================================*/
|
||||
#ifndef _MCDMA_GLUE_H
|
||||
#define _MCDMA_GLUE_H
|
||||
|
||||
#include <rtems.h>
|
||||
#include <mcf548x/mcf548x.h>
|
||||
|
||||
#define MCDMA_CLR_PENDING(chan) (MCF548X_DMA_DIPR = (1 << (chan)))
|
||||
#define MCDMA_GET_PENDING(chan) (MCF548X_DMA_DIPR & (1 << (chan)))
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_irq_enable
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| enable interrupt for given task number |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
int mcdma_taskno /* task number to enable */
|
||||
);
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_irq_disable
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| disable interrupt for given task number |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
int mcdma_taskno /* task number to disable */
|
||||
);
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_irq_install
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| install given function as mcdma interrupt handler |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
int mcdma_taskno, /* task number for handler */
|
||||
void (*the_handler)(rtems_irq_hdl_param), /* function to call */
|
||||
void *the_param
|
||||
);
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
|
||||
/*=========================================================================*\
|
||||
| Function: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void mcdma_glue_init
|
||||
(
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Purpose: |
|
||||
| initialize the mcdma module (if not yet done): |
|
||||
| - load code |
|
||||
| - initialize registers |
|
||||
| - initialize bus arbiter |
|
||||
| - initialize interrupt control |
|
||||
+---------------------------------------------------------------------------+
|
||||
| Input Parameters: |
|
||||
\*-------------------------------------------------------------------------*/
|
||||
void *sram_base /* base address for SRAM, to be used for DMA task */
|
||||
);
|
||||
/*-------------------------------------------------------------------------*\
|
||||
| Return Value: |
|
||||
| none |
|
||||
\*=========================================================================*/
|
||||
|
||||
#endif /* _MCDMA_GLUE_H */
|
||||
@@ -101,4 +101,20 @@ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mcf548x/$(dirstamp)
|
||||
$(PROJECT_INCLUDE)/mcf548x/mcf548x.h: mcf548x/include/mcf548x.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/mcf548x.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/mcf548x.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mcf548x/MCD_progCheck.h: mcf548x/mcdma/MCD_progCheck.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/MCD_progCheck.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/MCD_progCheck.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mcf548x/MCD_dma.h: mcf548x/mcdma/MCD_dma.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/MCD_dma.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/MCD_dma.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mcf548x/MCD_tasksInit.h: mcf548x/mcdma/MCD_tasksInit.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/MCD_tasksInit.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/MCD_tasksInit.h
|
||||
|
||||
$(PROJECT_INCLUDE)/mcf548x/mcdma_glue.h: mcf548x/mcdma/mcdma_glue.h $(PROJECT_INCLUDE)/mcf548x/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mcf548x/mcdma_glue.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mcf548x/mcdma_glue.h
|
||||
endif
|
||||
|
||||
Reference in New Issue
Block a user